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Chapter 2 DEFECTS, FAULTS, FAULT MODELS Elena Gramatová1) , Raimund Ubar2) , Witold Pleskacz3) , Mária Fischerová1) Institute of Informatics, Slovak Academy of Sciences, Bratislava, Slovakia Tallinn University of Technology, Tallinn, Estonia Warsaw University of Technology, Warsaw, Poland Abstract: The main evaluation criterion of digital circuits testing is fault coverage. Low efficiency of the classical stuck_at fault model in real defect coverage calculation for MOS logic has initiated the need of new fault models. This chapter contains basic terminology, defects classification, fault modelling and their manifestation at logical and higher levels for digital logic, memories and microprocessors, as well. Key words: defect, fault, error, defect analysis, fault coverage, fault model, Boolean algebra, digital circuits, combinational and sequential logic, RAM memories, microprocessors 1. CLASSIFICATION OF FAULTS (IISAS, TTU) Defects can happen anywhere on die, on one or multiple layers, packages, boards, etc.; they can consume arbitrary areas and can have arbitrary electrical properties. Quality of designing circuits or systems is evaluated by defect coverage estimation. But we cannot measure them directly therefore they have to be modelled at the higher abstracted level – faults. All defects can be observed at the logical, current or timing levels. The main goal of fault modelling is to reduce the infinite set of possible defect behaviours into a finite set of faults. Fault models are used in test pattern generation (TPG) and bridge the gap between the physical reality and 2 Chapter 2 mathematical abstracts. Some TPG algorithms and methods are described in chapter 3. The basic terminology and the current used fault models are introduced in this chapter. The primary fault model – the stuck_at fault model is still the most often used fault model and it is a base of many automatic TPG systems. Different properties like fault equivalence and fault dominance are explained in part 1.2 of the chapter. The fault model complexity can be reduced by fault collapsing methods based on the mentioned properties. The issues and problems with fault redundancy and fault masking will be also discussed. Faults and fault models should mirror real defects in the circuit and system design, therefore defects have to be modelled in the right way and faults have to be classified. Two approaches for defect analysis can be used – using some mathematical models based on the Boolean algebra and simulation based techniques at the transistor level. A short introduction into the Boolean differential algebra will be given and the concept of a generic Boolean function with a fault will be presented to generalize the fault modelling of arbitrary defects. This model can map an arbitrary physical defect onto a higher (in this case, logic) level. The functional fault model based on Boolean differential equations and its mapping to physical defects presented in a single cell or on interconnections is described in subchapter 2. The second methodology in defect modelling is a process of defect analysis and probability evaluation of defects occurrence based on simulation at the transistor level. The general approach based on the whole circuit analysis is computationally very expensive and impractical. An alternative approach – functionality of gates from a standard cell library is analysed for all possible physical defects using transistor-level simulation. These methods together with some examples based on the 0,8 CMOS technology are presented in subchapter 3. Modelling of faults is closely related to the modelling of the circuit. In the design hierarchy, the level refers to the degree of abstraction. Thus we can think about the behavioural level (sometimes referred to as a high level), the register transfer level (RTL) and the transistor and other lower levels (referred to as component levels). Finally, some fault models that may not fit any of the design hierarchies. A typical example is the quiescent current (IDDQ) discrepancy in faulty circuits discussed in chapter 4. Different fault models at the higher level like the fault models defined for RTL descriptions, high-level components and microprocessors are discussed in subchapter 4 of the chapter. Subchapter 5 targeted to defects and fault models in memory blocks closes the chapter. The correct fault models require understanding the memory design, and as memory designers invent new circuit topologies, new fault models are required. 2. DEFECTS, FAULTS, FAULT MODELS 1.1 3 Defects, faults, errors – definitions (IISAS) The terms defect, error and fault are sometimes used in confusing ways in the literature of testing. In this book we will use them according the definitions defined and used in [1,6]. Generally, a defect (failure mechanism) in an electronic system is the unintended difference between the implemented hardware and its intended design; defect causes deviation from device specifications. Defects occur either during manufacture or during use of devices. Besides of incorrect design (result: functional faults), some typical defects in VLSI chips can be produced by: 1. Manufacturing process - e.g. missing contact, parasitic transistors, gate-oxide shorts, oxide break-down, metal-to silicon shorts, missing or faulty components, broken or shorted tracks, etc. 2. Process fabrication marginalities: line width variation, etc. 3. Material and age defects: bulk defects (cracks, crystal imperfections), surface impurities, dielectric breakdown, electro-migration, etc. 4. Packaging: contact degradation, seal leaks, etc. 5. Environmental influence: e.g. temperature related defects, high humidity, vibration, electrical stress, crosstalk, radiation, etc. A fault is defined as a representation of the defect at the abstracted function level (electrical, Boolean or functional malfunction). The difference between a defect and a fault is rather subtle. It means imperfections in the hardware and function respectively. In general, a physical defect in a chip can produce multiple faults and no single test type detects all defects. Error is a wrong output signal produced by a defective system (an incorrect response in the behaviour of the circuit). An error is an effect whose cause is some defect. Example 2-1: One signal input line of the basic cell NAND (with 2 inputs) is shorted to ground. How the basic terms are represented? Solution: Defect: the short between the input and ground nodes. Fault: the faulty input line has the permanent value 0 – stuck_at 0. Error: for input pattern (11), the output value is 1, although the correct output value is 0. Notice that the error is not permanent; if a pattern has one or both values 0; there is no error in the output. Localization and determination causes of defects are used for improvements of specifications, design, verification, manufacturing and testing processes. All is aimed to reduction of the defect level and manufacturing yield. Therefore defect detection and their localization need to be solved in the testing processes. Defects are modelled and the trade-off in fault modelling is to develop models that are as simple as possible to use in test generation, but they cover as high a percentage of physical defects as 4 Chapter 2 possible. The first problem is to solve defects manifestation and their classification. In this context, defects can be divided roughly into two basic groups [4]: 1. Soft defects – defects which cause speed fault; show up at high speed or produce some temperature; they need two or more test patterns for their activation and error observation (require carefully constructed transitions for defect activation); require tests to be applied at speed. They are e.g. high resistance bridges, x-coupling, tunnelling break, etc. 2. Hard defects – defects manifested at all frequencies; a test can be applied at slow speed and they need only one-pattern test set. As an example: bridge with a low resistance, etc. Defects have to be measured and modelled into the faults. They can be observable in different measurable manners based on: - changing a logical value on a circuit node (we speak about Boolean testing, or testing at the logical level), - increasing the steady state supply current (we speak about IDDQ testing), - changing time specifications (we speak about at-speed testing and delay testing), - variation one or a set of parameters such that its specific distribution in a circuit makes it fall out of specifications. It is known all these groups are not identical, therefore all the mentioned testing types have to be used for achieving high quality of a circuit under test (CUT). Testing effectiveness is expressed by fault coverage therefore fault models have to be defined carefully. Nowadays, the following fault models are used in the testing process [1, 5]: a) Stuck-at fault model - it is a type of logical faults affecting logical signal states; it is the most spread fault model for digital circuits at the logical level. b) Bridging faults or simply bridges or shorts occur between two and group of signals otherwise unconnected nodes. Two types of bridging faults are recognised: inter-gate and intra-gate shorts. Shorts are the dominant cause of faults in modern CMOS processes. Some shorts occur when dust or extra material is deposited during fabrication [2,3]. c) Opens - the fault means that a physical line in a circuit is broken. The resulting unconnected node is not lied to either VDD or Gnd; occurrence of such defects can provide “memory effect” or delay faults. The opens can happen due to improper etching, masking error, electro-migration, etc. There are two types of opens – narrow and large [2,3]. d) Delay faults mean that timing specifications are not fulfilled. The gate or path delay faults have to be investigated [1,2]. e) Parametric faults; they are defects causing changes in CUT parameters (e.g. current, VDD and Gnd voltage, power consumption, temperature, 2. DEFECTS, FAULTS, FAULT MODELS 5 etc.). Generally, the parametric faults change the values of electrical parameters of active or passive devices from their nominal or expected values. There are some examples of parametric faults: the threshold voltage of a transistor (active device) and values of resistors and capacitors (passive devices), inductance changes, Vt shifts. The parametric defects create the most difficult fault class mainly in CMOS ICs. Typically these faults are neither sensitive to SAF or delay fault testing nor IDDQ testing. They are mostly speed-related failures detected in the field when customers use the parts at temperatures or power supply voltages different that what was done at production test. The parametric faults are not described and analysed in the book. Some features, measurements, natures, etc. of the parametric faults testing are presented e.g. in [2, 3, 7, 8, 9, 10]. 1.1.1 Stuck_at faults The stuck_at fault (SAF) is modelled by assigning the fixed value (0 or1) to a signal line in CUT. A signal line means an input or output line of a logic gate or a flip-flop. SAF is assumed to affect only the interconnection between gates. Each connecting line can have two types of faults: stuck_at 0 (SAF0) or stuck_at 1 (SAF1). One example with the gate OR is shown in Figure 2-1. SAF0 Figure 2-1. SAF0 at one of the OR inputs. The SAF model is the most often used fault model in automatic TPG systems (ATPG). Obviously, the following presumption is considered in ATPGs: only a single and permanent fault is considered in CUT at a time. Three properties characterize a single SAF: 1. only one line is faulty, 2. the faulty line is permanently set either 0 or 1, 3. the fault can be at an input or output of a gate. The SAF model is the industrial standard since 1959. The death of the SAF model has been predicted, but several reasons and properties have been persuaded that the SAF model continues in testing. There are its [5]: - simplicity: SAF is easy to apply to CUT, - tractability: can be applied to millions of gates at once, - logic behaviour: fault behaviour can be determined logically, so simulation is straightforward and deterministic, - measurability: detection/non detection are easy, 6 Chapter 2 adaptability: can apply SAF on gates, systems, transistors, RTL, etc. However, some defects cannot be covered by the single SAF model, mainly in CMOS technologies [e.g. 10, 11, 12, 13]. It is disadvantage of the SAF model. Sometimes the multiple SAFs are used but they doesn’t significantly increase the defect coverage enough. The major disadvantage is a large number of possible multiple SAF combinations (3n-1, where n is the number of CUT nodes). The ATPG algorithms and fault simulation techniques for multiple SAFs are much more complex and not as well developed. - 1.1.2 Bridging faults Bridging faults cover all defects and failure mechanisms that cause unintended electrical connections across two or more circuit nodes. Physical causes of the shorts can be produced by: - extra conducting material: e.g. photolitographic printing error, conductive particle contamination, etc., - missing insulating material: printing error, gate-oxide defect causing pinhole, insulating particle contamination, etc. Bridges have non-linear or linear properties with resistance from near zero to > 1 M. The bridge with infinite resistance has no effect. There exists some critical resistance above which a given bridge has no effect. The typical values for [5]: - logical critical resistance is 100 to 2 k, - timing critical resistance is 5 k to 10 k. Bridging faults can be classified into two rough groups: shorts either at the logic terminals of a gate (inter-gate shorts) or at transistor nodes (intragate shorts). The inter-gate shorts can produce sequential behaviour if the short creates feedback. One illustration example of inter-gate shorts is in Figure 2-2. Figure 2-2. Inter-gate shorts: combinatorial and feedback. The combinatorial short in the TPG process are obviously classified as: a) the wired-AND short (type “AND” or “0” dominated), see Figure 2-3. b) the wired-OR short (type “OR” or “1” dominated) ), see Figure 2-3, c) indeterminate, depending upon the technology in which CUT is implemented. 2. DEFECTS, FAULTS, FAULT MODELS 1 1 0 0 7 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 Figure 2-3. Combinatorial inter-gate shorts. Non-feedback bridging fault coverage detected by a SAF test is normally very high [1]. Considering the bridging faults at the transistor level (intragate shorts) obviously 6 shorts between all transistor terminals (gate, drain, source and substrate) and shorts to VDD and Gnd nodes are tested (two examples are in Figure 2-4). Their manifestation depends on resistance caused by the real existing short. Some intra-gate shorts can be mapped to the SAF model. VDD Figure 2-4. Intra-gate shorts. Example 2-2: Figure 2-5 illustrates a transistor level schematic of the NAND gate in the CMOS technology with 3 bridging defects d1,d2, d3. VDD V a b A B p1 1 p D pD2 d P1 2 n1 n d3 d2 n12 n Gnd 2 V Figure 2-5. Intra-gate shorts. s s Z Solution: In the simplistic analysis using the assumption that the defect resistance is substantially low to the „on“ resistance of a transistor. Then, defects d1 and d3 can be modelled by SAF, but d2 not. 8 Chapter 2 Defect d1: this defect causes a short between the output y and power supply VDD. Assuming that the „on“ resistance of n1 and n2 transistors is substantially high compared to defect resistance, the defect results in SAF 1 on y. Then using the test vector (a,b)=11 defect d 1 will be detected. The similar explanation can be done for defect d3. Defect d2: can be detected by SAF test vectors under the assumption that resistance of the defect and „on“ resistance of the n1 transistor is substantially smaller than „on“ resistance the p2 transistor. test vector (a,b)=10 causes transistors p2 and n1 to conduct. The analysis of some selected bridging faults and their modelling and detecting by classical Boolean (described in part 3 of this chapter) and IDDQ testing (in chapter 4). Defects modelling using Boolean algebra are described in part 2 of the chapter. Other non-linear bridges exist – e.g. gate oxide shorts, parasitic transistor leakage, leaky pn junctions, non-metallic particles. Gate-oxide shorts (GOS) have been recognised for some time to be a dominant mode of CMOS circuit failure. This failure due to the oxide layer breaks down obviously done during or after fabrication. The gate beneath the poly-silicon layer of the gate isolates it from the other terminals; illustrative edample is shown in Figure 2.6) [3]. GATE GATE DRAIN SOURCE SUBSTRATE DRAIN SOURCE SUBSTRATE DEFECT Figure 2-6. Illustration of gate-oxide short. Bridge defects detection is more efficient with IDDQ testing. Correct Boolean functionality exists for signal node bridge defects when the defect exceed a critical resistance. Critical resistance varied with W/L ratios and input logic patterns [14]. General classification of bridging faults was done by their natural links either to classical Boolean or alternative IDDQ testing by Hawkins [14] and he classified the bridging faults into the next classes: - Bridge type I – Combinational defect class: This category contains defects that cause the transistor nodes bridges, logic gate input/output 2. DEFECTS, FAULTS, FAULT MODELS - - 9 signal node to power bus bridges and power to bus-to-power bridges. These defects have various physical causes and include ohmic and nonohmic shorts. Bridge type II – Layout defect class: These defects occur at a variety of locations and as, opposed to the type I category, they require identification from the layout. These defects include bridges between two or more logic signal nodes or between logic gate I/O to transistor nodes. However, they have similar IDDQ and Boolean responses on common test patterns for their detection. This defect class shows similarities to the type I defect class in having relatively low critical resistance that affects Boolean functionality. Most layout bridging defects are easily detected by IDDQ testing. This defect is insensitive to Boolean tests unless the resistance is low, e.g. below about 1 k . Bridge type III – Sequential defect class: This defect category includes transistor node bridges of sequential circuits. Each design style of sequential circuitry has to be individually analysed for this fault type testing. 1.1.3 Opens Open circuit defects or shortly opens can be interpreted as unintentional electrical discontinuities.These defects include: - open contacts (missing metal or unopened oxide), - metallization opens (pattering, improper etching, electromigration, or stress voiding), - opens in diffusion or polysilicon (mask or fabrication errors). They can cause behaviour that may vary greatly and be difficult to predict. The manifestation of an open defect depends not only on the size of the crack, but also on the temperature, clock frequencies, location and technological parameters, as well. Opens can be located at the gate level and also at the transistor level (Figure 2-7). VDD Open source Floating gate Open drain Figure 2-7. Open faults at the gate and the transistor levels. 10 Chapter 2 Different classification exists in the literature for open defects. Two types of classification is introduced in this book – general, based on the size break and classification targeted to the transisor level. The basic general division is based on the charge transfer rate function with dependence on the size break and 3 groups can be recognized [5]: - almoust open or resistive open, - completely open (a stuck-open; the special case of a resistive open defect in which the resistance is very large), - tunneling open. Some experiments with the first two classes in the context of testing are presented in [21]. Classification of the opens at the transistor level was done by Hawkins anf the open faults were specified [14] into 6 main fault classes: - Open type-1: transistor-on defect class (an open defect that causes a transistor to be permanently on, or on for one logic state. Boolean testing is difficult, because this defect class causes delay attributed to a single transistor; it is detectable by IDDQ testing). - Open type-2: transistor pair-on defect class (an open defect that causes a transistor pair to be permanently; it is detectable by Boolean and IDDQ and delay testing). - Open type-3: transistor pair on/off defect class (this defect class is detected with a Boolean test set and the test patterns may be either delay fault or SAF; IDDQ is not increased for this class). - Open type-4: sequential open defect class (large open circuit defects in sequential circuits cause either degraded voltages with or without Boolean upset or strong clamping to a supply voltage. Degraded voltages are detected by IDDQ testing and nodes clamped to a supply voltage are detected by Boolean tests). - Open type-5: transistor-off defect class (detection of this CMOS IC memory effect is difficult to quantify; 2 Boolean test patterns targeted to each transistor is needed for its detection; this defects can be detected by IDDQ testing). - Open type-6: delay defect class (this defect class includes the delay effect seen in open circuits having small cracks that allow tunnelling and subsequent delay error. Detection depends upon the quality of the delay defect test patterns to examine all possible open situation; this type is detected mainly by delay testing). Example 2-3: Figure 2.8 illustrates a transistor level schematic of NAND gate with 2-inputs in CMOS technology with 3 open defects affecting the operation of transistor p1 : d1 , d2 , d3 [2]. Solution: These open faults are not detected by any of 3 single test vectors (a,b): 2. DEFECTS, FAULTS, FAULT MODELS 11 VDD V d1 d2 A B DD p1 d3 p p2 P 1 2 Z n1 n 1 n2 n 2 V s Figure 2-8. Open faults inside NAND. s T1=(11), T2=(10), T3=(01). Test vector T2 drives the output to logic 1 through transistor p2 and vector T3 instead drives the output to logic 1 through transistor p1. In the presence of these defects, the output is not driven to logic high. However, these defects are detected by a SAF test set, but ordered as the triple test set (T2, T1, T3). However, in general, for open defects two test vectors (T1, T2) are required. The first test vector T1 initialises the output to the logic level and T2 attempts to change state through a particular transistor-control path. For logic gates with higher complexity the SAF test set cannot guarantee detection all open defects. A detailed treatment of open defects and solutions of some specific problems with the open defects are presented in variety publications [e.g. 2, 3, 5, 21, 22]. 1.1.4 Delay faults Timing or delay fault is also an important design parameter in the inputoutput relationship. Studies of the electrical properties of defects have shown that most of the random CMOS defects cause a timing (delay) effect rather than a other catastrophic defects, e.g. resistive bridges above a critical resistance cause delay. The delay defects defines a class of delay defect typically is neither in the category bridges or opens. It means good CUT fails to perform correctly its function in a system, but it fails in designed timing specifications. It means the expected value on the output in a circuit node is delayed and the real output value is not correct. The observation can be by limits clock frequency. The illustrative example is in Figure 2-9. The output value change logical value 0 to 1 after larger clock interval in comparison with timing specifications. 12 Chapter 2 A B Figure 2-9. Illustrative example of the delay fault. A timing or delay fault could be caused by a number of reasons that include [2,5]: resistive vias, IR drop on power supply, weak transistors, subtle manufacturing, process defects, transistor threshold voltage shifts, increased parasitic capacitance, improper timing design, etc. Propagation delay faults are associated with either a net or a component thus delay fault models have been proposed for delay testing: - Gate delay fault model: each CUT is designed with a pre-specified nominal delay. However, under the gate delay fault model, the faulty gate may assume considerably larger delay. - Path delay fault model: this fault model considers the cumulative delay of paths from primary inputs to primary outputs. - Transition faults are faults of a gate characterized as slow-to-rise and slow-to-fall types. These fault types are obviously used in the time specification testing. - Line delay faults are rising and falling delays of a given signal line. The difference from the transition delay fault model is that the line delay fault is propagated through the specified line, obviously via the longest sensitizable path. - Segment delay faults mean delay through a chain of combinational gates with the specified length L. If L is taken as the maximum combinational depth of CUT, the segment-delay faults become the same as path-delay faults. For L=1, segment delay faults become identical to transition faults. Delay faults testing assumes that delay of a gate (or a path) depends on the transition propagated from the input to the output. Testing requires a 2pattern test, the first one for inicialization of a specific value in a CUT node and the second one for delay faults excitation. The test set is categorized as robust or non-robust test set. A robust test detects the targeted delay faults irrespective of the presence of other delay faults in CUT. Otherwise, the test set is non-robust. 1.1.5 Leakage Faults Some defects such as a GOS will cause leakage current flow between gate, source and drain, or gate and other nodes of the transistor. In general a 2. DEFECTS, FAULTS, FAULT MODELS 13 leakage fault may occur between any nodes of a MOS transistor. A leakage fault model was proposed containing six types of faults for MOS transistors [2,19]: - leakage fault between gate and source, - leakage fault between gate and drain, - leakage fault between source and drain, - leakage fault between bulk and source, - leakage fault between bulk and drain, - leakage fault between bulk and gate. These faults include not only the gate oxide defect causing leakage but also the leakages between various diodes required to realize a MOS transistor. Typically, small leakage faults do not cause a catastrophic failure of CUT, however, they are potential reliability hazards. 1.1.6 Summary to defect and fault classification New technologies bring new defects, which have to be modelled into faults. The fault modelling is targeted to reduce the number of individual defects that have to consider complexity of the device description that must be used in test generation and test analysis. Table 2-1. Defect and their detections Defects Property IDDQ Short Rdefect<Rcritical yes Rcritical<Rdefect yes <Rcrit_delay Rdefect>Rcrit_del yes ay Open on pair of transistors stuck high or low both transistors yes “on” strongly coupled to self Open on a single transistor Transistor stuck yes on hard transistor stuck on yes weakly transistor stuck off yes transistor strongly yes coupled to D Almost open Parametric defects logic delay yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes The trade-off in fault modelling is to develop a model that is simple as possible to use in test generation, but covers of many physical defects. 14 Chapter 2 Which fault model is the best and which type of testing is necessary to use is not simple task – depends on technology and defect manifestation. Table 2-1 shows results from analysis different defects with different properties [5]. For test generation is necessary to use fault models and find suitable relationships between real defects and fault models receiving the best quality of testing. In general, the fault coverage for two different fault models cannot be compared as well as the fault coverage for the same model and different test types [5]. 1.2 Stuck-at fault properties (TTU) One of the most important concerns when generating tests or simulating faults in digital systems is the complexity – the huge number of faults we have to work with. To overcome this problem we should reduce the total number of faults to be processed in test generation. To do that we need better to know different properties of faults like detectability, redundancy, equivalence, dominance a.o. Each of these properties will help us to select only essential faults and not consider other faults classified as nonessential. Let y(x) be the logic function of a combinational circuit C, where x is an input vector and y(x) denotes the mapping realized by C. The presence of a fault f transforms C into a new faulty circuit Cf with a function yf(x). Each input vector t can be regarded as a test, a sequence of input vectors T = (t1, t2, tn) is a test sequence. A test t detects a fault f iff y(t) yf(t). Fault redundancy. We call a fault f detectable if there exists a test t that detects f , otherwise, we call f undetectable. A combinational circuit that contains an undetectable stuck-at-fault (SAF) is said to be redundant, since such a circuit can always be simplified by removing at least one gate or gate input. For example, suppose that SAF1 on an input of an AND gate is undetectable. This means that the function of the gate does not change in the presence of the fault, and we can permanently place constant 1 on that input. But an n-input AND with a constant 1 value on one input is logically equivalent to the (n-1)-input AND obtained by removing the gate input with the constant signal. Similarly, if an AND input SAF0 is undetectable, the AND gate can be removed and replaced by a 0 signal. Other simplification rules can be found in [23]. Redundant faults cause a real trouble in test generation. A test generation is a procedure where a test should be searched among all possible input patterns or sequences. For non-redundant faults we usually find the test quickly by tracing only a small part of the search space. For redundant faults we have to go through the whole huge space of possible patterns. Hence, if we can exclude redundant faults from test generation we can significantly increase the speed of test generation. 2. DEFECTS, FAULTS, FAULT MODELS 15 Fault equivalence. Two faults f and g are called functionally equivalent iff yf(x) yg(x). A test t is said to distinguish between two faults f and g if yf(x) yg(x); such faults are distinguishable. There is no test that can distinguish between two functionally equivalent faults. The relation of functional equivalence partitions the set of all possible faults into functional equivalence classes. For test generation it is sufficient to consider only one representative fault from every equivalence class. With any n-input gate we can associate 2(n + 1) single SAFs. For a NAND gate all the inputs SAF0 and the output SAF1 are functionally equivalent. These equivalent faults can be represented by a single fault in the test generation process. Hence, for test generation for an n-input ŃAND gate (n1) we need to consider only n+2 single SAFs. This type of reduction of the set of faults based on equivalence relations is called equivalence fault collapsing. If in addition to fault detection, the goal of testing is fault location as well, we need to apply a test that not only detects the detectable faults but also distinguishes among them as much as possible. A complete fault location test distinguishes between every pair of distinguishable faults in a circuit. A complete fault location test can diagnose a fault to within a functional equivalence class. This is the maximal diagnostic resolution that can be achieved. Fault dominance. If the objective of a testing is limited to fault detection only, then in addition to fault equivalence, another fault relation called fault dominance can be used to reduce the number of faults that must be considered. Let Tg be the set of all test vectors that detect a fault g. A fault f dominates the fault g iff f and g are functionally equivalent under Tg. If f dominates g , then any test t that detects g will also detect f. Therefore, for fault detection it is unnecessary to consider the dominating fault f , since by deriving a test for g we automatically obtain a test that detects f as well. Fault collapsing. The fault equivalence and fault dominance properties can be used for minimizing the whole set of faults to be considered in test generation and fault simulation. Consider a 3-input NAND gate in Figure 2-10. SAFs on inputs A/0, B/0, C/0 and SAF1 fault D/1 on the output form an equivalent class of faults. On the other hand, the fault D/0 dominates faults A/1, B/1 and C/1. Any of the faults in the equivalence class can be chosen as the representative fault whereas all other faults can be excluded from consideration. Regarding to the dominance classes only the dominating fault D/0 can be excluded. 16 Chapter 2 A B C & D ABC D Fault class 1 0 1 1 A/0, B/0, C/0, D/0 Equivalence class A/1, D/0 B/1, D/0 Dominance classes C/1, D/0 1 1 0 1 1 1 1 0 0 1 1 1 Figure 2-10. Fault collapsing for a NAND gate. Consider now a simple combinational circuit in Figure 2-11. In the case of a circuit we can use the both rules of fault collapsing by combining them in a proper way. For example, for SAF1 on the output we first choose the SAF0 on the connection line between gates representative fault, and then collapses this fault by using dominance rule. As the result, we see that all the faults on the current path of the circuit are collapsed except the SAF1 on the input. In a similar case for SAF0 on the output we see that all the faults on the current path will be collapsed except SAF0 on the input. 1 1 1 & & 1 0 Equivalence Dominance 1 1 0 & & 0 1 Dominance Equivalence Figure 2-11. Fault collapsing for a combinational circuit. By generalizing this result in inductive way, we can easily show that for tree-like combinational circuits, only the stuck-at-faults on inputs are the essential faults for test generation and fault simulation. 2. FUNCTIONAL FAULT MODEL (TTU) The efficiency of test generation is highly depending on the system description and fault models. It has been shown that high SAF coverage cannot guarantee high quality of testing, for example, for CMOS integrated circuits [24]. The reason is that the SAF model ignores the actual behavior of CMOS circuits, and does not adequately represent the majority of real IC defects and failure mechanisms which often do not manifest themselves as stuck-at faults. To handle physical defects in fault simulation, we still need 2. DEFECTS, FAULTS, FAULT MODELS 17 logic fault models for the following reasons: to reduce the complexity of simulation (many physical defects may be modelled by the same logic fault), a single logic fault model may be applicable to many technologies, logic fault tests may be used for physical defects whose effect is not well understood. But the most important reason for logical modelling of physical defects is to get a possibility for moving from the lower physical level to the higher logic level, which has less complexity. In this subchapter, an approach is presented to model physical defects by generic Boolean differential equations with the goal to map them from the physical level to the logic level. Different transistor level faults will be analysed to show that this way of mapping is enough general and feasible. A new fault model is defined on that basis called the functional fault model. It is also shown how the functional fault model can be retreated as a uniform interface for mapping faults from a given arbitrary level of abstraction to the next higher level in test generation processes. 2.1 Fault modelling with Boolean differential equations Consider a Boolean function y = f (x1, x2, …, xn) implemented by an embedded component (complex gate) G in a circuit. Introduce a Boolean variable d for representing a given physical defect in the component, which may affect the value y by converting the Boolean function f into another function y = f d (x1, x2, …, xn) where in fact, some of the arguments xi can fall out, simplifying in that way the function because of the defect. Let us introduce for the component G a generic parametric function y* f * ( x1 , x2 ,..., xn d ) d f df d (2-1) as a function of a defect variable d, which describes the behavior of the component simultaneously for both fault-free and faulty cases. For the faulty case, the value of the defect variable d as a parameter is equal to 1, and for the fault-free case d = 0. In other words, y* = f d if d = 1, and y* = f if d = 0. The solutions of the Boolean differential equation Wd y * 1 d (2-2) describe the conditions which activate the defect d on a line y. The parametric modeling of a given defect d by equations (2-1) and (2-2) allow us to use the constraints Wd = 1, either in defect-oriented fault simulation, for checking if the condition (2-2) is fulfilled, or in defect-oriented test 18 Chapter 2 generation, to solve the equation (2-2) when the defect d should be activated and tested. To find Wd for a given defect d we have to create the corresponding logic expression for the faulty function fd either by logical reasoning or by carrying out directly defect simulation, or by carrying out real experiments to learn the physical behavior of different defects. Example 2-4. Let us have a transistor circuit in Figure 2-12 which implements the function y x1 x2 x3 x4 x5 A short defect as shown in Fig.10 changes the function of the circuit as follows: y d ( x1 x 4 )( x 2 x3 x5 ) Using the defect variable d for the short, we can create a generic differential equation for this defect and simplify the created expression as follows: y * (x1x2 x3 x4 x5 )d (x1 x4 )(x2 x3 x5 )d d d x1 x2 x4 x5 x1 x3 x4 x5 x1x2 x3x4 x5 1 From the equation three possible solutions follow: T = {10x01, 1x001, 01110}. Each of them can be used as a test pattern for the given short. On this contra-example, it is easy to show the inadequacy of the stuck-at fault (SAF) model for testing the transistor level faults. For example, the set of five test patterns 1110x, 0xx11, 01101, 10110, 11010, which test all the stuck-at faults in the circuit does not include any of the possible test solutions for detecting the short from the set T. y x1 x4 Short x2 x3 x5 Figure 2-12. Transistor circuit with a short Note, that for the same purposes of finding the test for the defect d we could solve also directly the equation 2. DEFECTS, FAULTS, FAULT MODELS 19 f fd ( x1 x2 x3 x4 x5 ) ( x1 x4 )( x2 x3 x5 ) 1 without introducing the defect variable d. However, solving the equation (22) will be much easier because of simplification possibilities resulting from specific properties of Boolean differentials [25]. 2.2 Mapping Physical Transistor Defects to Logic Level The described method represents a general approach to map an arbitrary physical defect onto a higher (in this case, logic) level. By the described approach an arbitrary physical defect in a component can be represented by a logical constraint Wd = 1 to be fulfilled for activating the defect (Figure 213). The event of erroneous value on the output y of a functional component can be described as dy = 1, where dy means Boolean differential. A functional fault representing a defect d can be described as a couple (dy, Wd). At the presence of a physical level defect d, we will have an higher level erroneous signal dy = 1 iff the condition Wd = 1 is fulfilled. Component d W F(x1,x2,…,xn) y Activated by W dpath Defect Figure 2-13. Transistor circuit with a short. From another point of view, the equation (2-2) can be interpreted as a mapping of a physical defect d from the transistor level to the logic level as an erroneous change of a logic value dy = 1 by means of fulfilling the logic condition Wd = 1. The following examples will show the feasibility of using Boolean differential equations for mapping faults from physical transistor level to the logic level. Example 2-5. Transistor level stuck-on faults. The behavior of the transistor level NOR gate depicted in Figure 2-14 cannot be described strictly logically. The input vector “10” produces a conducting path from VDD to VSS, and the corresponding voltage at the output node Y will not be equal to either VDD or VSS but will instead be a function of the voltage divider formed by the channel resistances of the conducting transistors: VY VDD RN ( RP RN ) 20 Chapter 2 Stuck-on VDD x1 x2 RN Y x1 x2 RP x1 x2 y yd 0 0 1 1 0 1 0 0 1 0 0 VY/IDDQ 1 1 0 0 VSS Conducting path for “10” Figure 2-14. Stuck-on fault in the transistor NOR gate. Depending on the ratio of these resistances along with the switching thresholds of the gates being driven by the output of the faulty gate y, the output voltage of the faulty gate may or may not be detected at a primary output. Denote by the Z this ambiguous value on the gate output. The faulty function of the gate can be represented as follows: If x1 x 2 1 then y d Z . Using the expressions (2-1) and (2-2) we get: y* d ( x1 x 2 ) d ( x1 x 2 x1 x 2 Z ) y d x1 x2 x1 x2 Z . W d y * / d x1 x 2 Z 1 . From that it follows that the condition to activate the defect is x1 1, x2 0. Example 2-6. Transistor level stuck-open faults. For the transistor stuckopen fault of the NOR gate in Figure 2-15, there will be no path from the Stuck-off (open) VDD x1 x2 y yd x1 0 0 1 1 x2 0 1 0 0 1 0 0 Y’ 1 1 0 0 Y x1 x2 VSS No conducting path from VDD to VSS for “10” Figure 2-15. Stuck-off (open) fault in the transistor NOR gate 2. DEFECTS, FAULTS, FAULT MODELS 21 output node to either VDD or VSS for some input patterns. As a result, the output node will retain its previous logic value. This creates a situation where a combinational logic gate behaves like a dynamic memory element. The faulty function of the gate is: y d x1 x 2 x1 x 2 y ' where y’ corresponds to the output value stored at the output of the faulty gate. Using now the expressions (2-1) and (2-2) we get: y* d ( x1 x2 ) d ( x1 x2 x1 x2 y ' ) x2 ( x1 dy ' ) W d y * / d x1 x2 y ' 1 . From that it follows that the condition to activate the defect is x1 1, x2 0, y' 1. In other words, for testing the fault we need a test sequence of two patterns: “00” to get the value 1 on the output, and then “11”. 2.3 Mapping Interconnection Defects to Logic Level Consider now a component (c) representing a Boolean function y = f (x1, x2, …,xn) embedded in an environment given by a subset of lines Ec = {xn+1, … ,xp}. Introduce the same Boolean variable d for representing physical defects in the subcircuit (c,Ec), given by the block c with its neighbourhood Ec, which may affect on the value y. Let the defect d convert the Boolean function f into another function y = fd (x1, x2, …, xn, xn+1, … xp). (2-3) Introduce for modelling physical defects related to the subcircuit (C,Ec) a generic parametric function y* f * ( x1 , x2 ,..., xn , xn1 ,..., x p , d ) (d f ) (d f d ) as a function of a defect variable d, which describes the behavior of the subcircuit simultaneously for both, fault-free and faulty cases. For the faulty case the value of the defect variable d as a parameter is equal to 1, and for the fault-free case d = 0. In other words, y* = f d if d = 1, and y* = f if d = 0. The solutions of the Boolean differential equation (2-2) describe the conditions which activate the defect d on a line y. 22 Chapter 2 x*k xk d xl Figure 2-16. A bridging fault. Example 2-7. A short between two lines xk and xl in the circuit in Figure 2-16. The faulty function of xk in the case of the defect d in accordance to the wired-AND fault model can be represented as x d k xk xl . Introduce now a generic parametric function xk * d xk dxk d xk d ( xk xl ) d as a function xk * f ( xk , xl , d ) of a defect variable d, which describes the behavior of the interconnection network simultaneously for both, fault-free and faulty cases. The solution of the Boolean differential equation W d xk * / d xk xl describes the conditions (constraints) which activate the fault d on a line xk (Figure 2-17). The condition W d xk xl 1 means that in order to detect the short between lines xk and xl on xk we have to assign to xk the value 1 and to xl the value 0. Bridging fault causes a feedback loop: x1 & x2 y & x3 Equivalent faulty circuit: x1 x2 & & & y x3 Figure 2-17. A Bridging fault with feedback loop. Example 2-8. A short between two lines xk and xl in the circuit which creates a feedback loop. A circuit with such a loop and its equivalent faulty circuit corresponding to the wired-AND fault model is depicted in Figure. 2- 2. DEFECTS, FAULTS, FAULT MODELS 23 17. The generic parametric function for describing the behavior of the circuit simultaneously for both, fault-free and faulty cases has the following form: y* d ( x1 x2 x3 ) d ( x1 x2 y x3 ) x1 x2 (d y ' ) x3 The solution of the Boolean differential equation W d y * / d x1 x2 x3 y' 1 describes the conditions (constraints) which activate the fault d on a line y (Figure 2-15). The apostrophe at y means that the value of y belongs to the previous time moment. The condition means that we need for testing of the short a sequence of two patterns. First, we have to set the value y = 0 (for example, by assigning x3 = 0), then we have to apply the pattern x1 = 1, x2 = 1, x3 =1. From this example we see that in the general case the constraints for activating a fault may be spread over different time moments, and represent a sequences of patterns. We also see that the method for describing faults by generic Boolean differential equations allows us directly to attack the problem of testing so called ”sequential faults” which convert combinational circuits into sequential ones, or which increase the number of states in sequential circuits. Test generators, which are able to work with such faults, are missing. The first, as a method of mapping arbitrary physical defects onto the logic level, and second, as a universal method of fault modeling in hierarchical approaches to test generation and fault simulation. The conditions Wd for activating defects d can be used as constraints at the higher (logical or register transfer) level either for fault simulation or for test pattern generation without paying attention to the physical reasons of defects. 2.4 Hierarchical representing of faults The method of defining faults by logic conditions Wd allows us to unify the diagnostic modelling of components of a circuit (or system) without going into structural details of components and into the diagnostic simulation of interconnection network of components. In both cases, a condition Wd describes how a lower level fault d (either a defect in a component or a defect in a network) should be activated at a higher level to a 24 Chapter 2 given node in a circuit (or system). The conditions Wd can be used both in fault simulation and in test generation. Consider a node k in a circuit (Figure 2-18) as the output of a module Mk, and represented by a variable xk. Associate with the node k a set of faults Rk = RFk RSk where RFk is the subset of faults in the module Mk, and RSk is a subset of structural faults (defects) in the “network neighbourhood” of Mk. Denote by Wd the condition when the fault d Rk will change the value of xk. Denote by WFk the set of conditions Wd activating the defects d RFk and by WSk the set of conditions Wd activating the defects d RSk. By using the sets of conditions WFk and WSk we can set up a mapping of faults from a lower level to a higher level for test generation purposes, and also in opposite direction, from a higher level to a lower level for fault simulation or fault diagnosis purposes. Mapping High level WFk WSk Component k Low level Bridging fault Environment Mapping Figure 2-18. Mapping faults from lower level to higher level. In test generation, to map a lower level fault d Rk to the higher level variable xk, a solution of the equation Wd = 1 is needed. In other words, if the condition Wd = 1 is fulfilled then the presence of the defect d Rk will change the value of the variable xk. In fault simulation (or in fault diagnosis) an erroneous value of xk (denoted by a Boolean differential dxk = 1) can be formally explained by implication dxk d1W d 1 d 2W d 2 ... d nW dn (2-4) where for j = 1,2,…n: dj Rk . To the higher-level event dxk = 1, we set into correspondence a lower level event dj if the condition Wdj = 1 is fulfilled. For hierarchical testing purposes we should construct for each module Mk of the circuit a list of faults Rk with logical conditions Wd for each fault d 2. DEFECTS, FAULTS, FAULT MODELS 25 Rk. The set of conditions WFk for the functional faults d RFk of the module can be found by low-level test generation for the defects in the module. The set of conditions WSk for the structural faults d RSk in the environment of the module can be found by Boolean differential analysis of generic faultfree/faulty functions as explained in previous Sections 2-1, 2-2 and 2-3. In Figure 2-19, a hierarchical test concept based on parametric fault modeling and functional fault model for a 3-level system is illustrated. In the functional approach, only the information about the functional behaviour is used. In the structural approach, tests are targeted to detect the faults in the networked components and in the network interconnections. Functional approach F Structural approach Test W Sk W Fk Network of modules System Fk Test W Ski Module W F ki F ki Gat e Test Network of gates W d ki Circuit Figure 2-19. Hierarchical fault representing. Consider a task of defect oriented fault simulation in a system, which is represented at three levels: register transfer, gate and defect levels. Formally, if Y is the system variable representing an observable point (a register) of the system, yM is an output variable of a logic level module and yG is the output of a logic gate with a physical defect d, then the condition to detect the defect d on the observable test point Y of the system is W = Y/yM yM /yG Wd = 1, where Y/yM means the fault propagation condition calculated by highlevel modeling, yM/yG is the fault propagation condition (Boolean derivative) calculated by gate-level modeling, and Wd is the functional fault condition calculated from (2-2) by the gate preanalysis. 26 3. Chapter 2 DEFECT MODELLING (WUT) In this Subchapter, a methodology for probabilistic modelling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed. Quality of testing depends also on quality of test patterns generated for a circuit under test. Evaluation criteria for digital circuits testing are fault coverage and test application time. Low efficiency of the classical stuck-at fault model in real defect coverage in CMOS logic has initiated the need of new test approaches. These approaches extend the CMOS standard cells characterisation methodology for voltage defect based testing and for IDDQ testing. The proposed methodology allows to find the types of faults, which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions – “Wired-AND” and “Wired-OR” – should be used. Examples of industrial standard cells characterisation indicate that a single logic fault probability table is not sufficient. Separate tables for “Wired-AND” and “Wired-OR” conditions at the inputs are needed for full characterisation and hierarchical test generation. 3.1 Model of manufacturing yield losses Modern VLSI technology possesses a number of difficult challenges [26] for design, test and manufacturing. One of them is to develop a product, which meets predefined technical specifications and can be manufactured at the minimum cost level [27, 28]. The manufacturing cost of functioning (fault free) integrated circuit (IC), Cch, can be expressed as: Cch Cw N tot Y (2-5) where: Cw is the cost of wafer manufacturing, Ntot is the number of IC dies per wafer, and Y is the manufacturing yield, i.e. the probability that a fabricated and tested die works according to its desired specifications. One can achieve decreasing of the IC manufacturing cost by increasing the product NtotY. The straightforward way to do it on an existing manufacturing line is increasing Ntot by downscaling IC design, which means reducing distances and sizes of the shapes in the IC layout. However, scaling down the IC design may lead to decrease of the manufacturing yield Y. Hence, there is a need for a trade-off between these two contradictory tendencies. 2. DEFECTS, FAULTS, FAULT MODELS 27 Manufacturing yield loss Y is often represented by the product [28]: Y Y fnc Y par (2-6) where: Yfnc is the functional yield associated with spot defects, and Ypar is the parametric yield associated with global process disturbances. In this Subchapter it is assumed that parametric yield loss is not of primary importance and we focus on Yfnc. Spot defects in an IC are caused by contaminants introduced by the manufacturing process. They can be seen as severe but local, often threedimensional (3D) deformations of IC structure. The most important origins of spot defects are: particles from the manufacturing equipment and manufacturing materials (e.g. photoresist), dust particles in the atmosphere of the clean room, imperfections in the glass used as a mask substrate, imperfections of the lithography process itself, etc. Under certain circumstances, defects may cause either: bridges between nonequipotential conducting paths resulting in a short circuit, or breaks (excessive resistance) in a connection resulting in an open circuit. Spot defects can occur in a single layer or can affect more than one IC layer. Spot defects are modelled as disks of extra or missing material in the conducting layer. Important characteristics of spot defects are: size (expressed by the radius R) and frequency of occurrence (density). This Subchapter is restricted to defects affecting single layers. It is also assumed that statistics describing defect characteristics are obtained from the defect scanner (e.g. as provided by KLA Co.). Estimations of layout sensitivity to spot defects and manufacturing yield are usually based on the concept of critical area. According to the generic definition [29, 30], the critical area for shorts for a given layout is the set of regions enclosing all locations of spot defect centres that result in shorts between conducting paths. The critical area for opens is the set of regions enclosing all locations of spot defect centres which result in interconnect opens. Figure 2-20 illustrates concept of critical area for shorts. For simplicity the discussion presented in this Subchapter is limited to the context of shorts, but the presented results can be easily extrapolated to opens as well. 28 Chapter 2 Figure 2-20. Concept of the critical area for shorts: (a) nonequipotential conducting paths; (b) example of different spot defect locations; (c) critical area for shorts The Poisson based yield model, known from the literature [e.g. 29, 30], is given by the following formula: N Y fnc Yi (2-7) i 1 and Yi exp Acri r Di r dr, 0 (2-8) where: Yfnc is the defect-related yield for an IC, N is the number of defect types, Yi is the defect-related yield for defect type ”i” (e.g. short on Metal1 or opens in Polysilicon layer), r is the defect radius random variable, layer Acri(r) is the critical area function, and Di(r) is the defect size distribution. The defect size distribution can be calculated from the formula [31]: Di r Doi fri r (2-9) where Doi is the density of spot defects of type ”i”. fri(r) is the size distribution function for defects of type ”i” given by [32, 33]: 2. DEFECTS, FAULTS, FAULT MODELS 29 2pi 1 r , for : 0 < r X 0i pi 1 X 0i2 f ri r p i 1 2pi 1 X 0i , for : X < r. 0i pi pi 1 r (2-10) The size distribution function has two parameters: X0i (which is modelled to be very small compared to the minimum feature size of technology process) and pi. Figure 2-21 shows an example of size distribution function fri(r) superimposed together with critical area function Acri(r). Acr fr fr(r) Acr (r) Critical Area - Acr & Size Distribution - f r 0 r Figure 2-21. Example of size distribution function and critical area function 3.2 Estimation of defect occurrence probabilities It is well known from the literature [e.g. 4, 24, 34-36] that classical test generation methods cannot handle the actual behaviour of faulty digital circuits implemented as CMOS integrated circuits (IC). These methods allow to generate test vectors using logic-driven gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-at fault model – SAF) to describe manufacturing defects causing IC failure. As a result the circuit layout, physical defects characteristics and the actual circuit behaviour are ignored. To overcome these limitations, in [36, 37] circuit and layout-driven test generation methods were proposed. In these works the whole circuits having hundreds of gates were analysed as single blocks. Such an approach is computationally expensive and thus highly impractical as a method of 30 Chapter 2 generation of tests for real VLSI designs. An alternative approach has been proposed recently [12, 38-40]. In these works functionality of gates from a standard cell library is analysed for all possible physical defects using transistor-level simulation. This characterisation process may be computationally expensive, but it should be done only once for every standard library cell. This information can be used for defect oriented fault simulation and test generation at higher levels of abstraction [12, 39, 41, 42]. It can be shown that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results [13]. In the following one kind of physical defects in CMOS gates – shorts between conducting regions is considered. This is one of the most important sources of faults in CMOS digital circuits. However, the methodology can be extended to other types of physical defects as well (e.g. breaks). A short is a piece of extra conducting material that connects a pair of separate conducting regions in the integrated circuit. This affects the connectivity of the circuit – two separate electrical nodes become shorted. It is intuitively obvious that probabilities of shorts depend on the layout of the circuit. Conducting regions that are adjacent to one another are more susceptible to shorts than regions that are separated by a large distance. We assume that every defect, which results in a short, can be approximated by a circle. To estimate the probabilities of shorts between pairs of nodes we use the concept of critical area for shorts [29, 30]. Probability that two electrical nodes will be shorted by a physical defect is given by the following formula derived from Poisson based yield model [12, 40]: N Psh 1 exp Acri r Doi f ri r dr. 0 i1 (2-11) In our calculations of the probability of shorts, three of the most important conducting layers – Polysilicon, Metal1 and Metal2 were taken into account. Parameters of size distribution function fri(r) were assumed as follow. X0i was assumed to be 20% of the minimal distance between shapes on a given conducting layer and p = 3. The density of physical defects was assumed Do = 10 defects/cm2. In this work we extracted the critical area using the commercial CAD tool (CADENCE Dracula [43]) by means of a series of geometrical operations on the cell layout. The operations that are possible in Dracula are normally used for design rule checking, but they can also be used for other 2. DEFECTS, FAULTS, FAULT MODELS 31 geometrical transformations of the layout, and in particular for extraction of the critical area defined as in Fig. 2-18. Formula (2-11) allows calculating the probability of shorts between more than two electrical nodes as well. In this case critical area Acri(r) should be extracted for nonequipotential conducting paths representing given nodes altogether. 3.3 Faulty functions identification and test vectors generation for voltage testing The first step in identifying logic faults and their probabilities is to calculate Psh for all pairs of conducting regions representing electrical nodes. If for a given pair Psh = 0, this pair of nodes cannot be shorted and is not taken into account. For the pairs that can be shorted the logic faults are determined. In simple cases this can be done by inspecting the circuit, for example it is obvious that a short between an output node and VDD results in “Stuck-at-1” fault at this node. In more complex cases it may be necessary to simulate operation of the faulty circuit at the transistor level. Analysed gates and circuits were simulated electrically to find the test set for each short. A testbench circuit (see Figure 2-22) was implemented in HSPICE. Level 47 (BSIM3 Version 2.0) MOS transistor model was used in simulations. Figure 2-22. Testbench circuit schematic diagram For each short the responses to all the input vectors were found. If at least one net of the shorted pair was an input, the simulation was carried out twice using “Wired-AND” and “Wired-OR” models [23, 44]. These two models were implemented by using input buffers with MOS transistors of different channel geometries. The construction of the buffers is shown in Figure 2-23. 32 Chapter 2 The channel width values of the transistors used in the buffers are given below: “Wired-AND” shorts: PMOS W = 10 µm, NMOS W = 10 µm; “Wired-OR” shorts: PMOS W = 40 µm, NMOS W = 5 µm. The channel length was 0.8 m in all the transistors. vdd In Out gnd Figure 2-23. Buffer schematic diagram In Tables 2-2 and 2-3 the logic levels (in Volts) at output for standard two input NAND gate are given. A and B are inputs, Y is output, vdd and gnd are supply lines. Notation A&B means the short between net A and B. Please observe the differences between these tables. In case of “Wired-And” condition the short A&B did not change the function of the NAND gate. However, in case of “Wired-Or” condition the NAND gate performs NOR function. Table 2-2. Logic levels for Y=NAND(A,B) gate in case of “Wired-And” conditions at inputs <AB> 00 01 10 11 O.K. H H H L A&B A&Y A&gnd A&vdd B&Y B&gnd B&vdd Y&gnd Y&vdd 5.00 1.17 5.00 5.00 1.17 5.00 5.00 0.00 5.00 5.00 0.52 5.00 0.00 5.00 5.00 5.00 0.00 5.00 5.00 5.00 5.00 5.00 0.52 5.00 0.00 0.00 5.00 0.00 3.21 5.00 0.00 2.90 5.00 0.00 0.00 5.00 Table 2-3. Logic levels for Y=NAND(A,B) gate in case of “Wired-Or” conditions at inputs <AB> 00 01 10 11 O.K. H H H L A&B A&Y A&gnd A&vdd B&Y B&gnd B&vdd Y&gnd Y&vdd 5.00 0.26 5.00 5.00 0.26 5.00 5.00 0.00 5.00 0.00 0.13 5.00 0.00 5.00 5.00 5.00 0.00 5.00 0.00 5.00 5.00 5.00 0.12 5.00 0.00 0.00 5.00 0.00 4.38 5.00 0.00 4.31 5.00 0.00 0.00 5.00 ( I would like to add here a few sentences to explain the physics of “Wired-Or”/“Wired-And” phenomenon, Witold) 2. DEFECTS, FAULTS, FAULT MODELS INV1 In1 33 Out1’ Out1=1 In A In B INV2 In2 Out CUT Out Rsh Out2=0 Out2’ Figure 2-24. Voltage divider created by transistors of driving inverters in presence of short at inputs of circuit under test. Arrow shows the flow direction of current In some cases (e.g. when one of the shorted nets was the output) the output voltage of the tested circuit was significantly different from the expected one, i.e. either 0.0 or 5.0 volts. More over CMOS gates have different switching thresholds (please see Table 2-4). To avoid ambiguity in classifying such responses as logic one or logic zero, a non-inverting buffer (of the same construction as the input ones) regenerating the voltage level was connected to the output. For each input vector the output voltage of the buffer was compared with the correct value of the logic function implemented by the tested circuit. If these two values did not match, the input vector was counted as a test vector. Table 2-4. Switching thresholds for selected standard CMOS gates Gate Driven Input Switching Threshold [V] IN1=NOT(A) A A (B = 1 = const) B (A = 1 = const) A=B A (B = 0 = const) B (A = 0 = const) A=B 2.30 2.01 1.83 2.53 2.70 2.45 1.91 NA2=NAND(A,B) NO2=NOR(A,B) The procedure presented above is the most time consuming part of the characterisation. If the number of possible shorts is large and operation of 34 Chapter 2 the faulty cell is not obvious for most of them, it is necessary to perform many circuit simulations. This is time consuming and difficult to automate. Hence, the complexity of the characterisation process depends mainly on the number of physically possible shorts in the characterised cell and the complexity of the cell function. In practice it may take from several hours to several days to characterise a single cell. However, this process is performed only once for every library cell. In this way the functional faults that result from shorts are identified and their probabilities are determined. 3.3.1 Examples of CMOS circuits characterization The methods described in Section 3.2 and 3.3 were used for characterisation of gates from an industrial standard cell library in 0.8 µm CMOS technology. Figure 2-25 shows the distribution of the probabilities of various types of functional faults for a complex 4 input AN3 gate performing the not((A and B) or C or D) function. Please observe that probabilities of SA1 and SA0 are not the highest. Layout, logic and schematic diagrams of AN3 gate are shown in Figure 2-26. Table 2-5 gives, the mapping between functional faults, input vectors of the gate and defects (for “Wired-AND” shorts) is given. For each vector, all the defects detected by this vector are marked by 1. The notation “A/C” means “a short between A and C electrical nodes”. Note also that some defects are not detectable by voltage testing method. In case of A/B short the reasons of this fact are “Wired-AND” conditions [23, 44] for shorts at the inputs of AN3 gate. 5.0E-07 4.0E-07 3.0E-07 2.0E-07 1.0E-07 Figure 2-25. Distribution of probabilities of faults for AN3 gate SA1 fo r Q n ot(A*B) n ot(A*B+C) n ot(A*B+C+no t(D )) not(A*B+D) n ot(A*B+no t(C )+D) SA0 fo r Q n ot(A*B+C*D) n ot(no t(B)+C +D ) not(A+C+D) not(B*D+C) not(B*C+D) n ot(C+D) n ot(no t(A)+C +D ) not(B+C+D) n ot(A*D+C) not(A*C+D) 0.0E+00 No t d etectab le Probability of Faults 6.0E-07 2. DEFECTS, FAULTS, FAULT MODELS 35 Figure 2-26. Logic diagram (top), layout (left) and schematic diagram (right) of AN3 complex gate Based on data from Table 2-5 the effectiveness of test vectors was calculated (see Table 2-6). This effectiveness is defined as the total probability of occurrence of a group of all faults detected by a given test vector [38]. In Table 2-6 one can see that the vector V(1) = 0010 has the highest effectiveness. Table 2-5. Probabilities of defects (“Wired-AND” shorts) in the complex gate AN3 = NOR( AND (A, B), C, D ) and the fault table i Input vector tj <ABCD> Defect Erroneous function Probability di f di Pi 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 A/B not detected 3.2938E-07 2 A/C not(A*C+D) 1.0199E-07 none 3 A/D not(A*D+C) 5.8123E-08 4 A/n1 not(B+C+D) 5.0892E-08 1 5 A/Q not(not(A)+C+D) 3.1540E-08 1 1 6 A/gnd not(C+D) 3.4523E-08 7 A/vdd not(B+C+D) 1.8743E-08 1 1 1 1 1 1 1 1 1 36 Chapter 2 8 B/C not(B*C+D) 3.0736E-07 9 B/D not(B*D+C) 1.2855E-07 10 B/n1 not(A+C+D) 5.5331E-08 1 11 B/Q not(not(B)+C+D) 6.5150E-08 1 1 12 B/gnd not(C+D) 2.7366E-08 13 B/vdd not(A+C+D) 2.1387E-08 14 C/D not(A*B+C*D) 4.4240E-07 15 C/n1 SA0 for Q 4.0733E-08 1 16 C/Q not(A*B+not(C)+D) 1.0515E-07 1 1 17 C/gnd not(A*B+D) 2.5810E-08 1 18 C/vdd SA0 for Q 1.4943E-08 1 1 1 19 D/n1 SA0 for Q 2.1978E-08 1 1 1 20 D/Q not(A*B+C+not(D)) 1.8618E-07 1 1 1 1 1 1 21 D/gnd not(A*B+C) 2.1360E-08 22 D/vdd SA0 for Q 1.0609E-08 1 23 n1/Q not(A*B) 4.2614E-08 24 n1/gnd SA0 for Q 7.2557E-09 1 25 n1/vdd not detected 1.4613E-07 26 Q/gnd SA0 for Q 1.2459E-07 1 27 Q/vdd SA1 for Q 7.0250E-09 28 gnd/vdd not detected 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 none 1 1 1 1 3.7640E-09 1 1 1 1 1 1 1 1 1 1 1 none Taking into account that in many cases one fault can be detected by several test vectors, the concept of usefulness of test vectors was introduced in [38]. It allows determining the optimum sequence of test vectors. Having calculated the effectiveness for every test vector, this sequence can be determined in the following way. The vector with the highest effectiveness is selected as the first one. Then the probabilities of occurrence of all faults detected by the first vector are subtracted from the effectiveness of the remaining vectors. In this manner one can obtain the effectiveness of the remaining vectors for the remaining (i.e. not detected by the first vector) faults. It is called usefulness of the test vectors. The second vector selected is the one with the highest usefulness, and again one must subtract the probabilities of the faults detected by the second vector from the usefulness of the remaining vectors. This procedure is repeated to select the third vector and subsequent ones until no more undetected faults remain. The results of the usefulness computation for AN3 cell are presented in Table 2-7 and Figure 2-27. The fault coverage for 5 test vectors equals 80.28%. Table 2-6. Effectiveness of test vectors for the gate AN3 Test vector <ABCD> V(1)=0010 Shorts detected A/C, B/C, C/D, C/Q, C/gnd, n1/Q, Q/vdd Effectiveness 1.0324e-06 2. DEFECTS, FAULTS, FAULT MODELS 37 V(2)=1010 B/C, C/D, C/Q, C/gnd, n1/Q, Q/vdd 9.3036e-07 V(3)=0001 A/D, B/D, C/D, D/Q, D/gnd, n1/Q, Q/vdd 8.8626e-07 V(4)=1001 B/D, C/D, D/Q, D/gnd, n1/Q, Q/vdd 8.2813e-07 V(5)=1100 A/C, A/D, A/Q, A/gnd, B/C, B/D, B/Q, B/gnd, Q/vdd 7.6163e-07 V(6)=0101 A/D, C/D, D/Q, D/gnd, n1/Q, Q/vdd 7.5771e-07 V(7)=0110 A/C, C/D, C/Q, C/gnd, n1/Q, Q/vdd 7.2499e-07 V(8)=1000 V(9)=0100 V(10)=0000 B/n1, B/Q, B/vdd, C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd A/n1, A/Q, A/vdd, C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd A/Q, B/Q, C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd 6.5331e-07 6.1262e-07 6.0813e-07 V(11)=0011 n1/Q, Q/vdd 4.9639e-08 V(12)=0111 n1/Q, Q/vdd 4.9639e-08 V(13)=1011 n1/Q, Q/vdd 4.9639e-08 V(14)=1101 Q/vdd 7.0250e-09 V(15)=1110 Q/vdd 7.0250e-09 V(16)=1111 Q/vdd 7.0250e-09 The similar simulations for AN3 cell but with “Wired-OR” shorts were also carried out. The fault table obtained is different from Table 2-5. It was not included because of the lack of space. But the most important results – usefulness of test vectors – are presented in Table 2-8. As one can note the sequence of test vectors was changed and sets of detected defects are different. In this case the fault coverage equals 75.63%. Table 2-7. Usefulness of test vectors for the gate AN3 (“Wired-AND” shorts) Test vector Shorts detected <ABCD> V(1)=0010 V(2)=1000 A/C, B/C, C/D, C/Q, C/gnd, n1/Q, Q/vdd B/n1, B/Q, B/vdd, C/n1, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd Usefulness absolute relative 1.0324e-06 0.42468 5.4816e-07 0.22550 V(3)=1100 A/D, A/Q, A/gnd, B/D, B/gnd 2.8010e-07 0.11523 V(4)=0100 A/n1, A/vdd 6.9635e-08 0.02865 D/gnd 2.1360e-08 0.00879 V(5)=0001 (or 0101, or 1001) Chapter 2 Vector Usefulness 38 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 V(1)=0010 V(2)=1000 V(3)=1100 V(4)=0100 V(5)=0001 (or 0101 or 1001) Figure 2-27. Usefulness of test vectors for the gate AN3 Table 2-8. Usefulness of test vectors for the gate AN3 (“Wired-OR” shorts) Test vector Usefulness Shorts detected <ABCD> absolute relative 1.3779e-06 0.56683 A/B, A/n1, A/Q, A/vdd, B/C, B/D, V(1)=0100 C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd V(2)=1000 A/C, A/D, B/n1, B/Q, B/vdd 3.0198e-07 0.12423 V(3)=0010 C/gnd, n1/Q, Q/vdd 7.5449e-08 0.03104 V(4)=1100 A/gnd, B/gnd 6.1889e-08 0.02546 D/gnd 2.1360e-08 0.00879 V(5)=0001 (or 0101, or 1001) In order to check the importance of defects causing shorts between more than two electrical nodes (so called double shorts) a similar characterisation procedure for NA2 = NAND(A,B) gate was carried out. The results for “Wired-AND” shorts in NA2 gate are presented in Table 2-9. Table 2-9. Probabilities of defects in the gate NA2 = NAND( A, B ) and the fault table (“Wired-AND” shorts) i Defect di Erroneous function Probability Pi Input vector tj <AB> f di 1 A/B absolute relative not detected 3.4405e-07 0.27840 2 A/Q A 1.4407e-07 0.11658 3 A/gnd SA1 for Q 1.7382e-08 0.01407 4 A/vdd not B 4.5933e-08 0.03717 5 B/Q B 8.1981e-08 0.06634 6 B/gnd SA1 for Q 4.5555e-08 0.03686 7 B/vdd not A 1.1434e-07 0.09252 0 1 2 3 none 1 1 1 1 1 1 1 1 1 1 2. DEFECTS, FAULTS, FAULT MODELS 39 8 Q/gnd SA0 for Q 6.6776e-08 0.05403 9 Q/vdd SA1 for Q 1.0407e-07 0.08421 10 gnd/vdd not detected 5.5575e-09 0.00450 1 1 1 1 none 11 A/B/Q A*B 5.9993e-08 0.04855 1 1 1 12 A/B/gnd SA0 for Q 1.6993e-08 0.01375 1 1 1 13 A/B/vdd SA1 for Q 2.7522e-08 0.02227 14 A/Q/gnd SA0 for Q 1.3286e-08 0.01075 15 A/Q/vdd SA1 for Q 2.6166e-08 0.02117 16 A/gnd/vdd not detected 5.3552e-09 0.00433 17 B/Q/gnd SA0 for Q 1.7587e-08 0.01423 1 1 1 1 1 1 none 1 1 1 18 B/Q/vdd SA1 for Q 3.2060e-08 0.02594 19 B/gnd/vdd not detected 5.5220e-09 0.00447 none 1 20 Q/gnd/vdd not detected 1.7270e-08 0.01397 none 21 A/B/Q/gnd SA0 for Q 1.2897e-08 0.01044 22 A/B/Q/vdd SA1 for Q 1.6905e-08 0.01368 23 A/B/gnd/vdd not detected 5.3194e-09 0.00430 none 24 A/Q/gnd/vdd not detected 4.6267e-09 0.00374 none 25 B/Q/gnd/vdd not detected 4.5913e-09 0.00372 none 1 1 1 1 In Table 2-9 one can observe that triple and quadruple shorts have much lower importance than double shorts from a probability of occurrence point of view. For data completeness results of the usefulness computation for NA2 cell are presented in Table 2-10 and Fig. 2-26. Please note that two vectors V(1) = 11 and V(2) = 10 can detect most of double and multiple shorts. Table 2-10. Usefulness of test vectors for the gate NA2 (“Wired-AND” shorts) Test vector Usefulness <AB> V(1)=11 Shorts detected A/Q, A/gnd, B/Q, B/gnd, Q/vdd, A/B/Q, A/B/vdd, A/Q/vdd, B/Q/vdd, A/B/Q/vdd absolute relative 5.5570e-07 0.44967 V(2)=10 B/vdd, Q/gnd, A/B/gnd, A/Q/gnd, B/Q/gnd, A/B/Q/gnd 2.4188e-07 0.19593 V(3)=01 A/vdd 4.5933e-08 0.03717 V(4)=00 not used 0 0 Chapter 2 Vector Usefulness 40 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 V(1)=11 V(2)=10 V(3)=01 V(4)=00 Figure 2-26. Usefulness of test vectors for the gate NA2 Described methodology for CMOS standard cells characterization can be also applied for bigger circuits, e.g. for C17 ISCAS-85 benchmark. Logic diagram and layout of C17 circuit are shown in Figure 2-29 and Figure 2-30 respectively. The results of the usefulness computation are presented in Table 2-11 and Figure 2-31. Using 5 test vectors one can achieve 99.84% fault coverage. Figure 2-29. Logic diagram of the C17 benchmark 2. DEFECTS, FAULTS, FAULT MODELS 41 Figure 2-30. Layout of the C17 benchmark 3.4 Current oriented test vectors generation IDDQ testing has been established as an effective and increasingly popular method of detecting realistic faults in CMOS circuits [3, 45-51]. In this method quiescent power supply current (IDDQ) of the IC under test is monitored and compared to the predefined reference current. This relies on the fact that transistors of a CMOS circuit pass current through only during state changes and do not pass in quiescent state (except leakage current). In a Table 2-11. Usefulness of test vectors for the C17 benchmark (“Wired-AND” shorts) Test Vector Net Shorts Detected <EDCBA> Vector Usefulness absolute relative V(1)=10000 A&E A&n1 A&n2 B&n3 B&Y2 B&vdd C&E A&n3 A&Y2 B&E B&n1 B&n2 C&n1 C&n2 C&n3 C&Y2 D&E D&n1 D&n2 D&n3 D&Y2 E&n4 E&Y1 E&gnd 6.2385E-06 0.51804 n1&n4 n1&Y1 n1&gnd n2&n4 n2&Y1 n2&gnd n3&n4 n3&Y1 n3&gnd n4&Y2 n4&vdd Y1&Y2 Y1&vdd Y2&gnd V(2)=00101 A&B D&n4 A&D A&gnd B&C D&Y1 E&n3 Y1&gnd Y2&vdd B&n4 B&Y1 C&D C&gnd 2.8359E-06 0.2354 E&vdd n1&n3 n1&vdd n3&Y2 n4&gnd 42 Chapter 2 V(3)=01110 A&C A&n4 A&vdd C&Y1 D&gnd E&n1 n1&n2 n1&Y2 1.9502E-06 0.1619 n2&n3 n2&vdd n4&Y1 V(4)=00110 A&Y1 B&D B&bnd D&vdd E&n2 V(5)=00001 C&n4 C&vdd n2&Y2 E&Y2 E&Y2 n3&vdd 8.1981E-07 0.068 1.7976E-07 0.0149 Fault Coverage 99.84% Total 1.2024E-05 0.9984 0.6 Vector Usefulness 0.5 0.4 0.3 0.2 0.1 V(5)=00001 V(4)=00110 V(3)=01110 V(2)=00101 V(1)=10000 0.0 Figure 2-31. Usefulness of test vectors for the C17 benchmark faulty chip the quiescent current is a few orders of magnitude larger than the IDDQ in a defect-free circuit. IDDQ testing procedure applies a set of test vectors, allows circuit to settle to a quiescent state, and then measures IDDQ. A fault will be detected if the measured IDDQ is larger than the reference current. One of the challenges with voltage test generation is to achieve good controllability and observability of the circuit under test to obtain high fault coverage. In contrast [52, 53], IDDQ testing has very good observability because it automatically propagates fault effect through the power supply line. This feature greatly simplifies test vector generation. There are many previous works on test pattern generation for IDDQ testing, e.g. [54-57], but very limited work has been reported in literature about layout-driven test generation [36] methods for current testing. Such a method was used in [58] for comparison of the performance of two test generation techniques, stuckat fault testing and current testing, when applied to CMOS bridging faults. However, defect statistics were not taken into account. Inductive fault analysis [59, 60] was used in [61] to reduce the fault set size, but defect occurrence probabilities were not available at the time of test patterns 2. DEFECTS, FAULTS, FAULT MODELS 43 generation. In [62] Monte Carlo-based inductive contamination analysis was demonstrated for complete fault characterization of standard cell libraries. Such a characterization can be applied for very accurate assessment of defect coverage and test generation. Nevertheless this method is too complex and time consuming to be used for test generation purposes. In this Section critical area approach based on a commercial CAD tool (Dracula) was used for estimation of probabilities of occurrence of physical defects. Functionality of analysed gates from a standard cell library was verified by using transistor-level simulation. The complete bridging fault set (including multiple shorts) was considered. The proposed characterization methodology takes into account the physical design of the characterized cell and therefore it allows to find the types of faults which may occur in a real IC, determine their probabilities, and generate compact test sets which detect these faults. This characterization process may be computationally expensive, but it should be done only once for every standard library cell. All this information can be used for current-voltage oriented fault simulation and test generation at higher levels of abstraction [12, 41, 63, 64]. These ideas were previously presented in Section 3.3 and applied for voltage oriented test generation. In this Section these ideas were reapplied for current oriented test generation. The first step in current oriented test vectors generation for logic gates or more complex circuits is to calculate Psh for all pairs of conducting regions representing electrical nodes. Three types of nodes being bridged within a gate were considered: Constant nodes – nodes with a constant logic value (VDD and GND). Input nodes – input nodes of gates (IN), which can be arbitrarily set to logic ‘1’ or ‘0’. Dependent nodes – nodes where the logic value depends on the input signals of the gates (output node Q or internal node in complex gates N1, N2, N3, etc.). If for a given pair Psh = 0, this pair of nodes cannot be shorted and is not taken into account. For the pairs that can be shorted the quiescent currents (IDDQ) for each input vector are determined. A short may lead to an increase of the quiescent current for a given input vector or not. The analysed gates and circuits were simulated electrically to find the test set for each short. A testbench circuit (see Figure 2-32) was implemented in HSPICE. Level 47 (BSIM3 Version 2.0) MOS transistor model was used in all simulations. The first simulation was always performed for defect-free gates, in order to estimate the reference IDDQ level. 44 Chapter 2 IDD I1 I2 … IN ICUT IO In 1 Buffer In 2 … Buffer Buffer Out CUT Buffer In N CLOAD = 10 fF Figure 2-32. Testbench circuit schematic diagram for IDDQ testing In the testbench circuit, the total current flowing through investigated gate and all buffers was measured. Such measurement better reflects realities, because in a real digital block every gate is surrounded and controlled by others, whose behaviour have influence on total observed power supply current consumption. To avoid ambiguity in classifying functional responses as logic one or logic zero, a non-inverting buffer (of the same construction as the input ones) regenerating the voltage level was connected to the output. The smallest buffers from an industrial standard cell library were used to drive and load tested circuit. For each input vector, the total quiescent current (in a faulty circuit) was compared with the nominal value of quiescent current in defect-free circuit. If this value was one or more orders of magnitude higher, the input vector was counted as a test vector. A short itself was implemented in the SPICE netlist as a resistor of 100 m, which is the average value of the sheet resistance of metal layers used in the 0.8 m CMOS process. The value of the resistor simulating a short is not critical. Several resistance values in the range from 0.01 to 1 M were tried. In this wide range of resistances the gate behaviour at the logic level depended on this resistance but measured supply current was still order of magnitude higher than current in the defect-free circuit. The procedure presented above is the most time consuming part of the characterization process. If the number of possible shorts is large, it is necessary to perform many circuit simulations. Hence, the complexity of the characterization process depends mainly on the number of physically possible shorts in the characterized cell. However, this process is performed only once for every library cell. In this way, the faults caused by shorts are identified and their probabilities are determined. 2. DEFECTS, FAULTS, FAULT MODELS 3.4.1 45 Examples of standard cells characterization for IDDQ testing The methods described in Section 3.4 were used for characterization of gates from an industrial standard cell library in 0.8 m CMOS technology. Figure 2-33 shows the distribution of the probabilities of various types of shorts for a complex 4-input AN3 (see Fig. 2-26). Probability of Defects 5.0E-07 4.0E-07 3.0E-07 2.0E-07 1.0E-07 Q/ vdd gnd/vdd Q/ gnd n1/ vdd n1/ Q n1/ gnd D/ vdd D/ Q D/ gnd D/ n1 C/ vdd C/ Q C/ gnd C/ D C/ n1 B/ vdd B/ Q B/ gnd B/ D B/ n1 B/ C A/ vdd A/ Q A/ gnd A/ D A/ n1 A/ C A/ B 0.0E+00 Figure 2-33. Distribution of probabilities of defects for AN3 gate In Table 2-12, the mapping between IDDQ current, input vectors of the gate and physical defects is given. For each vector, all the defects detected by this vector are marked by 1. The notation “A/B ” means “a short between A and B electrical nodes”. The nominal quiescent supply current for defectfree AN3 gate operating in the testbench circuit was measured. This nominal leakage current was within the range of 100 pA to 142 pA. Based on data from Table 2-12 the effectiveness of test vectors (defined as the total probability of occurrence of a group of all faults detected by a given test vector) was calculated (see Table 2-13). In Table 2-13 one can see that the vector V(1)=0101 has the highest effectiveness. Table 2-12. Probabilities of defects in the complex gate AN3 and the current consumption i Defect di IDDQ current [A] Probability Input vector tj <ABCD> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Min. Max. Pi 1 A/B 3.3E-3 3.6E-3 3.2938E-07 2 A/C 3.3E-3 4.4E-3 1.0199E-07 3 A/D 3.3E-3 4.6E-3 5.8123E-08 4 A/n1 1.6E-3 4.3E-3 5.0892E-08 1 1 1 1 1 1 1 1 5 A/Q 1.5E-3 3.9 E-3 3.1540E-08 1 6 A/gnd 3.6E-3 3.6E-3 3.4523E-08 7 A/vdd 4.1E-3 4.1E-3 1.8743E-08 1 1 1 1 1 1 1 1 8 B/C 3.3E-3 4.2E-3 3.0736E-07 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 Chapter 2 9 B/D 3.3E-3 4.2E-3 1.2855E-07 10 B/n1 1.6E-3 4.3E-3 5.5331E-08 1 1 1 1 11 B/Q 1.5E-3 3.6E-3 6.5150E-08 1 12 B/gnd 3.6E-3 3.6E-3 2.7366E-08 13 B/vdd 4.1E-3 4.1E-3 2.1387E-08 1 1 1 1 14 C/D 3.3E-3 3.9E-3 4.4240E-07 15 C/n1 3.8E-3 4.1E-3 4.0733E-08 1 1 16 C/Q 1.4E-3 3.7E-3 1.0515E-07 1 1 1 1 1 1 1 1 1 1 1 17 C/gnd 3.6E-3 3.6E-3 2.5810E-08 1 1 1 1 1 1 1 1 18 C/vdd 4.1E-3 4.1E-3 1.4943E-08 1 1 19 D/n1 3.8E-3 4.1E-3 2.1978E-08 1 20 D/Q 1.4E-3 3.7E-3 1.8618E-07 1 1 1 1 1 1 1 1 1 1 1 21 D/gnd 3.6E-3 3.6E-3 2.1360E-08 1 1 1 1 1 22 D/vdd 4.1E-3 4.1E-3 1.0609E-08 1 23 n1/Q 1.9E-3 4.1E-3 4.2614E-08 1 1 1 24 n1/gnd 4.4E-3 8.8E-3 7.2557E-09 1 1 1 1 1 1 1 1 1 1 1 1 25 n1/vdd 2.5E-3 2.5E-3 1.4613E-07 26 Q/gnd 1.6E-3 1.9E-3 1.2459E-07 1 27 Q/vdd 1.9E-3 6.4E-3 7.0250E-09 28 gnd/vdd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3.7640E-09 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 2-13. Effectiveness of test vectors for the gate AN3 Test vector <ABCD> V(1)=0101 V(2)=1010 V(3)=1001 V(4)=0100 V(5)=0110 V(6)=1011 Shorts detected A/B, A/D, A/n1, A/vdd, B/C, B/Q, B/gnd, C/D, C/n1, C/vdd, D/Q, D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/D, A/Q, A/gnd, B/C, B/n1, B/vdd, C/D, C/Q, C/gnd, D/n1, D/vdd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/C, A/Q, A/gnd, B/D, B/n1, B/vdd, C/D, C/n1, C/vdd, D/Q, D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/n1, A/Q, A/vdd, B/C, B/D, B/gnd, C/n1, C/Q, C/vdd, D/n1, D/Q, C/vdd, n1/gnd, Q/gnd, gnd/vdd A/B, A/C, A/n1, A/vdd, B/D, B/Q, B/gnd, C/D, C/Q, C/gnd, D/n1, D/vdd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/Q, A/gnd, B/C, B/D, B/n1, B/vdd, C/Q, C/gnd, D/Q, Effectiveness 1.6233E-06 1.5042E-06 1.4690E-06 1.4090E-06 1.3887E-06 1.3072E-06 2. DEFECTS, FAULTS, FAULT MODELS 47 D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd V(7)=1101 V(8)=0010 V(9)=1000 V(10)=0011 V(11)=0001 V(12)=0111 V(13)=1100 V(14)=1110 V(15)=0000 V(16)=1111 A/C, A/Q, A/gnd, B/C, B/Q, B/gnd, C/D, C/vdd, D/Q, D/gnd, Q/vdd, gnd/vdd A/C, A/n1, A/vdd, B/C, B/n1, B/vdd, C/D, C/Q, C/gnd, D/n1, D/vdd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/C, A/D, A/gnd, B/n1, B/Q, B/vdd, C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd, gnd/vdd A/C, A/D, A/n1, A/vdd, B/C, B/D, B/n1, B/vdd, C/Q, C/gnd, D/Q, D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/D, A/n1, A/vdd, B/D, B/n1, B/vdd, C/D, C/n1, C/vdd, D/Q, D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/B, A/C, A/D, A/n1, A/vdd, B/Q, B/gnd, C/Q, C/gnd, D/Q, D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd A/C, A/D, A/n1, A/Q, A/gnd, B/C, B/D, B/n1, B/Q, B/gnd, C/vdd, D/vdd, n1/vdd, Q/vdd, gnd/vdd A/D, A/Q, A/gnd, B/D, B/Q, B/gnd, C/D, C/Q, C/gnd, D/vdd, Q/vdd, gnd/vdd A/n1, A/Q, A/vdd, B/n1, B/Q, B/vdd, C/n1, C/Q, C/vdd, D/n1, D/Q, D/vdd, n1/gnd, Q/gnd, gnd/vdd A/Q, A/gnd, B/Q, B/gnd, C/Q, C/gnd, D/Q, D/gnd, Q/vdd, gnd/vdd 1.2436E-06 1.2223E-06 1.1811E-06 1.1415E-06 1.0993E-06 1.0508E-06 1.0433E-06 9.4001E-07 7.5825E-07 5.0787E-07 The results of the usefulness computation (see Section 3.3.1) for AN3 cell are presented in Table 2-14 and Figure 2-34. The fault coverage for 4 test vectors equals 100%. In case of voltage testing of AN3 the fault coverage for 5 test vectors was 80.28%. Table 2-14. Usefulness of test vectors for the gate AN3 Test vector <ABCD> Usefulness Shorts detected absolute relative A/B, A/D, A/n1, A/vdd, B/C, B/Q, V(1)=0101 B/gnd, C/D, C/n1, C/vdd, D/Q, 1.6233E-06 0.6678 D/gnd, n1/Q, n1/gnd, Q/vdd, gnd/vdd V(2)=1100 V(3)=1000 (or 0000) A/C, A/Q, A/gnd, B/D, B/n1, D/vdd, 5.0867E-07 0.2093 B/vdd, C/Q, D/n1, Q/gnd 2.7311E-07 0.1123 C/gnd 2.5810E-08 0.0106 n1/vdd V(4)=0010 (or 1010 or 0110 or 0011 or 1011 or 1110 or 0111) 48 Chapter 2 Vec tor Usefulness 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 V(1)=0101 V(2)=1100 V(3)=1000 (or 0000) V(4) = 0010 (o r 1010 o r 0110 o r 0011 o r 1011 o r 1110 o r 0111) Figure 2-34. Relative usefulness of test vectors for the gate AN3 The similar simulations (like for voltage testing in Section 3.3) for AN3 cell and remaining gates from standard cell library using “Wired-AND” and “Wired-OR” type of buffers in testbench circuit are repeated. The channel width values of the transistors used in the buffers driving CUT are given below: “Wired-AND” buffer: PMOS W=10 m, NMOS W=10 m; “Wired-OR” buffer: PMOS W=40 m, NMOS W=5 m; Buffer from standard cell library: PMOS W=18 m, NMOS W=10 m. The channel length was 0.8 m in all the transistors. The results of gate characterization in all these cases were the same. It means that test vector generation for IDDQ testing generally does not depend on the simulation conditions of shorts at inputs of logic gates. In order to check the importance of defects causing shorts between more than two electrical nodes a similar characterization procedure for NA2 = NAND(A,B) gate was carried out. The results for NA2 gate are presented in Table 2-15. One can observe that triple and quadruple shorts have much lower importance than double shorts from probability of occurrence point of view. It is also worth noticing, that a test vector detecting a single bridging fault d also detects all multiple bridging faults that contain d. For data completeness results of the usefulness computation for NA2 cell are presented in Table 2-16 and Fig. 2-35. Table 2-15. Probabilities of defects in the gate NA2 and the current consumption I Defect di IDDQ current [A] Probability Pi Input vector tj <AB> Min. Max. absolute relative 1 A/B 3.6E-3 3.6E-3 3.4405e-07 0.27840 2 A/Q 1.4E-3 2.8E-3 1.4407e-07 0.11658 3 A/gnd 3.6E-3 3.6E-3 1.7382e-08 0.01407 4 A/vdd 4.1E-3 4.1E-3 4.5933e-08 0.03717 0 1 2 1 1 3 1 1 1 1 1 1 1 2. DEFECTS, FAULTS, FAULT MODELS 49 5 B/Q 1.4E-3 2.8E-3 8.1981e-08 0.06634 6 B/gnd 3.6E-3 3.6E-3 4.5555e-08 0.03686 7 B/vdd 4.1E-3 4.1E-3 1.1434e-07 0.09252 1 8 Q/gnd 1.7E-3 3.4E-3 6.6776e-08 0.05403 1 1 1 9 Q/vdd 2.7E-3 2.7E-3 1.0407e-07 0.08421 5.5575e-09 0.00450 1 1 1 1 11 A/B/Q 2.1E-3 5.1E-3 5.9993e-08 0.04855 1 1 1 1 12 A/B/gnd 3.6E-3 7.2E-3 1.6993e-08 0.01375 1 1 1 13 A/B/vdd 4.1E-3 8.2E-3 2.7522e-08 0.02227 1 1 1 14 A/Q/gnd 1.7E-3 7.1E-3 1.3286e-08 0.01075 1 1 1 15 A/Q/vdd 2.7E-3 6.8E-3 2.6166e-08 0.02117 1 1 5.3552e-09 0.00433 1 1 1 1 17 B/Q/gnd 1.7E-3 7.1E-3 1.7587e-08 0.01423 1 1 1 1 18 B/Q/vdd 10 gnd/vdd 16 A/gnd/vdd 1 1 1 1 1 1 1 1 1 2.7E-3 6.8E-3 3.2060e-08 0.02594 1 1 1 19 B/gnd/vdd 5.5220e-09 0.00447 1 1 1 1 20 Q/gnd/vdd 1.7270e-08 0.01397 1 1 1 1 21 A/B/Q/gnd 3.4E-3 10.7E-3 1.2897e-08 0.01044 1 1 1 1 22 A/B/Q/vdd 2.7E-3 10.9E-3 1.6905e-08 0.01368 1 1 1 1 23 A/B/gnd/vdd 5.3194e-09 0.00430 1 1 1 1 24 A/Q/gnd/vdd 4.6267e-09 0.00374 1 1 1 1 25 B/Q/gnd/vdd 4.5913e-09 0.00372 1 1 1 1 Table 2-16. Usefulness of test vectors for the gate NA2 Test vector Usefulness Shorts detected <AB> absolute relative 8.8598E-07 0.7169 A/B, A/Q, A/vdd, B/gnd, Q/gnd, gnd/vdd, A/B/Q, A/B/gnd, A/B/vdd, A/Q/gnd, A/Q/vdd, V(1)=01 A/gnd/vdd, B/Q/gnd, B/gnd/vdd, Q/gnd/vdd, A/B/Q/gnd, A/B/Q/vdd, A/B/gnd/vdd, A/Q/gnd/vdd, B/Q/gnd/vdd V(2)=10 A/gnd, B/Q, B/vdd 2.4576E-07 0.1989 V(3)=11 Q/vdd 1.0407E-07 0.0842 V(4)=00 not used 0 0 Chapter 2 Vec tor Usefulness 50 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 V(1)=01 V(2)=10 V(3)=11 V(4)=00 Figure 2-35. Relative usefulness of test vectors for NA2 cell 4. MEMORY FAULTS (IISAS) ACKNOWLEDGEMENTS Thanks to support of the 5FP project IST-30193 Research and Training Activities in System on Chip Design (Reason), the Estonian Science 2. DEFECTS, FAULTS, FAULT MODELS 51 Foundation grant G4300, the Polish State Committee for Scientific Research project No. 4 T11B 023 24 and the Slovak VEGA grant 2/2066/22. APPENDIX REFERENCES [1] M. L Bushnell, V. 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