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Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Study of CMOS Rectifiers for Wireless Energy
Scavenging
Examensarbete utfört i Elektroniska komponenter
vid Tekniska högskolan i Linköping
av
Aiysha Ali Khalifa
LiTH-ISY-EX--10/4359--SE
Linköping 2010
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
Study of CMOS Rectifiers for Wireless Energy
Scavenging
Examensarbete utfört i Elektroniska komponenter
vid Tekniska högskolan i Linköping
av
Aiysha Ali Khalifa
LiTH-ISY-EX--10/4359--SE
Handledare:
Atila Alvandpour
isy, Linköpings universitet
Examinator:
Atila Alvandpour
isy, Linköpings universitet
Linköping, 21 November, 2010
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Division of Electronic Devices
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
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2010-11-21
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LiTH-ISY-EX--10/4359--SE
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Titel
Title
Trådlös Energi Sophantering
Study of CMOS Rectifiers for Wireless Energy Scavenging
Författare Aiysha Ali Khalifa
Author
Sammanfattning
Abstract
In recent years, there has been recent increase in the deployment of wireless sensor
networks. These sensors are typically powered by a battery which has limited
life span. This problem can be overcomed by using energy scavenging or power
harvesting which is the process of converting ambient energy from the environment
into usable electrical energy. It can be used in applications such as remote patient
monitoring, implantable sensors, machinery/equipment monitoring and so on. The
thesis presents the RF scavenging system and mainly focuses on the study of the
rectifier architectures which is one of the key components in the RF scavenging
system. The thesis also provides the design challenges while implementing the
different rectifier structures, which are PMOS bridge rectifier, CMOS differential
rectifier and charge pump. The functionality of the rectifier structures are studied
by simulation using RF signal of 900 MHz and implemented in 0.35µm and 65 nm
technologies to compare the results. The simulation results shows that there is a
tradeoff between high output DC voltage and high power efficiency.
Maximum DC output voltage of 1 V is obtained from input amplitude level of
0.16 V using 7-stage charge pump rectifier. In the other hand maximum power
efficiency of 23 % is obtained using CMOS differential rectifier.
Nyckelord
Keywords
Energy Scavenging, Rectifier
Abstract
In recent years, there has been recent increase in the deployment of wireless sensor
networks. These sensors are typically powered by a battery which has limited
life span. This problem can be overcomed by using energy scavenging or power
harvesting which is the process of converting ambient energy from the environment
into usable electrical energy. It can be used in applications such as remote patient
monitoring, implantable sensors, machinery/equipment monitoring and so on. The
thesis presents the RF scavenging system and mainly focuses on the study of the
rectifier architectures which is one of the key components in the RF scavenging
system. The thesis also provides the design challenges while implementing the
different rectifier structures, which are PMOS bridge rectifier, CMOS differential
rectifier and charge pump. The functionality of the rectifier structures are studied
by simulation using RF signal of 900 MHz and implemented in 0.35µm and 65 nm
technologies to compare the results. The simulation results shows that there is a
tradeoff between high output DC voltage and high power efficiency.
Maximum DC output voltage of 1 V is obtained from input amplitude level of
0.16 V using 7-stage charge pump rectifier. In the other hand maximum power
efficiency of 23 % is obtained using CMOS differential rectifier.
v
Acknowledgments
Firstly, I would like to thank Allah for giving me the strength and blessings to
carry out this study.
I would like to express my sincere gratitude to my examiner and supervisor Atila
Alvandpour for offering me this opportunity and giving me valuable guidance and
encouragement throughout the work.
I am grateful to Sara Qazi for been a great friend and supporter all along the
master studies.
I am very thankful to my parents who have supported me unconditionally throughout my life.
Finally, I express my gratitude to all who supported me in any respect during the
completion of the master thesis.
vii
Contents
1 Introduction
1.1 Motivation for Energy Scavenging . . . . . . .
1.2 Generic Block Diagram for Energy Scavenging
1.3 Energy Scavenging Techniques . . . . . . . . .
1.3.1 Piezoelectric energy scavenging . . . . .
1.3.2 Solar energy scavenging . . . . . . . . .
1.3.3 Thermoelectric energy scavenging . . . .
1.3.4 Electrostatic energy scavenging . . . . .
1.3.5 Electromagnetic energy scavenging . . .
1.3.6 RF energy scavenging . . . . . . . . . .
1.4 Comparison of Energy Scavenging Methods . .
1.5 Organization of the Thesis . . . . . . . . . . . .
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2 RF Scavenging System
2.1 Near and Far Field Propagation . . . . . . .
2.2 RF Power Transmission . . . . . . . . . . .
2.2.1 Link budget . . . . . . . . . . . . . .
2.3 System Overview of RF Scavenging System
2.4 Rectification- RF to DC Conversion . . . .
2.5 Critical Issues in RF Scavenging System . .
2.5.1 Threshold of the scavenger . . . . .
2.5.2 Power conversion efficiency . . . . .
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13
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3 RF CMOS Rectifier Architectures
3.1 Bridge Rectifier . . . . . . . . . . . .
3.1.1 Conventional CMOS rectifier
3.2 Charge Pump . . . . . . . . . . . . .
3.2.1 Dickson charge pump . . . .
3.2.2 Voltage multiplier . . . . . .
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4 Simulation and Evaluation Results
4.1 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Effect of input amplitude on output voltage and PCE
4.1.2 Effect of transistor size on output voltage and PCE .
4.1.3 Effect of frequency on PCE . . . . . . . . . . . . . . .
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x
Contents
4.2
4.3
4.1.4 Effect of load resistance on output voltage and PCE .
Differential CMOS Rectifier . . . . . . . . . . . . . . . . . . .
4.2.1 Effect of input amplitude on output voltage and PCE
4.2.2 Effect of transistor size on output voltage and PCE .
4.2.3 Effect of load resistance on output voltage and PCE .
4.2.4 Effect of frequency on PCE . . . . . . . . . . . . . . .
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Effect of transistor size on output voltage and PCE .
4.3.2 Effect of number of stages on output voltage and PCE
4.3.3 Effect of frequency on output voltage and PCE . . . .
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36
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49
5 Comparison of Results and Conclusion
51
Bibliography
53
List of Figures
1.1
1.2
1.3
General block diagram of an energy harvesting system. . . . . . . .
Piezoelectric power generation [12]. . . . . . . . . . . . . . . . . . .
Diagram of electromagnetic power generator. . . . . . . . . . . . .
2.1
2.3
Communication link between base station ans sensor in passively
powered sensor network. . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram illustrating the RF-DC power conversion system in
a passively powered sensor. . . . . . . . . . . . . . . . . . . . . . .
Diode-connected PMOS transistor. . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Diode bridge rectifier. . . . . . . . . . . . . . . . . . . . . .
CMOS bridge rectifier. . . . . . . . . . . . . . . . . . . . . .
MOS transistor transient equivalent circuits. . . . . . . . . .
Conventional CMOS rectifier circuit[21]. . . . . . . . . . . .
External-Vth-cancellation CMOS rectifier circuit[17]. . . . .
Self-Vth-cancellation CMOS rectifier circuit[21]. . . . . . . .
Differential-drive CMOS rectifier[21]. . . . . . . . . . . . . .
Rectifier formed by cascading N rectifying cells in series[14].
Dickson charge pump . . . . . . . . . . . . . . . . . . . . . .
cascade charge pump . . . . . . . . . . . . . . . . . . . . . .
Single stage charge pump. . . . . . . . . . . . . . . . . . . .
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28
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
PMOS bridge rectifier. . . . . . . . . . . . . . . . . . . . . .
Output voltage dependence on input amplitude. . . . . . . .
PCE dependence on input amplitude. . . . . . . . . . . . .
Output voltage dependence on transistor size. . . . . . . . .
PCE dependence on transistor size . . . . . . . . . . . . . .
PCE dependence on operating frequency. . . . . . . . . . .
Output voltage dependence on load resistance. . . . . . . .
PCE dependence on load resistance. . . . . . . . . . . . . .
Schematic of differential CMOS rectifier. . . . . . . . . . . .
Output voltage dependence on input amplitude. . . . . . . .
PCE dependence on input amplitude. . . . . . . . . . . . .
Output voltage dependence on transistor size. . . . . . . . .
PCE dependence on transistor size. . . . . . . . . . . . . . .
Output voltage dependence on load resistance. . . . . . . .
PCE dependence on load resistance. . . . . . . . . . . . . .
PCE dependence on input amplitude at various frequencies.
7-stage charge pump test bench. . . . . . . . . . . . . . . .
Output voltage generated with and without load resistance.
Output voltage dependence on transistor size. . . . . . . . .
Output voltage for different number of stages. . . . . . . . .
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5.1
5.2
Input amplitude vs output voltage for different rectifier architectures. 51
Input amplitude vs PCE for different rectifier architectures. . . . . 52
2.2
4
5
8
14
16
17
2
Contents
List of Tables
1.1
1.2
Power density of different types of energy scavenging[22] . . . . . .
Comparison of the mechanical converters . . . . . . . . . . . . . .
4.1
Summary of the achieved result of the output voltage
different values in 65 nm technology. . . . . . . . . .
Summary of the achieved result of the output voltage
different values in 0.35 µm technology. . . . . . . . .
Summary of the achieved result of the output voltage
different values in 65 nm technology . . . . . . . . .
Summary of the achieved result of the output voltage
different values in 0.35 µ m technology. . . . . . . . .
Summary of the achieved result of the output voltage
different values in 65 nm technology. . . . . . . . . .
Summary of the achieved result of the output voltage
different values in 0.35 µm technology. . . . . . . . .
4.2
4.3
4.4
4.5
4.6
and PCE for
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and PCE for
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and PCE for
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and PCE for
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and PCE for
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and PCE for
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10
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45
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49
Chapter 1
Introduction
1.1
Motivation for Energy Scavenging
The vast advancement of wireless technology and low power electronics have increased the deployment of wireless sensor nodes. Batteries have been the primary
source of power for the wireless sensor. As the technology scales down, it is expected that the size of the battery decreases. However, the battery technology has
evolved very slowly compared to electronic devices [18]. The limited life time and
large physical dimension introduce an unwanted maintenance burden of replacement or recharging. The greatest potential however, lies in a new class of devices
that will be battery-free and thus enable applications that would have been prohibitively expensive due to the maintenance cost and repeated battery replacement
[18]. It is highly desirable to have an alternate power sources which overcome the
above limitation. This limitation can be solved through energy harvesting.
Power harvesting or energy scavenging is the process of acquiring ambient energy from the surrounding environment (vibration, thermal energy, light energy or
RF radiation) and converting it to a usable electrical energy. The potential benefit
of energy harvesting mechanism is that the life time of the electronic sensor is not
limited by the life time of the energy source. However, most of the harvestable
energy sources are not continuous due to the variation of the environmental conditions. Thus the amount of energy harvested may not be sufficient to power the
electronic sensor node. Hence, it is necessary to accumulate the energy for further
use and also the electronic device should have low power consumption. The combination of an energy harvester with a small-sized rechargeable battery or other
storage device is the best approach to power electronic sensor node over the entire
lifetime.
3
4
Introduction
1.2
Generic Block Diagram for Energy Scavenging
Figure 1.1. General block diagram of an energy harvesting system.
The four main building blocks of an energy harvesting system:
• Transducer
The transducer converts a harvestable energy which can be in the form of solar
energy, thermal energy, vibration or RF energy into electrical energy, through an
antenna, solar cell, a piezoelectric device, or other various forms. The produced
output from the transducer can be in a DC form or in AC form depending on the
energy source.
• Power conversion
The power conversion circuit can be a rectifier or DC-DC converter which can
converts the obtained energy into a usable DC voltage. The efficiency of the
circuit is an important factor which indicates the amount of the useful energy that
can be utilized by the application.
• Power management
Depending on the application and the voltage available at the power conversion
circuit, the output voltage of the power conversion circuit can be regulated to
a stable DC voltage using buck or boost converter or it can limited by voltage
limiter. The power management circuit controls the conduction path between the
device and energy harvester [5].
• Charge storage
The charge storage is used to hold the charge and store it in a capacitor or a
rechargeable battery or other storage element. When selecting a rechargeable element, it is important to consider the ability of the battery/capacitor to withstand
1.3 Energy Scavenging Techniques
5
a high number of charge/discharge cycles and maintain its performance characteristics. Super-capacitors, traditional capacitors, and thin film batteries are known
for their ability to retain performance even after a high number of charge/discharge
cycles [22].
1.3
Energy Scavenging Techniques
Energy scavengers can be obtained from different energy sources, then converted
to the usable electrical energy using specific circuits. In this section some of the
energy scavengers are discussed:
1.3.1
Piezoelectric energy scavenging
Piezoelectric energy scavenger is one of the promising energy scavenging techniques
for micro-power generators, which generates an electric charge as the result of a
force exerted on a piezoelectric material. Before subjecting the material to some
external stress, its internal structure is in neutral. While exerting some pressure on
the material, its internal structure can be deformed which causes polarization of the
material and hence, generates an electric field. Piezoelectric effect is the conversion
of mechanical energy such as vibration into electrical energy. Piezoelectric effect
is a reversible process where it also produces mechanical strain when electrical
energy is applied to the piezoelectric material. Due to these bi-directional effects,
piezoelectric materials are widely used for making sensors and actuators [12]. The
widely used piezoelectric material is Lead Zirconate Titanate (PZT).
Figure 1.2. Piezoelectric power generation [12].
The figure above shows the mechanical setup of a piezoelectric generator with
a cantilever and proof mass, where the piezoelectric material is mounted on a
long thin cantilever beam and directly connected between the mass and the frame.
When the beam/mass structure oscillates, the piezoelectric structure deforms and
causes a charge to be displaced across the capacitor electrodes positioned on the
top and bottom surfaces of the piezoelectric elements, a voltage then appears across
the capacitor and a current will flow through the load. The power generated from
this system is proportional to the proof mass, to the square of acceleration, and
inversely proportional to the resonant and excitation untitled folder frequency [12].
6
Introduction
Most conventional power supplies have low internal impedance, but the piezoelectric generator has high impedance. This restricts the amount of the output
current which relatively reduces the output voltage, hence makes it challenging in
designing power conversion circuitry.
1.3.2
Solar energy scavenging
Photovoltaics(PV) is the direct conversion of light into electricity. Some materials exhibit a property known as the photoelectric effect, that causes them to
absorb photons of light and release electrons. Movement of these free electrons results in an electric current. PV cells are made of semiconductor materials such as
crystalline which behave as a voltage limited current source. The output current
depends on the extent of light radiation, the size of the PV cell and on the time
varying load impedance as the PV cell has current source-like behavior. PV conversion has potentially long life time, higher output level (10mW/cm2 ) compared
to other types of energy harvesting. However, the varying light intensity affects
the output power.
1.3.3
Thermoelectric energy scavenging
Thermoelectric energy scavenger makes use of the thermal energy that is ubiquitous in the environment. To harvest thermal energy, thermoelectric devices are
required to convert the temperature difference between two junctions to electricity. The direct conversion of temperature difference to electric voltage and vice
versa is called as thermoelectric effect. There are three kinds of thermoelectric effects which include: the Seebeck effect, the Peltier effect and the Thomson effect.
The Seebeck effect is responsible for the production of a voltage by a temperature
gradient.
By applying a temperature difference across the junctions of a conducting
material, a voltage V will be generated in the circuit,
V = αab δT
(1.1)
where δT = (TH − TC ) is the temperature difference across the two junctions and
αab is the Seebeck coefficient. The generated voltage is proportional to the temperature difference across the junction, hence large thermal gradient is necessary to
obtain reasonable voltage. The most attractive feature of a thermoelectric device
is its capability of converting body heat into electricity which can power medical
implants, wireless devices and other electronics devices. A successful example in
this attempt is the thermoelectric wristwatch developed by Seiko [2] and Citizen
[1] are successful examples of thermoelectric generator which convert heat from
the wrist into electrical energy. The thermoelectric generator produces a power of
at least 1.5µW when the temperature difference is in the range of 1◦ C to 3◦ C [15].
1.3.4
Electrostatic energy scavenging
Electrostatic energy scavenger converts a mechanical energy into electrical energy
by moving a part the pre-charged plate of capacitors. There are two possible
1.3 Energy Scavenging Techniques
7
energy conversion cycles, charge constrained conversion and voltage constrained
conversion [16]. The conversion is based on which property (charge or voltage) is
held constant during the conversion process while the other changes in response
to a varying capacitance.
In charge constrained, the charge is held constant. Moving apart the capacitor
plates due to the applied vibration decreases the capacitance, this necessarily
increases the voltage across the device to maintain constant charge.
Qconst =
1
CV
2
(1.2)
Increase in the voltage increases the net energy stored in the capacitor, as shown
in the equation below,
1
E = CV 2
(1.3)
2
However, the increased voltage can be very large compared to the breakdown
limit of the CMOS technology, for instance, a 100-to-1 pF variation produces a
2.7-to-270 V change across the capacitor [16]
In the voltage-constrained method, the voltage across the capacitor is held
constant. When the capacitance decreases due to separation of the plates of the
capacitor, the charge flows out of the capacitor.
Q=
1
CVconst
2
(1.4)
Mechanical energy is required to move the capacitor plates, and thereby the charge
that flow out of the capacitor is harvested and stored for further use. However, to
maintain constant voltage in the capacitor, a voltage source is required, which is
not optimal,
1.3.5
Electromagnetic energy scavenging
Electromagnetic energy harvesting is based on Faraday’s electromagnetic induction. It converts mechanical energy into electrical energy. A coil is attached to an
oscillating mass which traverses magnetic field produced by a stationary magnet
as shown in the figure below:
When a coil travels through a varying magnetic flux, a voltage is induced. Similarly, a voltage is induced when the coil is kept fixed and the magnetic structure is
moved. The voltage or electromotive force (emf) induced in the circuit is directly
proportional to the time rate of change of flux linkage of the circuit.
V =−
dφ
dt
(1.5)
where, V is the induced voltage and Φ is the flux linkage. In this implementation,
the circuit consists of a coil of multiple turns and permanent magnet which creates
the magnetic field. The voltage induced in N turns coil is given as:
V = −N
dΦ
dt
(1.6)
8
Introduction
Figure 1.3. Diagram of electromagnetic power generator.
Φ = N BA
(1.7)
where, N is the number of turns in a coil, B is the magnetic field flux density
over the area A. The voltage induced can also be expressed as the product of flux
linkage and the velocity,
V = −N
dΦ
dΦ dx
= −N
dt
dt dt
(1.8)
The power can be extracted by connecting the coil terminal to load resistance
RL and allowing the current to flow through it. The interaction between the field
from the induced current and the magnetic field give rise to a force which opposes
the motion. By acting against the electromagnetic force Fem , the mechanical
energy is converted to electrical energy. The electromagnetic force is expressed as
the product of electromagnetic damping Dem and velocity.
dx
(1.9)
dt
The power extracted from the electromagnetic force is the product of the electromagnetic force and the velocity.
Fem = Dem
dx
dt
The power dissipated in the coil and load impedance is given as:
P =
P = Fem
(1.10)
V2
RL + Rc + jwLc
(1.11)
where, Rc is the coil resistance and Lc is the coil inductance. Using equation 1.8,
1.9, and 1.10 the electromagnetic damping can be given as:
Dem =
2
N 2 ( dφ
dt )
RL + Rc + jwLc
(1.12)
1.3 Energy Scavenging Techniques
9
From the above equations, it is shown that to extract maximum power, the
electromagnetic damping must be increased, that is by maximizing the flux linkage
and minimizing the coil impedance.
1.3.6
RF energy scavenging
RF energy scavenger is one of the most popular power extraction methods for passively powered devices. It harvest power from propagating radio frequency (RF)
signals [6], which can be generated by cellular phones, local area network and
other wireless devices. RF powered devices are often part of telemetry systems
to remotely measure and report data back to a central processing unit [6]. It is
also used in applications such as structural monitoring, access control, equipment
monitoring and personal identification. Devices powered by propagating RF waves
are most often used in passive radio frequency identification (RFID) or passive RF
tag[6][9]. The harvested power depends on the distance of the harvester from the
power source, another phenomenon like multipath fading, reflection and absorption affect significantly the RF input power level. RF energy scavenging will be
discussed in detail in the later sections.
10
Introduction
1.4
Comparison of Energy Scavenging Methods
The main performance metrics that are commonly considered when selecting an
energy harvester are:
• Power density
The harvestable energy source tends to provide highly fluctuating amount of energy, hence, it is characterized by its power density as it depends on how long
the source is in operation [9]. The power density determines the life span of the
device.
• Efficiency
The efficiency measures the effectiveness of the energy scavenging system in converting the environmental energy into electrical energy.
• Integration
It is the ability of the energy harvester to be integrated on a chip.
A comparison of different types of energy harvesting is given in Table 1.1.
Table 1.1. Power density of different types of energy scavenging[22]
Energy Source
Radio Frequency
Light
Vibration
Thermal
Characteristics
GSM 900 MHz
WiFi 2.4 GHz
Outdoor
Indoor
Humans-Hz
Machines-KHz
Human
Industrial
Power Density
0.1µW/cm2
1nW/cm2
100mW/cm2
100 µW/cm2
6 µW/cm2
800 µW/cm2
60 µW/cm2
100 mW/cm2
Efficiency
50%
Integration
Easy
10-50%
Possible
25-50%
Difficult
0.1%
3%
Difficult
The power density obtained from the solar energy has the maximum power
density, but it decreases with the variation of environmental condition. Since the
power density of the harvestable energy is not constant, it is necessary to store
significant amount of the harvested energy to make it a feasible power source.
From the above harvestable energy, piezoelectric, electromagnetic and electrostatic energy require mechanical energy (vibration) to provide electrical energy.
The comparison of those mechanical converters is given in the table below.
1.5 Organization of the Thesis
11
Table 1.2. Comparison of the mechanical converters
Mechanism
Piezoelectric
Advantage
No voltage source is required
Electrostatic
Easy to integrate in micro-systems
Electromagnetic
No voltage source is required
1.5
Disadvantage
More diffcult to integrate in microsystems
Separate
voltage
source is required
Difficult to operate
at optimum condition when the size is
scaled down
Organization of the Thesis
The thesis discusses the design and study of RF-DC converter architectures and
presents some of the various energy scavenging methods. Chapter 2 discusses the
RF scavenging system and how it is possible to transmit RF energy wirelessly. It
also discusses the parameters that affect the RF transmission and estimates the
available RF energy required for harvesting using link budget.
Chapter 3 discusses about rectification and the main parameters of the rectifier.
Chapter 4 provides the various rectifier architectures and their analysis.
Chapter 5 presents the simulation results of the rectifier architectures and the
effects of various parameters on the output voltage and on the power conversion
efficiency of the rectifier.
Chapter 6 provides the conclusions of this work.
Chapter 2
RF Scavenging System
In the earlier chapter various forms of harvestable energy have been discussed.
One of the most popular power extraction methods for passively powered devices
is to harvest power from propagating radio frequency (RF) signals [6].
2.1
Near and Far Field Propagation
RF energy harvesting is widely used in passive RFID (Radio Frequency Identification) system. Passive RFID stores and retrieve data via electromagnetic
transmission to a radio-frequency compatible integrated circuit without using a
battery. Energy transfer is the way by which passive RF devices are powered [3].
The energy transfer mechanism is based on near-field propagation and far-field
propagation of electromagnetic waves. Near field propagation employ inductive
and capacitive coupling, where, inductive coupling is the transfer of energy between two electronic circuits due to mutual inductance between them. Similarly,
capacitive coupling is the transfer of energy between two electronic circuits due to
mutual capacitance between them [3].
Inductive coupling uses the magnetic field produced by the information signal
to induce current in a coiled antenna. The current induced charges the capacitor
to provide the operating voltage and power for the device. Near field coupling
generally operates in the LF (Low Frequency) and HF (High Frequency) band
with relatively short reading distance. It has been used in transformers, electric
motors, medical telemetry, RFID and so on.
In far field coupling the antenna is comparable in size to the wavelength. It
is applicable for longer reading distances as it operates in UHF and microwave
bands. In far field system, the propagation energy drops off rapidly with distance.
2.2
RF Power Transmission
RF powered devices harvest their power from RF wave radiation transmited from a
radiant source or base station. Fig 2.1 illustrates the communication link between
13
14
RF Scavenging System
Figure 2.1. Communication link between base station ans sensor in passively powered
sensor network.
the radiating source which transmit RF signal and the multiple sensors. The
maximum power transmitted decreases as the distance from the transmitter and
the receiver increases. The operating range vary with the power contained in the
wave transmitted, sensitivity of the receiving equipment, environment through
which the wave travels and presence of interferences. The transmitting station for
RFID typically operates in the ISM band (industrial, scientific or medical) which
is controlled by FCC (Federal Communications Commission). FCC regulations
limit the amount of power that can be transmitted.
2.2.1
Link budget
To estimate the available energy that can be carried by a RF signal and how much
of its energy can be harvested by the wireless device, it is essential to calculate
the power budget. Link budget accounts for all the gains and losses from the
transmitter through the medium to the receiver. Generally the received power is
calculated as,
received power[dBm] = Transmitted power[dBm]−Losses[dB]+Gains[dB] (2.1)
The amount of power that can be transmitted between 902 and 928 MHz ISM
band is 30 dBm before the antenna according to FCC regulations. If 6 dB gain of
antenna is added, then the maximum allowed power is 36 dBm which correspond
to 4 W. However, most of the power is lost in the transmission medium, which is
called free space loss. The free space loss is governed by Friis transmission equation
which gives an ideal estimate of the received powered, provided the transmitted
power and the operating distance from the transmitter to the receiver are known.
λ 2
)
(2.2)
4πR
where, Pr and Pt are the received and the transmitted power respectively, Gr and
Gt are the antenna gain of the receiving and transmitting antenna respectively,
Pr = Pt Gr Gt (
2.2 RF Power Transmission
15
λ is the wavelength of the transmitted signal and R is the distance between the
transmitter and the receiver. From the Friis formula, the free space loss is given
as:
4πRf 2
F SL = (
)
(2.3)
c
For example if 900 MHz frequency and 10 m operating distance are used, then the
free space loss is found to be 51.52 dB. Thus the received power calculated from
the above equation is -15.5 dBm corresponding to 28 µW. The estimated voltage
that can be received is less than 74 mV, if 50 ohm antenna is used.
16
RF Scavenging System
2.3
System Overview of RF Scavenging System
Figure 2.2. Block diagram illustrating the RF-DC power conversion system in a passively powered sensor.
Block diagram of the RF scavenging system is shown in figure 2.2. It illustrates
the method of conversion of ambient RF energy emitted by various sources such
as TV signal, wireless radio networks, base stations onto a feasible DC voltage.
The main components of RF energy scavenging system are:
• Antenna
The antenna design is critical in designing RF scavenging system since it must
captures RF signals generated by multiple RF sources. The antenna is designed to
have high gain and small return loss over wide range of frequencies. The antenna
should also have a small size so it can be integrated on a chip.
• Matching network
As the received RF signal is very small, impedance matching between the
antenna and the input of the rectifier circuit is required to obtain the maximum
achievable power. Passive voltage amplification is also achieved by using high Q
impedance matching.
2.4 Rectification- RF to DC Conversion
17
• Rectifier
The harvested RF signal is converted into a DC voltage by using RF-to-DC converter (rectifier). It will be discussed in detail in later sections.
• Power Storage and Management
The ambient RF signal source is not always readily available, hence, it cannot
provide steady power all the time. Therefore, power management is required to
provide a regulated output voltage. The DC-DC converter is often used to provide
a regulated voltage or to boost the voltage level. The obtained DC voltage can be
stored in a battery or a super capacitor for later use.
2.4
Rectification- RF to DC Conversion
An efficient power conversion system is required to convert power from the incident
electromagnetic waves to a DC voltage. The rectifier is the basic part of the DC
voltage generation circuit, which comprises mainly of a diode. Large losses in the
rectifier must be avoided, because the typical output power of the energy harvester
(antenna) is in the micro-watt range. It is also obvious that with decrease in power
level, the input voltage also decreases. Hence, it is challenging to build a rectifier
that extract very low level of power from the incident EM radiation.
In this thesis the focus is on CMOS rectifier. Diode is the main component
in a rectifier, which allows one-way flow of electrons. PN junction diode has a
threshold voltage of 0.7 V, thus the input must exceed the threshold voltage to
operate the rectifier. Hence, this is not suitable for rectifying low level signals.
Whereas, schottky diode has low threshold voltage, low conduction resistance,
low junction capacitance, and large saturation current. However, Schottky diode
is incompatible with standard CMOS circuits. While implementation of CMOS
rectifier, the diode is replaced by a diode-connected transistor i.e connecting the
gate and the drain terminal. When considering a diode-connected PMOS, the
Figure 2.3. Diode-connected PMOS transistor.
substrate is connected to its source. When the source has a higher voltage than
the drain, there will be a current flowing from source to drain, which means that
the diode turns on when it is forward-biased. On the other hand, when drain has
a higher voltage than the source, the diode is reverse-biased. By connecting the
substrate of PMOS to the highest voltage and substrate of NMOS to the lowest
voltage, the leakage currents and latch up can be avoided.
18
2.5
2.5.1
RF Scavenging System
Critical Issues in RF Scavenging System
Threshold of the scavenger
In a CMOS rectifier circuit, the typical threshold voltage of a MOS transistor
ranges between 0.2-0.6 V. The power required to overcome the threshold voltage
with typical 50 ohm input impedance can be calculated from the equation below.
P =
2
Vrms
R
(2.4)
The power required to turn on the transistor translates to 0.4 mW to 3.6 mW,
which corresponds to the dead zone of the rectifier. The minimum power required
to overcome the rectification dead zone is called the power-up threshold of the
harvester [4].
According to Friis equation, to obtain the required power to turn on the transistor, the distance of operation is calculated to be 2.65 m-0.88 m at 900 MHz
frequency. Those distances are considered to operate in the near field. In order
to harvest power for longer operating distances, the threshold voltage should be
minimized.
From the previous section, the maximum input voltage that can be received
from 3.6 mW input power is 0.074 V, which is very small to turn on the CMOS
transistor. There is also some other solutions used to reduce the threshold voltage
which are the floating gate devices[13]. Impedance transformation boosts the
voltage level of the input signal, by employing matching network between the
antenna and the rectifier circuit.
2.5.2
Power conversion efficiency
Power conversion efficiency (PCE) is defined as the ratio of the power dissipated
by the load to the total energy consumed by whole circuit. It can also defined as
the ratio of output DC power to the input RF power.
P CE =
Pout
∗ 100
Pin
(2.5)
The RF power available for extraction is in the range of micro-watt, thus it is
required to utilize the power without losses. But according to maximum power
transfer theorem, half of the power is available for delievery to the load under
matched input conditions. Impedance matching network between the antenna
and the rectifier increases the PCE of the system.
Chapter 3
RF CMOS Rectifier
Architectures
The RF rectifier is a key component in a wireless sensor networks and RFID
applications. It converts the input RF signal into DC voltage to power up the
system. Rectifiers can be broadly categorized in two types, half wave rectifier
and full wave rectifier. The simplest of all the rectifier circuits is the half-wave
rectifier which uses a single diode that conducts current in one direction. It is
inefficient as it just uses one half of each complete sine wave of the RF signal to
convert it to a DC voltage. In the other hand, full wave rectifier makes use of the
whole input signal to deliver a DC signal. There are several ways of connecting
diodes to make a rectifier, but bridge rectifier is the most popular version. In this
section conventional CMOS bridge rectifiers and voltage multiplier are going to be
discussed.
3.1
Bridge Rectifier
A full wave bridge rectifier along with a capacitor converts both polarities of the
input signal to a DC signal. The arrangement requires four diodes as shown in fig
3.1, whereby, a pair of diodes is responsible for rectification of each signal cycle.
When the input voltage is higher than the output, a diode conducts to deliver
power to the load and the other regulates the current path from the load to the
ground [8]. This structure benefits from high power efficiency and smaller output
ripple compared to half wave rectifier. However, threshold voltage drop of two
diodes are lost in each signal cycle.
The rectified output voltage is given by,
Vout = 2Vin − 2Vth
(3.1)
As the MOS transistor is the main part of the rectifier structure, it is worth
to analyze the equivalent circuit of the MOS transistor. The power consuming
19
20
RF CMOS Rectifier Architectures
Figure 3.1. Diode bridge rectifier.
Figure 3.2. CMOS bridge rectifier.
Figure 3.3. MOS transistor transient equivalent circuits.
elements in the equivalent circuit are mainly substrate-drain diode, substratesource diode and channel resistor. So most of the power is consumed by the
channel resistance which is the resistance between the source and the drain, MOS
diodes and the load resistance. To increase the power efficiency of the rectifier, the
turn on voltage of the transistor should be small and the channel resistance also
should be decreased. To obtain small channel resistance, larger transistor size is
required which contribute to large CMOS diodes and parasitic capacitances which
can introduce greater leakage current and parasitic losses.
3.1.1
Conventional CMOS rectifier
A variety of conventional full wave rectifier have been addressed in [8][23] [7] [20]
[10] [21] [11]. A conventional CMOS rectifier circuit [11], which is composed of
series connection of diode-connected NMOS and PMOS transistors is shown below.
The RF input is applied through the coupling capacitor Cc . During the positive
3.1 Bridge Rectifier
21
Figure 3.4. Conventional CMOS rectifier circuit[21].
half cycle of the RF voltage signal, forward current flows to the output load. When
negative half cycle of the RF voltage signal is applied, almost no current flows.
The output voltage that is developed across the load is given as,
Vout = 2Vrf − Vdrop
(3.2)
Most of the power losses of the integrated rectifier circuit originate from the
on-resistance of the transistor. The PCE of the rectifier circuit is affected by
circuit topology, diode parameters, and input RF signal level [20][10]. Small ONresistance and small reverse leakage current are the main parameters of the MOS
diode which can increase the PCE of the rectifier. Generally, small on-resistance
of the MOS-diode is achieved by small turn on voltage of the transistor that is the
threshold voltage of the transistor. It is thus desirable for the threshold voltage
of the transistor to be as small as possible to decreases the losses in the rectifier
circuit. The voltage drop across a MOS diode is given as,
s
2LI
δV = Vth +
(3.3)
Cox W µ
where, W and L are the width and length of the transistor, I is the current flowing
and Cox is process related product and Vth is the threshold voltage of the transistor. The voltage drop not only related to the threshold voltage, but also depend
on the overload voltage, which linearly increases with square root of the current.
As the threshold voltage is the main parameter which can degrade the performance of the rectifier, appropriate Vth-cancellation mechanism is applied, which
are External-Vth-cancellation (EVC) scheme [21], Self-Vth-cancellation (EVC)
scheme [11] [20], and Internal-Vth-cancellation (IVC) scheme [17].
External-Vth-cancellation (EVC) scheme
The output voltage that can be obtained from conventional rectifier as discussed
above is given as:
Vout = 2 ∗ (Vrf − Vth )
(3.4)
Maximum output voltage is obtained when threshold voltage is negligible. In
this scheme a bias voltage is added between the gate and drain of the transistor.
22
RF CMOS Rectifier Architectures
Figure 3.5. External-Vth-cancellation CMOS rectifier circuit[17].
Thereby the threshold voltage changes to Vth − Vbias . The output voltage can be
rewritten as:
Vout = 2 ∗ (Vrf − Vth + Vbias )
(3.5)
The threshold voltage is expected to reduce to zero when Vth is nearly equal to
Vbias , then the output voltage can be approximated as,
Vout = 2Vrf
(3.6)
Therefore, it is possible to rectify small RF signals with this structure. However,
it is not optimal due to the additional batteries used.
Self-Vth-cancellation (SVC) scheme
The developed self-Vth-cancellation (SVC) CMOS rectifier circuit [11] [20] is shown
figure 3.6. In self-Vth-cancellation rectifier, the gate of the NMOS and PMOS
transistors are cross-connected such that the NMOS transistor and The transistors
Figure 3.6. Self-Vth-cancellation CMOS rectifier circuit[21].
are connected to the output terminal and ground terminal respectively as shown
in the figure. This connection increases the gate-source voltage of the transistor
which equivalently decreases the threshold voltage.
3.1 Bridge Rectifier
23
This scheme is simple and does not require any additional power circuitry.
Gate-source voltages of the NMOS and PMOS transistors are statically biased
using the output DC voltage, thus reducing the effective Vth of the MOS transistors [20], which result in large PCE. In this configuration, the energy loss mostly
depends on the on-resistance of the transistor. When the threshold voltage is too
small, it may cause reverse leakage current which will reduce the PCE. Hence it is
not possible to achieve small on-resistance and small leakage current in self-Vthcancellation rectifier. As a result, PCE of the SVC rectifier circuit will first increase
with the increase in input power, but then decrease with the further increase in
input power, exhibiting some peak value in between [10].
CMOS differential rectifier
According to SVC scheme rectifier it is not possible to achieve small on-resistance
and small leakage current simultaneously. In order to solve the problem differential-
Figure 3.7. Differential-drive CMOS rectifier[21].
drive CMOS rectifier circuit has been developed [20] [10]. It consist of a crosscoupled differential CMOS with a bridge structure. In this differential structure,
the gate of the transistor is biased by a differential signal. From the figure, Vx and
Vy are the differential input RF signal. When Vx is negative then the transistor
MN1 is forward biased and when Vy is positive which correspond to positive gate
voltage bias of MN1 transistor, which decreases the threshold voltage of the transistor. This results in small on-resistance. Whereas, when Vx is positive and Vy
is negative, the transistor is reversed biased and the gate voltage decreases which
increase the threshold voltage, resulting in reduction in reverse leakage current.
This kind of rectifier performs better than the MOS-diode based rectifier. It
is also called four-transistor cell according to [14] and called negative voltage
converter according to [19]. The structure consists of combination of two crossconnected gate structure which provide complimentary bridge rectifier. In the
circuit, the PMOS transistor delivers highest voltage to the load, whereas the
NMOS-transistor provide the lowest voltage. The transistor operates in the triod
24
RF CMOS Rectifier Architectures
region which behaves as a switch, thereby having smaller voltage drop compared
to MOS-diode. The output voltage is given as,
VDC = 2VRF − Vdrop
(3.7)
where, VRF is the amplitude of the differential signals and Vdrop is the losses
due to swich resistance and reverse conduction. The maximum output voltage is
limited to 2VRF . To increase the output voltage, N cells of the structure can be
cascaded. Differentials signal of the first stage is directly connected to to the RF
source whereas, the proceeding stages are capacitivly coupled to the RF source.
This structure behaves as a charge pump voltage multiplier [14], as the expected
output voltage at the N’th stage is VDC = N (2VRF − Vdrop ) but in practice the
output voltage is lower because the Vdrop increases with the increase of the number
of cells due to increase of the body bias of the transistor.
Figure 3.8. Rectifier formed by cascading N rectifying cells in series[14].
3.2 Charge Pump
3.2
3.2.1
25
Charge Pump
Dickson charge pump
Charge pump circuit generates higher output voltage from lower input signal.
It has been widely used in non-volatile memories such as EEPROM and flash
memories. The basic charge pump architecture is proposed by Dickson in 1976.
Figure 3.9. Dickson charge pump
This kind of charge pump consists of diodes and two non-overlapping pumping
clocks φ1 φ2 , whose amplitude is the supply voltage Vφ and is capacitively coupled
to alternate nodes along the diode chain. It is operated by pumping charges
through the diodes and thereby charging the capacitors each clock cycle. At each
node the voltage increases progressively from the input to the output of the diode
chain by Vφ . However, the total output voltage is affected by a voltage drop VD
of the diode. The output voltage of a dickson charge pump is given as:
Vout = Vin + N (Vφ − VD ) − VD
(3.8)
where, N is the number of stages of the charge pump. The extra VD in the
equation is because of the last diode available out of the chain. This kind of
charge pump implementation is not optimal for passive wireless devices, as it
require clock generation module which consume more power and area. To avoid
the clock generation module, the RF input signal is used to pump the charges
through the circuit where it rectifies the AC signal and increases the DC level.
3.2.2
Voltage multiplier
The N-stage voltage multiplier or cascade charge pump is based on the dickson
charge pump except that, it does not require a clock signals. The N-stage voltage
multiplier consists of a cascade of peak-to-peak detectors as shown in the figure
below. A peak detector is a series connection of a diode and a capacitor which
outputs a DC voltage equal to the peak value of the applied AC signal.
26
RF CMOS Rectifier Architectures
Figure 3.10. cascade charge pump
To describe the operation of the charge pump, a single stage charge pump is
analyzed. During the negative half cycle of the RF signal, when Vn−1 > Vin + Vth ,
Figure 3.11. Single stage charge pump.
the transistorMn−1 turns on while transistor Mn turns off as Vc < VN and the
charge transfers from capacitor CV (N −1) to capacitor Cc . At this cycle the node
voltage at Vc is given as Vin + Vn−1 − Vth . When the input changes to the positive
half cycle the transistor Mn−1 turns off while transistor Mn turns on and the charge
transfer from Cc to capacitor Cn . The available voltage at Cn is given as
Vn = Vn−1 + 2Vin − 2Vth
(3.9)
3.2 Charge Pump
27
The maximum voltage that can be achieved in a single stage charge pump is twice
the RF amplitude minus twice the threshold voltage of the MOS diode. The output
voltage of N’th stage charge pump is given as:
Vn = 2N (Vin − Vth )
(3.10)
From the above equation it is obvious that the threshold voltage has a drastic
effect on the the output voltage. To obtain a decent voltage from small input RF
signal, the threshold voltage must be minimized. Other way to increase the output
voltage is by increasing the number of stages. However, increasing the number of
stages causes to degradation of power dissipation and power conversion efficiency.
The threshold voltage also increases linearly with the increase of number of stages
due to the body effect, thus limiting the number of stages that can be cascaded.
The MOS transistor in the charge pump operate in saturation region due to
the short connection between gate and darin, the drain current in this region is
given as:
β
ID = .(VGS − Vt )2
(3.11)
2
W
(3.12)
L
According to the equation to ensure pumping of low input voltage, low threshold
voltage and small on-resistance of the transistor are required. To obtain small
resistance of the transistor, large transistors have to be used, leading to larger
parasitic capacitance and thereby increasing the leakage current. In the other
hand, if the transistor size is too small, then the charge transfer is incomplete
which leads to small output voltage and hence low efficiency. Hence to obtain
maximum output voltage and high efficiency, low threshold voltage and optimal
transistor size should be selected.
β = µn .Cox .
Chapter 4
Simulation and Evaluation
Results
In this section RF rectifiers are simulated in cadence environment using 0.35 µm
and 65 nm technology. The results have been analyzed, and effect of various
parameters on the output voltage and power conversion efficiency.
4.1
Bridge Rectifier
As discussed in section 3, the full wave bridge rectifier consists of four diode connected MOS-transistors connected in bridge form. The transistors can be NMOS
or PMOS, however, PMOS transistor is preferred to reduce the variation of threshold voltage due to body effect. The bridge rectifier suffers from low voltage and
efficiency not only because of the threshold voltage drop of two diode connected
transistor, in addition to the leakage current of two MOS diodes at every half
cycle. The effect of different parameters on the output voltage and on the power
conversion efficiency is given below.
Figure 4.1. PMOS bridge rectifier.
29
30
4.1.1
Simulation and Evaluation Results
Effect of input amplitude on output voltage and PCE
According to the simulation results, it is shown that increasing the input voltage
increases the output voltage linearly as shown in figure 4.2. Similarly, the PCE
increases for larger input voltage as shown in figure 4.3.
Figure 4.2. Output voltage dependence on input amplitude.
4.1 Bridge Rectifier
31
Figure 4.3. PCE dependence on input amplitude.
4.1.2
Effect of transistor size on output voltage and PCE
It is noticed from the graph 4.4 and 4.5 that the output voltage increases with the
transistor size since larger transistor size has small channel resistance. Similarly,
the PCE increases with larger transistor size.
32
Simulation and Evaluation Results
Figure 4.4. Output voltage dependence on transistor size.
Figure 4.5. PCE dependence on transistor size
4.1 Bridge Rectifier
4.1.3
33
Effect of frequency on PCE
The PCE decreases with higher frequency ranges. This rectifier structure is not
suitable for higher frequency as it suffer from lower PCE wit increasing the frequency.
Figure 4.6. PCE dependence on operating frequency.
34
4.1.4
Simulation and Evaluation Results
Effect of load resistance on output voltage and PCE
Figure 4.7. Output voltage dependence on load resistance.
It is shown from the figure 4.7 and 4.8 that the PCE goes up with the load
resistance, but still the PCE cannot be very high for larger load resistance. This
is because of the increased power consumption. However, larger load resistance
gives higher output voltage.
4.1 Bridge Rectifier
35
Figure 4.8. PCE dependence on load resistance.
Summary of the achieved result of the output voltage and PCE for different
values of input amplitude for 0.35 µ m and 65 nm technology is given below:
Table 4.1. Summary of the achieved result of the output voltage and PCE for different
values in 65 nm technology.
Input amplitude (V)
Output voltage (V)
Power conversion
efficiency(%)
0.4
0.35
0.3
0.25
0.152
0.104
0.064
0.034
15.63
12.17
8.3
4.6
36
Simulation and Evaluation Results
Table 4.2. Summary of the achieved result of the output voltage and PCE for different
values in 0.35 µm technology.
4.2
Input amplitude (V)
Output voltage (V)
Power conversion
efficiency(%)
1
0.8
0.65
0.6
0.387
0.218
0.1
0.056
0.6
0.329
0.16
0.1
Differential CMOS Rectifier
The schematic of differential CMOS rectifier or four transistor cell rectifier is shown
below and it has been simulated in 0.35 µm and 65 nm technology. Differential
input signal with a 50 ohm resistance as of the antenna is used. The output voltage
obtained when input signal amplitude of 0.25 V is applied at 900 MHz frequency.
Capacitance of 10 pF and resistance of 8 k ohm are used as a filter which reduces
the ripple voltage to obtain a smoother output.
Figure 4.9. Schematic of differential CMOS rectifier.
Higher efficiency is obtained comparing to PMOS bridge rectifier. This is
because when the diode connected transistor is reversed biased, the source appear
connected to the gate. A large leakage current is available at Vgs =0. Whereas,
when a pair of cross connected transistor is reversed biased, the leakage current
produced is very small.
4.2 Differential CMOS Rectifier
4.2.1
37
Effect of input amplitude on output voltage and PCE
From figure 4.10, increasing the input voltage level increases the output voltage.
However, figure 4.11 shows that the PCE increases first and decreases with further
increase of the input voltage. The reason behind the decrease in PCE for higher
input voltage level is that higher input voltage level increases the VGS which causes
decrease in threshold voltage. In this case, reverse leakage current of the rectifier
increases which causes extra energy dissipation.
Figure 4.10. Output voltage dependence on input amplitude.
38
Simulation and Evaluation Results
Figure 4.11. PCE dependence on input amplitude.
4.2.2
Effect of transistor size on output voltage and PCE
The output voltage increases with the increase of the transistor size according
to figure 4.12. This is due to increase of transistor size decreases the channel
resistance of the transistor and hence increases the output voltage. However, larger
transistor sizes lead to larger parasitic capacitance which will lead to parasitic
losses. Hence, the PCE decreases for larger transistor sizes as it has been shown
in the figure 4.13.
4.2 Differential CMOS Rectifier
Figure 4.12. Output voltage dependence on transistor size.
Figure 4.13. PCE dependence on transistor size.
39
40
4.2.3
Simulation and Evaluation Results
Effect of load resistance on output voltage and PCE
Figure 4.14 shows the output voltage increases linearly with the load resistance.
However, figure 4.15 shows that with larger load resistance, the Peak PCE can
be obtained at a smaller input power. The peak PCE increases slightly with the
increase of the load resistance.
Figure 4.14. Output voltage dependence on load resistance.
4.2 Differential CMOS Rectifier
41
Figure 4.15. PCE dependence on load resistance.
4.2.4
Effect of frequency on PCE
The dependence of the PCE on the operating frequency is illustrated in figure
4.16. As the operating frequency increases, the PCE decreases. This is because
with the increase of the frequency, the energy loss increases due to increase of the
reactance component.
42
Simulation and Evaluation Results
Figure 4.16. PCE dependence on input amplitude at various frequencies.
4.2 Differential CMOS Rectifier
43
Summary of the achieved result of the output voltage and PCE for different
values of input amplitude for 0.35 µ m and 65 nm technology is given below
Table 4.3. Summary of the achieved result of the output voltage and PCE for different
values in 65 nm technology
Input amplitude (V)
0.4
0.35
0.3
0.25
0.2
Output voltage (V)
0.297
0.262
0.224
0.18
0.124
Power conversion efficiency(%)
11.56
14.14
17.9
23
26.78
Table 4.4. Summary of the achieved result of the output voltage and PCE for different
values in 0.35 µ m technology.
Input amplitude (V)
0.55
0.5
0.45
0.4
Output voltage (V)
0.309
0.222
0.122
0.047
Power conversion efficiency(%)
9.9
6.3
2.4
0.5
44
4.3
Simulation and Evaluation Results
Charge Pump
From the previous section, it was shown that as the number of stages in the charge
pump is increased, the output voltage is also increased, but this will also results
increase in internal impedance thereby decreasing the output drive current. To
increase the output current, the capacitance and the size of the transistor can be
increased, but these contribute to parasitic capacitance. Hence optimal number
of stages of the charge pump should be chosen. In the simulation, 7-stage charge
pump is used. The simulation setup has been shown in the figure below:
Figure 4.17. 7-stage charge pump test bench.
A sinusoidal signal is applied to the charge pump with a 50 ohm resistance as of
the antenna. A load resistance of 1 M ohm is used to represent a transmitter with
high impedance connected to the charge pump. The output voltage obtained from
7-stage charge pump using 0.15 V input amplitude of the signal is given below:
Figure 4.18. Output voltage generated with and without load resistance.
4.3 Charge Pump
45
The generated output voltage is nearly 1 V but when output load of 1 M ohm
is connected 0.25 V output voltage is obtained, however, this voltage can vary
with various parameter like transistor size, number of stages of the charge pump,
capacitance value, load resistance.
4.3.1
Effect of transistor size on output voltage and PCE
How the transistor size can affect the output voltage and PCE can be noticed
from figure 4.18. It is seen that as the transistor size increases the output voltage
Figure 4.19. Output voltage dependence on transistor size.
increases. This is due to the fact that large transistor sizes cause small resistance
of the transistor and thereby increasing the output current. Similarly, the power
conversion efficiency can be improved with large transistor size but not significantly.
46
4.3.2
Simulation and Evaluation Results
Effect of number of stages on output voltage and PCE
Figure 4.20. Output voltage for different number of stages.
As the number of stages of the charge pump increases the output voltage also
increases as shown in equation 3.10 and figure 4.20. However, as the numbers of
stages increases, the source voltage of the transistor increases, thereby increasing
the VSB voltage. Thereby increasing the threshold voltage, which can lead to
degradation of the power conversion efficiency.
p
p
Vth = Vtho + ( |2ΦF + VSB | − |2ΦF |)
(4.1)
where, VSB is the source-bulk potential difference, φ is the body effect coefficient.
4.3 Charge Pump
4.3.3
47
Effect of frequency on output voltage and PCE
To increase the output voltage, the number of stages need to be increased as
discussed earlier but this increases the internal impedance as represented in the
equation below.
N
Rs =
(4.2)
C ∗f
where, Rs is the internal impedance, N is the number of stages, C is the capacitance
and f is the operating frequency of the charge pump. The optional way to achieve
higher output voltage is to increase the frequency or the capacitance as increasing them reduces the internal impedance. A larger capacitor allow more charge
to be transferred and thus increases the output voltage, but larger capacitance
introduces parasitic capacitance, this can lead to a higher power consumption,
P = Cf V 2 . Hence, the power efficiency of the charge pump decreases with the
increased output voltage.
Summary of the achieved result of the output voltage and PCE for different
values of input amplitude for 0.35 µm and 65 nm technology is given below:
Table 4.5. Summary of the achieved result of the output voltage and PCE for different
values in 65 nm technology.
Input amplitude (V)
0.37
0.16
0.1
0.06
Output voltage without load (V)
2.7
1
0.5
0.22
PCE with 1 M ohm RL (%)
13.3
2.8
0.78
-
Table 4.6. Summary of the achieved result of the output voltage and PCE for different
values in 0.35 µm technology.
Input amplitude (V)
1
0.8
0.7
0.6
Output voltage without load (V)
1.375
0.743
0.446
0.226
PCE with 1 M ohm RL (%)
0.3
0.1
0.08
-
Chapter 5
Comparison of Results and
Conclusion
The choice of rectifier structure depends on the application in use. Charge pump
and the differential CMOS rectifier are the most promising. Charge pump is
suitable to generate the preferred output voltage level from too low input voltage,
but it suffers from low power efficiency due to the more stages incorporated which
increases the power consumption.
Figure 5.1. Input amplitude vs output voltage for different rectifier architectures.
49
50
Comparison of Results and Conclusion
Figure 5.2. Input amplitude vs PCE for different rectifier architectures.
On the other hand, to achieve better PCE the differential CMOS rectifier or
NMOS-PMOS cross-coupled structure is suitable but requires larger input voltage
compared to charge pump. It is also noticed that the differential CMOS rectifier
has higher efficiency for lower input voltage, but the PCE decreases for larger
input voltage.
The comparison between PMOS-bridge rectifier, differential CMOS rectifier,
and the charge pump are shown in Figure 5.1 and 5.2. It is noticed from the figure
that the charge pump can achieve the highest output voltage of 2.7 V using input
amplitude of 0.35 V. However, the maximum PCE is achieved using differential
CMOS rectifier of 23% at 0.25 V input amplitude. On the other hand, the PMOSbridge rectifier has the lowest output voltage and PCE.
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