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Realization of Current Conveyors-based Floating Simulator Employing Grounded Passive Elements Winai Jaikla* and Montree Siripruchyanun** *Electric and Electronic Program, Faculty of Industrial Technology, Suan Sunandha Rajabhat University, Dusit, Bangkok, 10300, THAILAND Email: [email protected] **Department of Teacher Training in Electrical Engineering, Faculty of Technical Education, King Mongkut’s Institute of Technology North Bangkok, Bangkok, 10800, THAILAND Email: [email protected] Abstract- A novel circuit for realizing floating inductance, floating capacitance, floating frequency dependent negative resistance (FDNR) and grounded to floating admittance converter depending on the passive component selection is proposed in this paper. The proposed simulator employs second-generation current conveyors (CCIIs), differential voltage current conveyor (DVCC) and only grounded passive elements. The non-ideal current and voltage gains as well as parasitic impedance effects on the proposed circuit are investigated. Also, simulation results using PSPICE program are given for the introduced floating simulator to verify the theory and to exhibit the performances of the circuit. II. PRINCIPLE AND OPERATION A. The Differential Voltage Current Conveyor (DVCC) The DVCC, whose electrical symbol and equivalent circuit are shown in Fig. 1, is a four-terminal network with the terminal ideal characteristics described by following equation !VX " !0 #I $ # # Y 1 $ % #0 # IY 2 $ #0 # $ # #& I Z $' &1 Index Terms- CCII, Capacitor, DVCC, FDNR, Inductor. I. INTRODUCTION Recently, a simulated immittance has become a standard research topic since it can be applied in areas like oscillator design, active filters and cancellation of parasitic elements [1]. The advent of integrated circuits has encouraged the design of synthetic inductances, which can be used instead of the bulky inductors in passive filters. Although it is difficult to implement inductors and floating capacitors in the integrated circuits, several published circuits [2-15] employing different high-performance active building blocks. The circuits given in [2–7] can realize floating inductor employing a grounded capacitor but the circuits [3–6] can realize floating FDNR employing floating capacitors, at least one of two capacitors is floating, which is not convenient to further fabricate in IC. Also, some circuits introduced in the literature can realize floating FDNR [10–15] and some of the circuits reported in the literature can realize floating capacitor [8-9]. The proposed circuit in [7] needs for passive element matching As a result, a circuit for the simulation of a floating inductance, capacitance, FDNR and grounded to floating admittance converter depending on the passive element choice is presented. The proposed circuit consists of CCIIs and DVCC as active components. In addition, the proposed circuit employs two to three grounded resistors and one to two grounded capacitors as passive components. The circuit can realize a lossless floating inductance and capacitance, and can convert the grounded admittance into the corresponding floating admittance without changing the original topology. Furthermore, the effects of non-ideal gains on the proposed simulator are considered. The PSPICE simulation results are also IY 1 IY 2 Y1 DVCC Z Y2 X IZ 1 1 0 " !IX " # $ 0 0 0 $$ #VY 1 $ . 0 0 0 $ #VY 2 $ $# $ 0 0 0 ' #&VZ $' Y1 Y2 (1) IY 1 % 0 1 IZ IY 2 % 0 Vd Z IX Vd % VY 1 VY 2 IX X Figure 1. The DVCC (a) Symbol (b) Equivalent circuit B. The Second Generation Current Conveyor (CCII) The characteristics of ideal CCII are represented by the following hybrid matrix ! IY " ! 0 0 0 " !VY " #V $ % #1 0 0 $ # I $ . (2) # X$ # $# X $ #& I Z $' #& 0 ( 1 0 $' #&VZ $' The symbol and the equivalent circuit of the CCCII are illustrated in Fig. 2(a) and (b), respectively. IY IX Y CCII Z IZ X VY VX iy ix iz 1 VZ ( ix Figure 2. The CCII (a) Symbol (b) Equivalent circuit C. Proposed floating simulator The proposed floating simulator is shown in Fig. 3. Straightforwardly analyzing circuit in Fig. 3, it gives the following short circuit admittance matrix shown, which are in correspondence with the theoretical analysis. ECTI-CON 2007 The 2007 ECTI International Conference ___________________________________________________________ 89 I1 Y1 DVCC1 Z Y2 X V1 V2 e) Y Z CCII 2 )Z X I2 Y1 Y2 *YC + % Y CCII 3 Z X Y f) CCII 4 Z X Y3 Y5 Y4 Y1Y2Y5 ! 1 Y3Y4 #& 1 1" . 1$' (3) For the proposed circuit, the following passive elements are chosen to achieve floating inductance, capacitance, FDNR and admittance converter, as following explained. a) If Y1 % sC1 , Y2 % G2 , Y3 % G3, Y4 % G4 and Y5 % G5 are taken for the circuit in Fig.1, the short circuit admittance matrix of the floating capacitance simulator is obtained as sC G G ! 1 1" ! 1 1" (4) *YC + % 1 2 5 # $ % sCeq # 1 1$ . G3G4 & 1 1' & ' Hence, Ceq % C1G2 G5 / G3G4 . b) If Y1 % G1 , Y2 % sC2 , Y3 % G3, Y4 % G4 and Y5 % G5 are chosen, the short circuit admittance matrix of the floating capacitance simulator is found to be sC G G ! 1 *YC + % 2 1 5 # G3G4 & 1 c) 1" ! 1 % sCeq # $ 1' & 1 1" . 1$' (5) Hence, Ceq % C2 G1G5 / G3G4 . If Y1 % G1 , Y2 % G2 , Y3 % sC3, Y4 % G4 and Y5 % G5 are obtained, the short circuit admittance matrix of the floating inductance simulator is found to be *YL + % G1G2 G5 ! 1 sC3G4 #& 1 1" 1 ! 1 % $ 1' sLeq #& 1 1" . 1$' (6) Hence, Leq % C3G4 / G1G2G5 . d) If Y1 % G1 , Y2 % G2 , Y3 % G3, Y4 % sC4 and Y5 % G5 are achieved, the short circuit admittance matrix of the floating inductance simulator is found to be G G G ! 1 1" 1 ! 1 1" . (7) % *YL + % 1 2 5 # $ sC4 G3 & 1 1' sLeq #& 1 1 $' G1G2 ! 1 y( s) # G3G4 & 1 1" ! 1 % ay ( s ) # $ 1' & 1 1" . 1 $' (8) Thus, a % G1G2 / G3G4 is defined as a multiplier, and y ( s) is the grounded admittance. If Y1 % sC1 , Y2 % sC2 , Y3 % G3, Y4 % G4 and Y5 % G5 are taken, the short circuit admittance matrix of the FDNR is found to be *YD + % Figure 3. Proposed floating simulator *Y + % Hence, Leq % C4 G3 / G1G2 G5 . If Y1 % G1 , Y2 % G2 , Y3 % G3, Y4 % G4 and Y5 % y ( s) are taken, the short circuit admittance matrix of grounded to floating admittance converter is calculated as s 2 C1C2 G5 ! 1 G4 G3 #& 1 1" ! 1 % s 2 Dd # 1$' & 1 1" . 1$' (9) Consequently, Dd % C1C2 G5 / G4 G3 is obtained. As the frequency increases, the absolute value of negative resistance decreases. g) If Y1 % G1 , Y2 % G2 , Y3 % sC3, Y4 % sC4 and Y5 % G5 are taken, the short circuit admittance matrix of the FDNR is found to be *YD + % G1G2 G5 ! 1 s 2 C4 C3 #& 1 1" Di ! 1 % 1 $' s 2 #& 1 1" . 1$' (10) Consequently, Di % G1G2 G5 / C4 C3 is obtained. As the frequency increases, the absolute value of negative resistance also increases. D. Non-ideal case For non-ideal case, the DVCC can be respectively characterized with the following equations IY 11 % IY 12 % 0 , VX % ,11VY 1 ,12VY 2 , IZ % - I X , (11a) (11b) (11c) While then non-idea of CCII can be respectively presented with the following equations (12a) IY % 0 , VX % , VY , (12b) (12c) IZ % - I X , (12d) IZ % . I X . - and . are the frequency dependent current gains besides ,i is the frequency dependent voltage gain. These gains are ideally equal to unity. In practice, they depend on the frequency of operation, temperature and transistor parameters of the DVCC and CCII. In the case of non-idea, the short matrix in Eq. (3) is converted to ECTI-CON 2007 The 2007 ECTI International Conference ___________________________________________________________ 90 *Y + % Y1Y2Y5 -1 , 2 Y3Y4 - 3- 4 , 3 , 4 !. 2 ,11 # - , & 2 11 . 2 ,12 " . - 2 ,12 $' (13) If parasitic resistances ( RX in series ideally equal to zero, RY % 1/ GY and RZ % 1/ GZ in parallel ideally equal to infinity) and parasitic capacitances ( CY and CZ in parallel ideally equal to zero) affecting the impedance of the circuit in Fig. 3 are considered, the following equations are obtained / Second port is grounded V 1 (14) // Z L . Z in1 % 1 % I1 sCY 11 ) GY 11 Hence, 0 sC ZL % 2 A 3 2 Y4 3 3 2 Y3 54 54 1) R Y 5 ) ) ) sC Y G R Y 1 6 B 5 B 76 X4 4 76 X3 3 7 . 2 Y1 3 2 Y2 3 41) R Y 541) R Y 5 6 X1 1 7 6 X2 2 7 ) GA 1 ) 4 1 Where C A % CY 2 ) CY 4 ) CZ 1 ) CZ 3 , GA % GY 2 ) GY 4 ) GZ 1 ) GZ 3 , CB % CY 3 ) CZ 4 and GB % GY 3 ) GZ 4 . / First port is grounded V 1 // Z L . Z in 2 % 2 % I 2 sCY 12 ) GY 12 (15) If Y1 % sC1 , Y2 % sC2 , Y3 % G3, Y4 % G4 and Y5 % sC5 are taken for the circuit in Fig.1, the circuit has limitations at high frequencies due to terms 1 ) RX 1 sC1 , 1 ) RX 2 sC2 s 0 CY 2 ) CY 4 ) CZ 1 ) CZ 3 1 ) GY 2 ) GY 4 ) GZ 1 ) GZ 3 s 0 CY 3 ) CZ 4 ) C5 1 ) GY 3 ) GZ 4 as given in Eq. (15) thus the limit at high frequencies is found as GY 3 ) GZ 4 2 GY 2 ) GY 4 ) GZ 1 ) GZ 3 4 C )C )C )C ,C )C )C 1 Y4 Z1 Z3 Y3 Z4 5 min 4 Y 2 f ! 4 1 1 28 , 4 6 C1 RX 1 C2 RX 2 " $ $. $ 1 $ Z p 2 // Z L $' 1 ZL (16) for the circuit in Fig.1 as the case d), the first developed circuit has limitations at low frequencies due to terms 1 ) RX 3 sC3 , 1 ) RX 4 sC4 , s 0 CY 2 ) CY 4 ) CZ 1 ) CZ 3 1 ) GY 2 ) GY 4 ) GZ 1 ) GZ 3 and s 0 CY 3 ) CZ 4 1 ) G5 ) GY 3 ) GZ 4 as given in Eq.(15) thus the limit at low frequencies is found as f (a) (17) Note that the term 1/ 0 sCY 11 ) GY 11 1 and 1/ 0 sCY 12 ) GY 12 1 in Eqs. (14) and (16) are effected at very high frequency. There are also high and low frequency limitations depending on the passive element selection. If Y1 % G1 , Y2 % G2 , Y3 % sC3, Y4 % sC4 and Y5 % G5 are taken 2 GY 2 ) GY 4 ) GZ 1 ) GZ 3 G5 ) GY 3 ) GZ 4 4 C )C )C )C , C )C 1 Y4 Z1 Z3 Y3 Z4 max 4 Y 2 4 1 1 28 , 4 6 C3 RX 3 C4 RX 4 3 ,5 5 . (19) 5 5 7 As seen from Eq. (19), C1, C2 and C5 should be chosen as small as possible in order to increase the high frequency performance. Also, if Z P1 % 1/ 0 sCY 11 ) GY 11 1 and Z P 2 % 1/ 0 sCY 12 ) GY 12 1 are defined, the short circuit admittance matrix in Eq. (3) turns to 1 ! # Z // Z p1 L *Y + % ## 1 # #& Z L and 3 ,5 5 . (18) 5 5 7 As it is seen from Eqn. (18), C3 and C4 should be chosen large in order to decrease the limit at low frequencies. (b) Figure 4. Internal construction of (a) CCII (b) DVCC III. SIMULATION RESULTS To prove the performances of the proposed circuit, the PSPICE simulation program was used for the examination. The PNP and NPN transistors employed in the proposed circuit were simulated by respectively using the parameters of the PR200N and NR200N bipolar transistors of ALA400 transistor array from AT&T [16] with (1.5V supply voltages and I B % 2009 A . Fig. 4 depicts schematic descriptions of the CCII and DVCC used in the simulations. Phase and magnitude responses for the impedances of the proposed circuit in Fig. 3 are given in Fig. 5 where the second port of the floating inductor is grounded. There can be seen that, in case of (a) and (b), the useful frequency ranges are about 1kHz to 3MHz and approximately 10kHz to 1MHz, in case of (c) and (d). In order to show the frequency domain performance of the proposed circuit, the second-order band-pass filter example in ECTI-CON 2007 The 2007 ECTI International Conference ___________________________________________________________ 91 Fig. 6 was simulated with PSPICE program. G1=G2=G4=G5=1mS and C3=1nF are chosen to obtain inductance value of 1mH. Furthermore, G2=G3=G4=G5=1mS and C1=1nF are taken to obtain capacitance of 1nF. Both of the ideal and simulated bandpass (Vo/Vin) filter responses is depicted in Fig. 7. The maximum power dissipation is about 20.09mW. REFERENCES [1] G. Ferri and N.C. Guerrini, Low-Voltage Low-Power CMOS Current Conveyors. Kluwer Academic Publishers, London, 2003. [2] E. Yuce, S. Minaei, and O. Cicekoglu, “Resistorless floating immittance function simulators employing current controlled conveyors and a grounded capacitor.” Electrical Engineering, vol.88, pp. 519–525, 2006. [3] E. Yuce, O. Cicekoglu, and S. Minaei, “Novel floating inductance and FDNR simulators employing CCII+s.” Journal of Circuits, Systems and Computers, vol. 15, no. 1, pp. 75–81, 2006. [4] E. Yuce, O. Cicekoglu, and S. Minaei, “CCII-based grounded to floating immittance converter and a floating inductance simulator.” Analog Integrated Circuits and Signal Processing, vol. 46, no. 3, pp. 287–291, 2006. [5] S. Minaei, E. Yuce, and O. Cicekoglu, “A versatile active circuit for realizing floating inductance, capacitance, FDNR and admittance converter.” Analog Integrated Circuits and Signal Processing, vol. 47, no. 2, pp. 199–202, 2006. [6] E. Yuce, “On the implementation of the floating simulators employing a single active device.” Accepted for Publication in International Journal of Electronics and Communications (AEU ), 2006. [7] E. Yuce, “Floating inductance, FDNR and capacitance simulation circuit employing only grounded passive elements.” International Journal of Electronics, vol. 93, no. 10, pp. 679-688, 2006. [8] K. Pal, “New inductance and capacitor floatation schemes using current conveyors.” Electronics Letters, vol. 17, pp. 807–808, 1981. [9] M.T. Abuelma’atti and N.A. Tasadduq, “Electronically tunable capacitance multiplier and frequency-dependent negative resistance simulator using the current-controlled current conveyor.” Microelectronics Journal, vol. 30, pp. 869–873, 1999. IV. CONCLUSION Phase Impedance ( ) A novel circuit which can simulate floating inductance, floating capacitance, floating admittance and floating FDNR employing CCIIs and DVCC has been proposed. The presented circuit requires no critical component matching constraints, and employs only grounded passive components so it is easy to fabricate the proposed circuit in a fully integrated circuit technology. Under non-ideal considerations, the presented circuit is still lossless synthetic inductor or capacitor. The simulation results agree well with the theoretical calculations. [10] R. Senani, “Floating ideal FDNR using only two current conveyors.” Electronics Letters, vol. 20, no. 5, pp. 205–206, 1984. [11] M. Higashimura and Y. Fukui, “New lossless tunable floating FDNR simulation using two current conveyors and an INIC.” Electronics Letters, vol. 23, no. 10, pp. 629–630, 1987. Phase Impedance ( ) (a) Capacitance simulator (case a) [12] M. Higashimura and Y. Fukui, “Novel lossless tunable floating FDNR simulation using two current conveyors and a buffer.” Electronics Letters, vol. 22, no. 18, pp. 938–939, 1986. [13] S. Nandi, P.B. Jana, and R. Nandi, “Floating ideal FDNR using current conveyors.” Electronics Letters, vol. 19, no. 7, pp. 251–252, 1983. [14] S. Nandi, P.B. Jana, and R. Nandi, “Novel floating ideal tunable FDNR simulation using current conveyors.” IEEE Transactions on Circuits and Systems, vol. CAS-31, no. 4, pp. 402–403, 1984. [15] H. Sedef and C. Acar, “A new floating FDNR circuit using differential voltage current conveyors.” International Journal of Electronics and Communications (AEU), vol. 54, no. 5, pp. 297–301, 2000. Phase Impedance ( ) (b) Capacitance simulator (case b) [16] D. R. Frey “Log-domain filtering: an approach to current-mode filtering,” IEE Proc. Circuit Devices Syst., vol. 140, no. 406-416, 1993. Vin Ceq VO R % 1k : Figure 6. A bandpass filter example Phase Impedance ( ) (c) Inductance simulator (case c) Leq 0 -10 -20 Ideal Simulated (d) Inductance simulator (case d) -3010k Figure 5. Phases and impedances of the proposed circuit when the second port is grounded 30k 100k 300k Frequency (Hz) 1.0M 3.0M Figure 7. Both of the ideal and simulated responses of the filter in Fig. 6. ECTI-CON 2007 The 2007 ECTI International Conference ___________________________________________________________ 92