Download Rectangular Wave Delta Modulation Buck Regulator for Voltage Regulator Modules

Rectangular Wave Delta Modulation
Buck Regulator for Voltage Regulator Modules
J. Ngarmnil and K. Sooksood
Department of Electronic Engineering, Faculty of Engineering,
Mahanakorn University of Technology, Bangkok, 10530, Thailand
Email: [email protected], [email protected]
Abstract-This paper describes design of rectangular wave
delta modulation (RWDM) buck regulator for voltage regulator
modules (VRM). This regulator does not require clock generator
as PWM regulators do. It has simple and compact circuit; it
consumes less chip area. Hence, it is suitable for VRM application.
The proposed regulator was simulated by HSpice simulation
program using AMIS 0.5 µm CMOS parameters to verify the
concept. It shows very fast transient response and 70.55%
maximum efficiency. Moreover, the proposed buck regulator can
easily be integrated onto a monolithic chip.
I.
INTRODUCTION
Buck regulators have seen increasing popularity in their
utilization in the voltage regulator modules (VRM) for modern
microprocessor system. To decrease power consumption and
increase the speed, the microprocessors will operate at
significantly low voltage and high current. A VRM is used to
deliver highly accurate supply voltage regulation and high
output current to the microprocessors.
Conventional buck regulators in VRM use pulse width
modulation (PWM) signal to control on and off duration of
switches in order to supply the input voltage to load. The
switching is done at constant frequency and on time of the
switch is adjusted to control the average output voltage. There
are many control techniques both in analog and digital can be
used to make PWM signal to control buck regulators [1-2].
However, to obtain high performance and efficiency of the
regulators, a larger chip area and complexity are required to
facilitate the required high performance control circuitries such
as amplifier, saw-tooth generator, oscillator, A/D converter and
an embedded controller in fully digital control. Function of the
wave generator circuit is always critical under modern low
voltage environment and having power supply variations from
battery operation. Then a robust wave generator, which always
comes with a high cost, will be needed. As a result, a high
performance PWM-based regulator becomes expensive for a
practical implementation.
RWDM principle is also another attractive technique that
can be used in high performance DC-DC converters because
the RWDM output signal is pulse like PWM but fewer devices
are required in the control circuitries. RWDM principle is
firstly applied to switching power converter system in an
inverter [3]. It shows an excellent low order harmonic
attenuation. Recently, the RWDM control approach has been
applied and successfully implemented onto a class-D audio
amplifier [4-5] of which 92% maximum power efficiency has
been achieved. In scenario of efficiency, ease of control,
simple and compact structure, the RWDM is seen as another
promising technique to be implemented in the control loop of a
buck converter. This paper presents a new RWDM-based buck
regulator scheme having four advantages. First, the triangular
wave generator or oscillator is not required. Second, the
integrator of the RWDM loop is reduced since the actual
output voltage, which is essentially proportional to the
switching rectangular wave, can be used instead. Third, the
switching frequency is variable. Then, the power loss is low at
low load current [6]. Finally, it provides faster transient
response than V2 control method [7]. The proposed
architecture is verified through HSpice simulation program.
II. RWDM PRINCIPLE
The RWDM principle is shown in Fig. 1 [8]. Conceptually,
RWDM is similar to PWM except that the input signal VR(t) is
compared with the feedback signal Ve(t), which is essentially
the integrated signal of RWDM by integrator. Then, Ve(t) can
track the amplitudes of VR(t) within the V hysteresis boundary.
From Fig. 1, the frequency of RWDM signal can be given by
f %
#
$
1
V
V
%1 & !
! "
'
"
(
(
T !T
) m " x (t ) m ! x (t ) *
!
where m+ and m denote the slopes of the rising and falling
e(t ) Hysteresis
VR (t )
Vm (t )
Element
!
Input
signal
Ve (t )
RWDM
signal
Integrator
Upper boundary
level
Ve (t )
"V
2
!
"V
2
VR (t )
Lower boundary
level
B
A
T
C
T!
Vm (t ) RWDM
signal
This work has been supported by a grant from Shell Centennial Education
Fund.
(1)
Figure 1. RWDM principle
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curve of the feedback signal Ve(t), respectively. x'(t) is the
average slope of the input signal VR(t) and V is the tracking
boundary corresponding to the magnitude of the hysteresis
loop which is controlled directly by the trip voltage of the
comparator. m+ and m are also controlled by the time constant
of the integrator in the feedback path. Derived in Eq. (1), the
frequency of RWDM output signal is variable frequency. The
frequency is a function of hysteresis boundary and slopes of
both input and feedback signal.
Based on the principle, RWDM controller is simple for
implementation. RWDM-based converters can then be
integrated with less area consumption than conventional PWM
converters. Considering Eq. (1), it can notice that the slope of
the input signal x'(t) of the RWDM loop is normally small in
the application of switching regulator as compared to m+ and
m . Then, the variation of the switching frequency is not too
broad and can be a predictable parameter.
The RWDM-based buck regulator is illustrated in Fig. 2. It is
noted that the preliminary integrator in the RWDM loop is
cancelled out of the circuit, while the integration of RWDM
signal is taken from the output voltage of error amplifier node.
However, this is double integral signal because a buck
regulator is always second order system.
initial condition of vout(0) = Vout and iL(0) = ILmin. The ton is the
time that vout(t) = Vout. Calculating Eq. (2) yields ton = 0.343 µs.
B. Off-Time Interval
The off-time interval (toff) is taken during MP is opened and
MN is closed. This is a second-order system with zero forced
response. Thus, the differential equation of the output voltage
is
d2
d vout vout
vout !
!
%0.
dt RL C LC
dt 2
Similar to the ton, the toff can be determined by solving Eq. (3)
under the initial condition of vout(0) = Vout and iL(0) = ILmax. The
toff is the time that vout(t) = Vout. Calculating Eq. (3) yields toff =
2.4 µs.
C. Switching Frequency
From the above analysis, it can be observed that the time
intervals are a function of L, C, load resistance, input voltage
and output voltage level. Then, the switching frequency is
varied as a function of these values and directly obtained from
f %
III. BUCK REGULATOR ANALYSIS AND DESIGN
The steady state analysis and design of RWDM-based buck
regulator is discussed in this section. Fig. 3 demonstrates the
ideal waveforms of output voltage and inductor current used
for calculation. The proposed buck regulator is designed to
meet a following specification for VRM: Vin = 12 V, Vout =
1.5 V ±1%, and Iout = 20 A. The inductor L is 0.9 µH, output
capacitor C is 3300 µF and load resistor is 75 m!.
1
% 364.564 kHz .
ton ! toff
SR %
Vout
% 87463.56 V/s
ton
(2)
Vout max
Vout
The ton can be straightforward analyzed by solving second
order differential equation of the output voltage under the
Vout min
t
toff
ton
I out
T
(a)
L
MN
(5)
vout
d2
d vout vout Vin
.
v !
!
%
2 out
dt
dt RL C LC LC
Vin
(4)
D. RWDM Signal Slopes
Referring to Eq. (1), the frequency of the RWDM signal
depends on signals’ slope. The input signal of the RWDM is
the regulated output voltage and the feedback signal is the PIcontroller output voltage. The rising and falling slope of the
regulated output voltage can be approximated as follow:
A. On-Time Interval
During MP is closed and MN is opened (ton). It is obviously
seen that, this is a second order system with DC forced
response. The differential equation of the output voltage is
MP
(3)
iL
C
Vout
LOAD
I L max
IL
vgp
R1
+
Gate
Drive
I L min
R2
C1
vgn
RWDM
+
Figure 2. RWDM buck regulator
t
toff
ton
O.A.
Vref
T
(b)
Figure 3. Ideal waveforms, (a) output voltage and (b) inductor current
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VDD
M5
M9
M8
Vin !
M1
M7
M 21
M16
Vin
M2
M11
CC
M12
Vout
MC
I bias
M18
M 6 M14
M4
M3
M17
M13
M19
M15
M 22
M 20
M10
VSS
Figure 4. CMOS operational amplifier
SF %
Vout
% 12500 V/s
toff
(6)
where SR and SF are the slopes of rising and falling curve,
respectively. "Vout is a desired output ripple. The feedback
signal slopes (m+ for rising and m for falling curve) are
obtained by multiplying slopes of the regulated output voltage
with error amplifier gain. Error amplifier is designed using PIcontroller with the gain of 50 and the integrating time of 1 ns.
Thus, m+ = 4373177.843 V/s and m = 625000 V/s.
E. Hysteresis Boundary
The average slope of the regulated output voltage is much
VDD
M 25
M 27 M 28
M 26
M 29
M 30
vin !
vin
M 24
M 23
M 31
vout
M 32
I Bias
VSS
Figure 5. CMOS hysteresis comparator
VDD
M 40
M 39
M 33
M 34
M 41
M 35
M 37
M 47
M 43
M 45
vp
M 49
M 46
M 50
vgp
smaller than feedback signal slopes. Then, the x'(t) in Eq. (1)
can be neglected as
The proposed buck regulator has been verified through
HSpice using AMIS 0.5 µm CMOS parameters. The PMOS
switch (MP) with W/L = 600 mm/1 µm and the NMOS switch
(MN) with W/L = 200 mm/1 µm were employed. They showed
0.01 # on resistance. The parameter of a 0.9 µH MVR series
Coilcraft inductor was used. It had 1.72 m# of dc resistance.
The output capacitor was 3300 µF with 3 m# ESR. The
CMOS opamp with class-AB output buffer was used as
illustrated in Fig. 4. The simple CMOS hysteresis comparator
in Fig. 5 was also utilized. The gate driver was design using
CMOS inverter chains [9] with 100 ns dead time, demonstrated
in Fig. 6. The control circuitries were biased with regulator
input voltage and Ibias = 50 µA. The transistors aspect ratios
and component values are listed in Table 1. The simulation
results of the output voltage are shown in Fig. 7 and 8. The
output voltage has maximum ripple of 11.8 mV and switching
frequency of 407.554 kHz at 20-A output current.
2.5
2
M 55
M 56
M 61
M 59
M 63
vn
vgn
RWDM
M 57
M 64
M 60
1.5
1
0.5
M 58
M 52
Cd
M 62
Voltages [V]
M 38
M 53
(7)
M 42
VSS
VDD
M 51
.
IV. SIMULATION RESULTS
M 36
Cd
V + m! ! m" ,
Substituting known value (f, m+, and m ) into the Eq. (7), the
hysteresis boundary of the RWDM loop can then be obtained
as "V = 1.5 V.
M 48
M 44
m! m"
f %
0
M 54
0
100u
200u
Time [sec]
VSS
Figure 6. CMOS gate driver with dead time
Figure 7. Simulated output voltage
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127
300u
Fig. 9 exhibits the regulated output voltage and current when
output current is stepped from 10-A to 20-A. It can be seen that
the RWDM buck regulator provides very fast transient
response (approximately 1.5 µs). In addition, the switching
frequency only depends on output current, but the output
voltage level and ripple are not affected.
Finally, the power efficiency as a function of output current
at Vin = 12 V and Vout = 1.5 V is illustrated in Fig. 10. It shows
maximum power efficiency of 70.55% at 10-A output current.
The power efficiency of the designed RWDM buck regulator is
not too high, because the employed CMOS process is improper
for high power operation. To improve power efficiency, the
external discrete power MOSFET should be used as switches.
1.52
Voltages [V]
1.51
1.5
1.49
1.48
220u
Time [sec]
200u
240u
1.51
1.49
The analysis and design of RWDM-based buck regulator for
VRM is presented in this paper. It has simple circuit and can be
easily integrated onto monolithic chip. Furthermore, the
proposed regulator provides very fast transient response, which
suitable for VRM applications. The HSpice simulation results
are included to confirm the theory. They agree well with the
theoretical calculations. They show 1.5 µs transient response
and 70.55% maximum power efficiency.
REFERENCES
[1] R. W. Erickson, and D. Maksimovi$, Fundamentals of Power Electronics,
2nd ed., Massachusetts: Kluwer Academic Publishers, 2001, ch. 1.
[2] S. Maniktala, Switching Power Supply Design & Optimization, New
York: McGraw-Hill, 2004, ch. 3.
[3] P. D. Ziogas, “The delta modulation technique in static PWM inverters,”
IEEE Trans. Ind. Appl., vol. 17, no. 2, pp. 199-204, 1981.
[4] K. Nandhasri, J. Ngarmnil, and K. Moolpho, “A 2.8V RWDM class-D
power amplifier using an FGMOS comparator,” Proc. IEEE ISCAS 2002,
vol.5, pp. 261-264, 2002.
[5] S. C. Li, V. C. Lin, K. Nandhasri, and J. Ngarmnil, “New high efficiency
2.5V/0.45W RWDM class-D audio amplifier for portable consumer
electronics,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 9, pp.
1767-1774, 2005.
[6] B. Arbetter, R. Erickson, and D. Maksimovi$, “DC-DC converter design
for battery-operated systems,” Proc. IEEE PESC 95, vol. 1, pp.103-109,
1995.
[7] D. Goder and W. R. Pelletier, “V2 architecture provides ultra-fast
transient response in switch mode power supplies,” Proc. HFPC 96,
pp.19-23, 1996.
[8] R. Steele, Delta Modulation Systems, London: Pentech Press, 1975, ch. 6.
[9] A. J. Stratakos, S. R. Sanders, and R. W. Broderson, “A low-voltage
CMOS DC-DC converter for a portable battery-operated system,” Proc.
IEEE PESC 94, vol. 1, pp. 619-626, 1994.
1.47
TABLE I
TRANSISTORS ASPECT RATIOS AND COMPONENT VALUES
20
Currents [A]
Voltages [V]
Figure 8. Simulated output ripple
V. CONCLUSION
15
10
360u
400u
Time [sec]
440u
Figure 9. Regulated output voltage when output current is stepped
75
Efficiency [%]
70
65
60
55
5
10
15
20
25
I out [A]
Figure 10. Power efficiency versus output current
30
Components
M1-M2
M3-M4
M5, M8, M9, M10, M11
M6
M7
Mc
M12, M13, M16, M17
M14, M15, M18, M19
M20
M21
M22
M23-M24
M25-M26, M29-M30
M27-M28
M31-M32
M33, M35, M37, M43, M45, M51, M53, M59
M34, M36, M38, M44, M46, M52, M54, M60
M39-M40, M55-M56
M41-M42, M57-M58
M47, M49, M61, M63
M48, M50, M62, M64
Cc
Cd
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Dimension
20 µm/2 µm
38 µm/2 µm
6.9 µm/1 µm
152 µm/2 µm
28 µm/2 µm
1.5 µm/2 µm
22 µm/2 µm
22 µm/1 µm
40 µm/1 µm
600 µm/0.5 µm
400 µm/0.5 µm
25.5 µm/1 µm
28.5 µm/2 µm
29 µm/1 µm
6 µm/1 µm
5 µm/2 µm
10 µm/2 µm
10 µm/1 µm
20 µm/1 µm
100 µm/1 µm
50 µm/1 µm
0.15 pF
100 pF