Download MAX98356 PDM Input Class D Audio Power Amplifier General Description Features

EVALUATION KIT AVAILABLE
MAX98356
PDM Input Class D Audio Power Amplifier
General Description
The MAX98356 is a digital pulse-density modulated
(PDM) input Class D power amplifier that provides Class
AB audio performance with Class D efficiency. This IC
offers five selectable gain settings (3dB, 6dB, 9dB, 12dB,
and 15dB) set by a single gain-select input (GAIN).
The MAX98356 takes a stereo pulse density modulated
(SPDM) input signal directly into the DAC. Data on the
rising edge of PDM_CLK is considered left-channel data
while data on the falling PDM_CLK edge is right channel.
The IC can be configured to produce a left channel, right
channel, or left/2 + right/2 output from the stereo input
data. The IC also features an extremely robust digital
audio interface with very high wideband jitter tolerance
(12ns typ) on PDM_CLK.
Features
SSingle-Supply Operation (2.5V to 5.5V)
S3.2W Output Power into 4I at 5V
S1.8mA Quiescent Current
S92% Efficiency (RL = 8I, POUT = 900mW,
VDD = 3.7V)
S29µVRMS Output Noise (AV = 6dB)
SLow 0.013% THD+N at 1kHz
SExceptionally High Jitter Tolerance
SSupported PDM_CLK Rates of 1.84MHz–4.32MHz
and 5.28MHz–8.64MHz
Active emissions-limiting, edge-rate limiting, and overshoot control circuitry greatly reduce EMI. A filterless
spread-spectrum modulation scheme eliminates the need
for output filtering found in traditional Class D devices and
reduces the component count of the solution.
SSupports Left, Right, or Left/2 + Right/2 Outputs
The IC is available in a 9-pin WLP package (1.345mm x
1.435mm x 0.64mm) and is specified over the -40NC to
+85NC temperature range.
SLow RF Susceptibility Rejects TDMA
Noise from GSM Radios
Applications
Cellular Phones
Tablets
SSophisticated Edge Rate Control Enables
Filterless Class D Outputs
S77dB PSRR at 217Hz
SExtensive Click-and-Pop Reduction Circuitry
SRobust Short-Circuit and Thermal Protection
SAvailable in Space-Saving Package:
1.345mm x 1.435mm WLP (0.4mm Pitch)
Portable Media Players
Notebook Computers
Simplified Block Diagram
Ultrasonic Devices
Ordering Information and Functional Diagram appears at
end of data sheet.
PDM
INPUT
SHUTDOWN
AND
CHANNEL
SELECT
MAX98356
GAIN
CONTROL
DIGITAL
AUDIO
INTERFACE
DAC
CLASS D
OUTPUT
STAGE
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX98356.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6311; Rev 1; 7/13
MAX98356
PDM Input Class D Audio Power Amplifier
ABSOLUTE MAXIMUM RATINGS
VDD, PDM_CLK and PDM_DATA to GND...............-0.3V to +6V
All Other Pins to GND............................... -0.3V to (VDD + 0.3V)
Continuous Current In/Out of VDD/GND/OUT_.................. Q1.6A
Continuous Input Current (all other pins)......................... Q20mA
Duration of OUT_ Short Circuit to GND or VDD…......Continuous
Duration of OUTP Short to OUTN..............................Continuous
Continuous Power Dissipation (TA = +70NC)
WLP (derate 13.7mW/NC above +70NC)....................1096mW
Junction Temperature......................................................+150NC
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -65NC to +150NC
Soldering Temperature (reflow).......................................+230NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (qJA)...........73°C/W
Junction-to-Case Thermal Resistance (qJC)................50°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Supply Voltage Range
VDD
Undervoltage Lockout
UVLO
CONDITIONS
Guaranteed by PSSR test
MIN
TYP
2.5
1.4
1.8
MAX
UNITS
5.5
V
2.3
V
TA = +25NC
2.2
2.7
TA = +25NC, VDD = 3.7V
1.8
2.2
SD_MODE = 0V, TA = +25NC
0.6
2
FA
ISTNDBY
SD_MODE = 1.8V, no PDM_CLK, TA =
+25NC
300
400
FA
Turn-On Time
tON
Time from receipt of first clock cycle to
full operation
0.6
0.7
ms
Output Offset Voltage
VOS
TA = +25NC, gain = 15dB
Q0.3
Q1.5
mV
KCP
Peak voltage, TA = Into shutdown
+25NC, A-weighted,
32 samples per
Out of shutdown
second (Note 3)
Quiescent Current
IDD
Shutdown Current
ISHDN
Standby Current
Click-and-Pop Level
Power-Supply Rejection Ratio
Maxim Integrated
PSRR
VDD = 2.5V to 5.5V, TA = +25NC
f = 217Hz,
200mVP-P ripple
TA = +25NC
(Notes 3, 4)
f = 10kHz,
200mVP-P ripple
mA
-66
dBV
-72
60
75
77
dB
60
2
MAX98356
PDM Input Class D Audio Power Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
THD+N 10%,
gain = 12dB
Output Power (Note 3)
POUT
THD+N = 1%,
gain = 12dB
Total Harmonic Distortion +
Noise
THD+N
MIN
TYP
ZSPK = 4I + 33FH
3.2
ZSPK = 8I + 68FH
1.8
ZSPK = 8I + 68FH,
VDD = 3.7V
0.93
ZSPK = 4I + 33FH
2.5
ZSPK = 8I + 68FH
1.4
ZSPK = 8I + 68FH,
VDD = 3.7V
0.77
f = 1kHz, POUT = 1W, TA = +25NC,
ZSPK = 4I + 33FH
0.02
f = 1kHz, POUT = 0.5W, TA = +25NC,
ZSPK = 8I + 68FH
0.013
MAX
UNITS
W
0.06
%
Dynamic Range
DR
A-weighted, PDM_CLK = 6.144MHz,
VRMS = 2.54V
99
dB
Output Noise
VN
A-weighted (Note 4)
29
FVRMS
Gain (Relative to a 2.1dBV
Reference Level)
Current Limit
Efficiency
AV
GAIN = GND through 100kI
14.4
15
15.6
GAIN = GND
11.4
12
12.6
GAIN = unconnected
8.4
9
9.6
GAIN = VDD
5.4
6
6.6
GAIN = VDD through 100kI
2.4
3
3.6
ILIM
h
ZSPK = 8I + 68FH, THD+N = 10%,
f = 1kHz, gain = 12dB
DAC Gain Error
Frequency Response
dB
2.8
A
92
%
1
%
Q0.05
dB
DIGITAL AUDIO INTERFACE
PDM_CLK High Frequency
Range
fCLKH
5.28
8.64
MHz
PDM_CLK Low Frequency
Range
fCLKL
1.84
4.32
MHz
PDM_CLK High Time
tPDM_CLKH
40
ns
PDM_CLK Low Time
tPDM_CLKL
40
ns
Maximum Low Frequency
PDM_CLK Jitter
RMS jitter below 40kHz
0.5
Maximum High Frequency
PDM_CLK Jitter
RMS jitter above 40kHz
12
Maxim Integrated
ns
3
MAX98356
PDM Input Class D Audio Power Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
Input High Voltage
SYMBOL
Digital audio inputs
VIL
Digital audio inputs
Input Low Voltage
Input Leakage Current
Input Capacitance
CONDITIONS
VIH
IIH, IIL
VIN = 0V, VDD = 5.5V, TA = +25NC
MIN
MAX
0.6
V
+1
FA
3
Maximum
75
Minimum
25
PDM_DATA to PDM_CLK
Setup Time
tSETUP
10
PDM_DATA to PDM_CLK
Hold Time
tHOLD
10
UNITS
V
-1
CIN
PDM Ones Density
TYP
1.3
pF
%
ns
SD_MODE COMPARATOR TRIP POINTS
B0
See SD_MODE and shutdown operation
for details
B1
B2
SD_MODE Pulldown Resistor
RPD
0.08
0.16
0.355
0.65
0.77
0.825
1.245
1.4
1.5
92
100
108
V
kI
GAIN COMPARATOR TRIP POINTS
VGAIN
AV = 3dB gain
0.65 x
VDD
0.85 x
VDD
AV = 6dB gain
0.9 x
VDD
VDD
AV = 9dB gain
0.4 x
VDD
0.6 x
VDD
AV = 12dB gain
0
0.1 x
VDD
AV = 15dB gain
0.15 x
VDD
0.35 x
VDD
V
Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
RL = 8I, LL = 68FH. For RL = 4I, LL = 33FH.
Note 4: Digital silence used for input signal.
Maxim Integrated
4
MAX98356
PDM Input Class D Audio Power Amplifier
tPDM_CLK
tPDM_CLKH
tPDM_CLKL
PDM_CLK
tSETUP
LEFT
PDM_DATA
tHOLD
tSETUP
RIGHT
tHOLD
LEFT
RIGHT
Figure 1. PDM Audio Interface Timing Diagram
Typical Operating Characteristics
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
General
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
3.0
2.5
2.0
1.5
1.0
0.6
0.5
0.4
0.3
0.2
0.1
0.5
0
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
Maxim Integrated
0.7
MAX98356 toc02
3.5
SHUTDOWN CURRENT (µA)
MAX98356 toc01
4.0
5.0
5.5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
5
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
Speaker Amplifier
-40
f = 6kHz
-50
f = 1kHz
-60
-70
-40
-50
-90
-40
MAX98356 toc05
f = 6kHz
-50
-60
-70
0.01
0.1
f = 1kHz
-100
0.001
10
1
f = 100Hz
0.01
0.1
1
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
f = 6kHz
-50
-60
-70
f = 1kHz
-80
-90
0.1
OUTPUT POWER (W)
Maxim Integrated
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
-30
-40
f = 6kHz
-50
-60
-70
-80
1
10
-100
0.001
0.01
0
0.1
OUTPUT POWER (W)
-10
-20
1
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
-30
-40
f = 6kHz
-50
-60
-70
-80
f = 1kHz
f = 100Hz
-90
f = 100Hz
0.01
-20
THD+N RATIO (dB)
-30
-40
0
-10
10
MAX98356 toc08
OUTPUT POWER (W)
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
-100
0.001
-30
-90
f = 100Hz
THD+N RATIO (dB)
-20
-20
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
-80
-100
0.001
10
1
0
-10
MAX98356 toc07
0
-10
0.1
f = 1kHz
-70
-90
0.01
f = 6kHz
-60
-80
f = 100Hz
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
-30
-80
-100
0.001
THD+N RATIO (dB)
-20
THD+N RATIO (dB)
-30
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
THD+N RATIO (dB)
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
MAX98356 toc06
THD+N RATIO (dB)
-20
0
MAX98356 toc03
0
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98356 toc04
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
f = 100Hz
-90
10
-100
0.001
0.01
0.1
f = 1kHz
1
10
OUTPUT POWER (W)
6
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
-40
-50
-60
POUT = 75mW
-80
-40
-50
-60
POUT = 100mW
1k
10k
100
1k
10k
100k
10
100
MAX98356 toc11
1k
10k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
0
-20
POUT = 150mW
-80
-30
-40
-50
-60
POUT = 250mW
-70
-80
POUT = 600mW
-100
1k
FREQUENCY (Hz)
Maxim Integrated
10k
100k
-20
100k
-30
-40
-50
-60
POUT = 350mW
-70
POUT = 1.5W
-90
-100
100
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
-80
POUT = 850mW
-90
0
-10
THD+N RATIO (dB)
-60
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
-10
THD+N RATIO (dB)
-50
10
POUT = 850mW
FREQUENCY (Hz)
-40
-90
POUT = 150mW
-70
FREQUENCY (Hz)
-30
-70
-60
-100
10
MAX98356 toc13
-20
-50
FREQUENCY (Hz)
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
-10
100k
MAX98356 toc12
0
100
-40
-90
-100
10
-30
-80
POUT = 500mW
-90
-100
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
-20
-80
POUT = 350mW
-90
THD+N RATIO (dB)
-30
-70
0
-10
MAX98356 toc14
-70
-20
THD+N RATIO (dB)
THD+N RATIO (dB)
-30
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
THD+N RATIO (dB)
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
-20
0
MAX98356 toc09
0
-10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98356 toc10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
-100
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
7
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
0.5
2.0
1.5
THD+N = 10%
1.0
0
THD+N = 1%
10
100
10
1
1.0
THD+N = 1%
0
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
Maxim Integrated
100
5.0
5.5
MAX98356 toc17
THD+N = 1%
10
1
NORMALIZED GAIN vs. FREQUENCY
3.0
THD+N = 10%
2.5
0.5
MAX98356 toc19
GAIN = 12dB
ZSPK = 4I + 33µH
3.5
2.0
1.5
THD+N = 1%
1.0
100
LOAD (I)
ZSPK = 8I + 68µH
0.4
0.3
NORMALIZED GAIN (dB)
THD+N = 10%
4.0
OUTPUT POWER PER CHANNEL (W)
2.0
2.5
THD+N = 10%
1.5
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX98356 toc18
GAIN = 12dB
ZSPK = 8I + 68µH
0.5
2.0
LOAD (I)
OUTPUT POWER vs. SUPPLY VOLTAGE
1.5
2.5
0
LOAD (I)
2.5
3.0
0.5
0
1
OUTPUT POWER (W)
3.5
1.0
0.5
THD+N = 1%
VDD = 5V
GAIN = 12dB
ZSPK = RLOADI + 68µH
4.0
MAX98356 toc20
THD+N = 10%
1.0
OUTPUT POWER vs. LOAD RESISTANCE
4.5
OUTPUT POWER (W)
1.5
VDD = 4.2V
GAIN = 12dB
ZSPK = RLOADI + 68µH
2.5
OUTPUT POWER (W)
OUTPUT POWER (W)
MAX98356 toc15
VDD = 3.7V
GAIN = 12dB
ZSPK = RLOADI + 68µH
2.0
OUTPUT POWER vs. LOAD RESISTANCE
3.0
MAX98356 toc16
OUTPUT POWER vs. LOAD RESISTANCE
2.5
0.2
0.1
0
-0.1
-0.2
-0.3
0.5
-0.4
0
-0.5
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
10
100
1k
10k
100k
FREQUENCY (Hz)
8
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
80
60
50
40
30
70
80
60
50
40
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
20
10
0
200
400
600
800
EFFICIENCY vs. OUTPUT POWER
80
40
70
60
50
40
30
30
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
10
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
OUTPUT POWER PER CHANNEL (mW)
Maxim Integrated
90
80
EFFICIENCY (%)
50
100
MAX98356 toc25
90
EFFICIENCY (%)
60
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY vs. OUTPUT POWER
70
20
0
1000 1200 1400
100
MAX98356 toc24
80
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
10
OUTPUT POWER PER CHANNEL (mW)
EFFICIENCY vs. OUTPUT POWER
90
40
0
0
OUTPUT POWER PER CHANNEL (mW)
100
50
20
0
0 100 200 300 400 500 600 700 800 900 1000
60
MAX98356 toc26
10
70
30
30
20
EFFICIENCY (%)
90
EFFICIENCY (%)
70
90
EFFICIENCY (%)
EFFICIENCY (%)
80
100
MAX98356 toc22
MAX98356 toc21
90
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY vs. OUTPUT POWER
100
MAX98356 toc23
EFFICIENCY vs. OUTPUT POWER
100
70
60
50
40
30
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
20
10
0
0
500
1000
1500
2000
OUTPUT POWER PER CHANNEL (mW)
2500
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
20
10
0
0
500
1000 1500 2000 2500 3000 3500
OUTPUT POWER PER CHANNEL (mW)
9
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
80
60
60
40
-20
50
40
30
30
20
10
0
3.0
3.5
4.0
4.5
5.0
10
5.5
100
1k
INBAND OUTPUT SPECTRUM
0
-60
-80
-20
-40
-60
-80
-60
-80
-120
-120
-140
10 12 14 16 18 20
FREQUENCY (kHz)
Maxim Integrated
PDM_CLK = 5.6448MHz
ZSPK = 8I + 68µH
-40
-140
8
10 12 14 16 18 20
-20
-120
6
8
0
-100
4
6
INBAND OUTPUT SPECTRUM
-100
2
4
20
-100
0
2
FREQUENCY (kHz)
AMPLITUDE (dBV)
-40
PDM_CLK = 5.6448MHz
ZSPK = 8I + 68µH
0
AMPLITUDE (dBV)
AMPLITUDE (dBV)
-20
-140
100k
INBAND OUTPUT SPECTRUM
20
MAX98356 toc30
PDM_CLK = 6.144MHz
ZSPK = 8I + 68µH
0
-80
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
20
10k
MAX98356 toc31
2.5
-60
-120
10
0
-40
-100
20
f = 1kHz
ZSPK = 8I + 68µH
PDM_CLK = 6.144MHz
ZSPK = 8I + 68µH
0
MAX98356 toc32
70
PSRR (dB)
70
50
VDD = 5V
ZSPK = 8I + 68µH
90
AMPLITUDE (dBV)
80
INBAND OUTPUT SPECTRUM
20
MAX98356 toc28
90
PSRR (dB)
100
MAX98356 toc27
100
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY
MAX98356 toc29
POWER-SUPPLY REJECTION
RATIO vs. SUPPLY VOLTAGE
-140
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
10
MAX98356
PDM Input Class D Audio Power Amplifier
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). PDM_CLK = 3.072MHz, speaker loads (ZSPK) connected between OUTP and OUTN,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
-80
-60
-80
-40
-60
-80
-100
-100
-100
-120
-120
-120
-140
-140
2
4
6
8
10 12 14 16 18 20
-140
0
2
4
6
FREQUENCY (kHz)
-60
-80
-20
-40
-60
-80
-60
-80
-120
-140
-140
8
10 12 14 16 18 20
Maxim Integrated
PDM_CLK = 2.048MHz
ZSPK = 8I + 68µH
-40
-120
FREQUENCY (kHz)
10 12 14 16 18 20
-20
-140
6
8
0
-120
4
6
INBAND OUTPUT SPECTRUM
-100
2
4
20
-100
0
2
FREQUENCY (kHz)
AMPLITUDE (dBV)
-40
PDM_CLK = 2.048MHz
ZSPK = 8I + 68µH
0
AMPLITUDE (dBV)
-20
0
INBAND OUTPUT SPECTRUM
20
MAX98356 toc36
PDM_CLK = 2.8224MHz
ZSPK = 8I + 68µH
0
10 12 14 16 18 20
FREQUENCY (kHz)
INBAND OUTPUT SPECTRUM
20
8
MAX98356 toc37
0
AMPLITUDE (dBV)
-20
MAX98356 toc38
-60
-40
PDM_CLK = 2.8224MHz
ZSPK = 8I + 68µH
0
MAX98356 toc35
-20
INBAND OUTPUT SPECTRUM
20
AMPLITUDE (dBV)
-40
PDM_CLK = 3.072MHz
ZSPK = 8I + 68µH
0
AMPLITUDE (dBV)
AMPLITUDE (dBV)
-20
MAX98356 toc33
PDM_CLK = 3.072MHz
ZSPK = 8I + 68µH
0
INBAND OUTPUT SPECTRUM
20
MAX98356 toc34
INBAND OUTPUT SPECTRUM
20
-100
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
11
MAX98356
PDM Input Class D Audio Power Amplifier
Pin Configuration
TOP VIEW
BUMP SIDE DOWN
MAX98356
+
SD_MODE
VDD
OUTP
A1
A2
A3
PDM_DATA
GAIN
OUTN
B1
B2
B3
PDM_CLK
GND
GND
C1
C2
C3
WLP
Pin Description
PIN
NAME
A1
SD_MODE
A2
VDD
A3
B1
OUTP
FUNCTION
Shutdown and Channel Select. Determines left, right, or left/2 + right/2 mix and also used for shutdown.
See Table 5.
Power-Supply Input
Positive Speaker Amplifier Output
PDM_DATA PDM Digital Input Signal
Amplifier Gain
B2
GAIN
B3
OUTN
C1
PDM_CLK
C2, C3
GND
Maxim Integrated
Gain Connections
Gain (dB)
GND through 100kI resistor
15
GND
12
Unconnected
9
VDD
6
VDD through 100kI resistor
3
Negative Speaker Amplifier Output
PDM Bit Clock Input Signal. Supports frequency ranges: 1.84MHz–4.32MHz and 5.28 MHz–8.64MHz.
Ground
12
MAX98356
PDM Input Class D Audio Power Amplifier
Detailed Description
The output stage features low-quiescent current, comprehensive click-and-pop suppression, and excellent RF
immunity. The IC offers Class AB audio performance with
Class D efficiency in a minimal board-space solution.
The Class D amplifier features spread-spectrum modulation with edge-rate and overshoot control circuitry that
offers significant improvements in switch-mode amplifier
radiated emissions. The amplifier features click-and-pop
suppression that reduces audible transients on startup
and shutdown. The amplifier includes thermal-overload
and short-circuit protection.
The MAX98356 is a digital PDM input Class D power
amplifier. The PDM modulation scheme uses the relative
density of digital pulses to represent the amplitude of an
analog signal. The IC accepts stereo PDM data through
PDM_DATA and PDM_CLK.
SD_MODE selects which audio channel is output by the
amplifier and is used to put the IC into shutdown. The
GAIN pin offers five gain settings and allows the output of
the amplifier to be tuned to the appropriate level.
Digital Audio Interface
Table 1. PDM_CLK Polarity
PDM_CLK EDGE
DIRECTION
CHANNEL
Rising edge
Left
Falling edge
Right
The IC takes a stereo PDM input signal directly into the
DAC. Data read on the rising edge of PDM_CLK is leftchannel data while data read on the falling PDM_CLK
edge is right channel (Table 1).
Supported PDM_CLK Rates
Table 2 indicates the range of PDM_CLK rates that are
supported by the IC. Table 3 indicates the specific clock
rates to use based on the baseband rate and the oversample rate of the incoming PDM signal.
Table 2. PDM_CLK Rates
SUPPORTED CLOCK RATES (MHz)
PDM_CLK Jitter Tolerance
The IC features a very high PDM_CLK jitter tolerance of
0.5ns for RMS jitter below 40kHz and 12ns for wideband
RMS jitter while maintaining a dynamic range greater than
98dB (Table 4).
1.84–4.32
5.28–8.64
Table 3. Calculated PDM_CLK Rates
BASEBAND SAMPLE
RATE (kHz)
INPUT CLOCK RATES (MHz)
32x OVERSAMPLED
PDM
64x OVERSAMPLED
PDM
128x OVERSAMPLED
PDM
256x OVERSAMPLED
PDM
8
—
—
—
2.048
16
—
—
2.048
4.096
32
—
2.048
4.096
—
44.1
—
2.8224
5.6448*
—
48
—
3.072
6.144*
—
88.2
2.8224
5.6448*
—
—
96
3.072
6.144*
—
—
*The mono left/2 + right/2 feature is not supported at PDM_CLK rates of 5.28MHz and above.
Table 4. RMS Jitter Tolerance
Maxim Integrated
FREQUENCY
RMS JITTER TOLERANCE (ns)
< 40kHz
0.5
40kHz–BCLK
12
13
MAX98356
PDM Input Class D Audio Power Amplifier
the shutdown mode provides the lowest power consumption and the best power-on/off click-and-pop performance.
PDM Timing Characteristics
Figure 2 shows the PDM operation of the IC. The bitdepth is one bit and each bit alternates between leftchannel and right-channel data.
SD_MODE Pin and Shutdown Operation
The IC features a low-power shutdown mode, drawing
less than 0.6FA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the IC into shutdown.
If the PDM generator produces data that is stuck at logichigh or logic-low, then the output of the IC is railed, forcing DC at the load. Therefore, it is recommended that the
PDM generator includes protection to detect this invalid
condition. If such a condition is detected, then the IC
should either be put into shutdown or PDM_CLK should
be stopped.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left channel of the
stereo input data. Drive SD_MODE high through a sufficiently small resistor to select the right channel of
the stereo input data. Drive SD_MODE high through a
sufficiently large resistor to select both the left and right
channels of the stereo input data (left/2 + right/2). The left/2
+ right/2 mode is not supported for PDM_CLK rates above
5.28MHz. RLARGE and RSMALL are determined by the
Standby Mode
If PDM_CLK stops toggling, the IC automatically enters
standby mode. In standby mode, the Class D speaker
amplifier is turned off and the outputs go into a highimpedance state, ensuring that the unwanted current is not
transferred to the load during this condition. Standby mode
should not be used in place of the shutdown mode because
SD_MODE = LOGIC-HIGH
PDM_CLK
PDM_DATA
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
RIGHT CHANNEL IGNORED
SD_MODE = PULLUP THROUGH RSMALL
PDM_CLK
PDM_DATA
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
LEFT CHANNEL IGNORED
SD_MODE = PULLUP THROUGH RLARGE
PDM_CLK
PDM_DATA
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
R
L
LEFT AND RIGHT CHANNELS AVERAGED
Figure 2. PDM Digital Audio Interface Timing
Table 5. SD_MODE Control
SD_MODE STATUS
SELECTED CHANNEL
High
VSD_MODE > B2 trip point (1.4V typ)
Left
Pullup through RSMALL
B2 trip point (1.4V typ) > VSD_MODE >
B1 trip point (0.77V typ)
Right
Pullup through RLARGE
B1 trip point (0.77V typ) > VSD_MODE >
B0 trip point (0.16V typ)
Left/2 + right/2
Low
B0 trip point (0.16V typ) > VSD_MODE
Shutdown
Maxim Integrated
14
MAX98356
PDM Input Class D Audio Power Amplifier
VDDIO voltage (logic voltage from control interface) that is
driving SD_MODE according to the following two equations:
IC continues to disable and re-enable the outputs until
the fault condition is removed.
RSMALL (kI) = 98.5 x VDDIO - 100
RLARGE (kI) = 222.2 x VDDIO - 100
Gain Selection
The IC offers five programmable gain selections through
a singel gain input (GAIN). Gain is referenced to the
full-scale output of the DAC, which is 2.1dBV (Table 7).
Assuming that the desired output swing is not limited by
the supply voltage rail, the IC’s output level can be calculated based on the PDM input ones’s density and selected amplifier gain according to the following equation:
Figure 3 and Figure 4 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a pullup/down driver.
When the device is configured in left channel mode
(SD_MODE is directly driven to logic-high by the control interface) care must be taken to avoid violating
the Absolute Maximum Ratings limits for SD_MODE.
Ensuring that VDD is always greater than VDDIO is one
way to prevent SD_MODE from violating the Absolute
Maximum Ratings limits. If this is not possible in the
application (e.g., if VDD < 3.0V and VDDIO = 3.3V), then
it is necessary to add a small resistance (~2kI) in series
with SD_MODE to limit the current into the SD_MODE
pin. This is not a concern when using the right channel or
(left + right)/2 modes.
Class D Speaker Amplifier
The filterless Class D amplifier offers much higher efficiency
than Class AB amplifiers. The high efficiency of a Class
D amplifier is due to the switching operation of the output
stage transistors. Any power loss associated with the
Class D output stage is mostly due to the I2R loss of the
MOSFET on-resistance and quiescent current overhead.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromagnetic-interference (EMI) regulation standards. Maxim’s
active emissions-limiting edge-rate control circuitry and
spread-spectrum modulation reduces EMI emissions
while maintaining up to 92% efficiency.
Maxim’s spread-spectrum modulation mode flattens
wideband spectral components while proprietary techniques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction or
efficiency. The ICs’ spread-spectrum modulator randomly varies the switching frequency by Q10kHz around the
center frequency (300kHz). Above 10MHz, the wideband
spectrum looks like noise for EMI purposes (Figure 5).
Speaker Current Limit
If the output current of the speaker amplifier exceeds the
current limit (2.8A typ), the IC disables the outputs for
approximately 100Fs. At the end of the 100Fs, the outputs are re-enabled. If the fault condition still exists, the
Maxim Integrated
Output signal level (dBV) = 20 x log[abs(PDM one’s
density(%) - 50) /25] (dBFS) + 2.1dB + selected
speaker amplifier gain (dB)
where the one’s density of the PDM input ranges from
75% (maximum positive magnitude) to 25% (maximum
negative magnitude). 0dFBS is referenced to 0dBV.
Click-and-Pop Suppression
The IC speaker amplifier features Maxim’s comprehensive
click-and-pop suppression. During startup, the clickand-pop suppression circuitry reduces audible transient
sources internal to the device. To achieve optimal clickand-pop reduction at startup, it is recommended that idle
data be sent to the digital audio interface for the first 0.5ms
of turn-on time. When entering shutdown, the differential
speaker outputs immediately go to a high-impedance
state without creating an audible click-and-pop noise.
Table 6. Examples of SD_MODE Pullup
Resistor Values
LOGIC VOLTAGE
RLARGE
RSMALL
LEVEL (VDDIO) (V) (kI, 1% tolerance) (kI, 1% tolerance)
1.8
76.8
300
3.3
226
634
Table 7. Gain Selection
GAIN
GAIN (dB)
Connect to GND through
100kI Q5% resistor
15
Connect to GND
12
Unconnected
9
Connect to VDD
Connect to VDD through
100kI Q5% resistor
6
3
15
MAX98356
PDM Input Class D Audio Power Amplifier
PROCESSOR
VDDIO
LEFT MODE
MAX98356
R
VSD_MODE
GPIO
B2 (1.4V typ)
RIGHT MODE
100kI
±8%
B1 (0.77V typ)
LEFT/2 + RIGHT/2 MODE
B0 (0.16V typ)
Figure 3. SD_MODE Resistor Connection Using Open-Drain Driver
PROCESSOR
VDDIO
GPIO
LEFT MODE
MAX98356
R
VSD_MODE
B2 (1.4V typ)
RIGHT MODE
100kI
±8%
B1 (0.77V typ)
LEFT/2 + RIGHT/2 MODE
B0 (0.16V typ)
Figure 4. SD_MODE Resistor Connection Using Pullup/Down Driver
90
EMISSION LEVEL (dBµV/m)
70
50
30
10
-10
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 5. EMI with 12in of Speaker Cable and No Output Filtering
Maxim Integrated
16
MAX98356
PDM Input Class D Audio Power Amplifier
Applications Information
2.5V TO 5.5V
2.5V TO 5.5V
10µF
0.1µF
SD_MODE
GAIN
B2
CODEC
GPIO*
A1
PDM CLOCK
PDM DATA OUT
PDM_CLK
PDM_DATA
C1
A2
GPIO*
OUTP
SD_MODE
GAIN
B2
A1
VDD
A2
A3
MAX98356
PDM CLOCK
B3
B1
0.1µF
CODEC
VDD
A3
10µF
PDM_CLK
C1
OUTN
PDM DATA OUT
C2, C3
PDM_DATA
MAX98356
B3
B1
GND
OUTP
OUTN
C2, C3
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
Figure 6. Left-Channel Operation with 6dB Gain
Figure 7. Left-Channel Operation with 12dB Gain
2.5V TO 5.5V
10µF
CODEC
RSMALL
(76.8kI)**
GPIO*
PDM CLOCK
PDM DATA OUT
0.1µF
VDD
GAIN
SD_MODE
PDM_CLK
PDM_DATA
A1
C1
B2
A2
A3
MAX98356
B3
B1
OUTP
OUTN
C2, C3
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
Figure 8. Right-Channel Operation with 6dB Gain
Maxim Integrated
17
MAX98356
PDM Input Class D Audio Power Amplifier
2.5V TO 5.5V
10µF
0.1µF
VDD
GAIN
SD_MODE
A1
B2
A2
A3
PDM_CLK
PDM_DATA
OUTP
MAX98356
C1
B3
B1
OUTN
C2, C3
GND
CODEC
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
GPIO*
2.5V TO 5.5V
PDM CLOCK
10µF
PDM DATA OUT
RSMALL
(76.8kI)**
0.1µF
VDD
GAIN
SD_MODE
A1
B2
A2
A3
PDM_CLK
PDM_DATA
C1
MAX98356
B3
B1
OUTP
OUTN
C2, C3
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
Figure 9. Stereo Operation Using Two ICs
Maxim Integrated
18
MAX98356
PDM Input Class D Audio Power Amplifier
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency
and THD+N performance. The IC’s filterless modulation
scheme does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to
recover the audio component of the square-wave output.
Because the switching frequency of the IC is well beyond
the bandwidth of most speakers, voice coil movement
due to the switching frequency is very small. Use a
speaker with a series inductance > 10FH. Typical 8I
speakers exhibit series inductances in the 20FH to
100FH range.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing
results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. Figure 11 shows
the dimensions of the WLP balls used on the IC.
2.5V TO 5.5V
10µF
CODEC
GPIO*
Power-Supply Input
VDD, which ranges from 2.5V to 5.5V, powers the IC,
including the speaker amplifier. Bypass VDD with a 0.1FF
and 10FF capacitor to GND. Some applications might
require only the 10FF bypass capacitor, making it possible to operate with a single external component. Apply
additional bulk capacitance at the IC if long input traces
between VDD and the power source are used.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio performance and prevents switching noise from coupling into
the audio signal.
PDM CLOCK
PDM DATA OUT
RLARGE
(300kI)**
SD_MODE
0.1µF
A1
VDD
GAIN
B2
A2
A3
PDM_CLK
PDM_DATA
C1
OUTP
MAX98356
B3
B1
OUTN
C2, C3
GND
*LEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH.
**300kI ASSUMES VGPIO = 1.8V.
THE MAX98356 IS SHUTDOWN WHEN GPIO IS LOW.
Figure 10. Left/2 + Right/2 Operation with 6dB Gain
0.24mm
Use wide, low-resistance output traces. As load impedance decreases, the current drawn from the device
outputs increases. At higher current, the resistance of
the output traces decreases the power delivered to the
load. For example, if 2W is delivered from the speaker
output to a 4I load through 100mI of total speaker
trace, 1.904W is being delivered to the speaker. If power
is delivered through 10mI of total speaker trace, 1.951W
is being delivered to the speaker. Wide output, supply,
and ground traces also improve the power dissipation of
the IC.
The IC is inherently designed for excellent RF immunity.
For best performance, add ground fills around all signal
traces on top or bottom PCB planes.
Maxim Integrated
0.21mm
Figure 11. MAX98356 WLP Ball Dimensions
19
MAX98356
PDM Input Class D Audio Power Amplifier
Functional Diagram
2.5V TO 5.5V
10µF
0.1µF
VDD
A2
GAIN
B2
MAX98356
PDM_CLK C1
PDM_DATA B1
SD_MODE A1
DIGITAL
AUDIO
INTERFACE
DAC
CLASS D
OUTPUT
STAGE
A3 OUTP
B3 OUTN
C2, C3
GND
Ordering Information
PART
MAX98356EWL+
TEMP RANGE
PIN-PACKAGE
-40NC to +85NC
9 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Maxim Integrated
20
MAX98356
PDM Input Class D Audio Power Amplifier
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
9 WLP
W91F1+1
21-0459
Refer to Application Note 1891
E
PIN 1
INDICATOR
MARKING
1
COMMON DIMENSIONS
A3
A
A1
AAAA
D
A2
A
0.05 S
S
See Note 7
SIDE VIEW
TOP VIEW
E1
A
0.64
0.05
A1
0.19
0.03
A2
A3
0.45 REF
0.025 BASIC
b
0.27
0.03
D1
0.80
BASIC
E1
0.80
BASIC
e
0.40 BASIC
SD
0.00 BASIC
SE
0.00 BASIC
SE
e
B
C
SD
B
D1
A
1
2
3
A
b
0.05 M
S
DEPOPULATED
BUMPS
E
D
W91B1+7
1.260 0.040
1.260 0.040
NONE
W91C1+1
1.595 0.035
1.415 0.035
NONE
PKG. CODE
W91F1+1
1.435 0.015
1.345 0.015
NONE
W91G1+1
1.465 0.015
1.455 0.015
NONE
W91J1+1
1.238 0.015
1.238 0.015
NONE
AB
BOTTOM VIEW
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
- DRAWING NOT TO SCALE -
Maxim Integrated
maxim
integrated
TITLE
APPROVAL
TM
PACKAGE OUTLINE
9 BUMPS, WLP PKG. 0.4mm PITCH
DOCUMENT CONTROL NO.
21-0459
REV.
G
1
1
21
MAX98356
PDM Input Class D Audio Power Amplifier
Revision History
REVISION
NUMBER
REVISION
DATE
0
5/12
Initial release
1
7/13
New lower tolerances in the Electrical Characteristics table and throughout; updates
to the Typical Operating Characteristics global conditions
DESCRIPTION
PAGES
CHANGED
—
1–11
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013
Maxim Integrated Products, Inc.
22
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.