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Transcript
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
超低功耗、轨至轨输出、负电源轨输入、VFB 运算放大器
查询样品: OPA836, OPA2836
特性
1
•
•
•
•
•
•
•
•
超低功耗
– 源电压: 2.5V 至 5.5V
– 静态电流: 1mA
– 断电模式: 0.5μA
带宽: 290MHz
转换速率: 560 V/µs
上升时间: 3ns (2VSTEP)
稳定时间: 22ns (2VSTEP)
过驱动恢复时间: 60ns
SNR: 0.00013% (–117.6dBc), 在 1 kHz
(1VRMS) 时
THD: 0.00003% (–130dBc), 在 1kHz (1VRMS)
时
HD2/HD3: –85dBc / -105dBc,在 1 MHz (2Vpp)
时
•
•
•
•
•
•
•
输入电压噪声: 4.6nV/rtHz (f=100 kHz)
输入失调电压: 65μV (400μV 最大值)
CMRR: 116dB
输出驱动电流: 50mA
RRO——轨至轨输出
输入电压范围: -0.2V 至 3.9V (5V 电源)
工作温度范围: -40℃ 至 +125℃
应用
•
•
•
•
•
•
低功耗信号调节
音频 ADC 输入缓冲器
低功耗 SAR 及 ΔΣ ADC 驱动器
便携式系统
低功耗系统
高密度系统
说明
对于将功耗作为关键性的重要指标的电池供电型便携式应用而言,OPA836 和 OPA2836 的低功耗及高频性能为设
计人员提供了采用其他器件所无法获得的性能/功耗比。 再加上可将电流减小至 <1μA 的节能模式,这些器件为电
池供电型应用中的高频放大器提供了一款极具吸引力的解决方案。
OPA836 和 OPA2836 提供了下列封装选项:
•
OPA836 单通道器件: SOT23-6 (DBV),和具有集成型增益电阻器的 10 引脚 RUN。
•
OPA2836 双通道器件: SOIC-8 (D)、MSOP-10 (DGS) 和 10 引脚 RUN。
OPA836 RUN 封装选项包括断电 (<1μA) 和集成型增益设定电阻器,以在印刷电路板上占用尽可能小的面积
(≈2mm x 2mm)。 通过在 PCB 上增设电路走线,可以实现 +1、-1、+2、-3、+4、-4、+5、-7、+8 和若
干其他非整数值的增益以及衰减。 片上电阻器的阻值被精确地修整至 1% 绝对值容差以内,因而可使用外部电阻器
以实现更大的灵活性。
该器件针对 -40℃ 至 125℃ 扩展工业温度范围内的运作进行了特性分析。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.BDTIC.com/TI
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated
English Data Sheet: SLOS712A
PRODUCT PREVIEW
•
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
PACKAGE –
LEAD
CHANNEL
COUNT
PACKAGE
DESIGNATOR
SPECIFIED TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
OPA836
1
SOT23-6
DBV
–40°C to 125°C
QTL
OPA836IDBVT
Tape and Reel, 250
OPA836
1
SOT23-6
DBV
–40°C to 125°C
QTL
OPA836IDBVR
Tape and Reel, 3000
OPA836
1
RUN-10
RUN
–40°C to 125°C
TBD
OPA836IRUNT
Tape and Reel, 250
OPA836
1
RUN-10
RUN
–40°C to 125°C
TBD
OPA836IRUNR
Tape and Reel, 2500
OPA2836
2
SOIC-8
D
–40°C to 125°C
TBD
OPA2836IDT
Tape and Reel, 250
OPA2836
2
SOIC-8
D
–40°C to 125°C
TBD
OPA2836IDR
Tape and Reel, 2500
OPA2836
2
MSOP-10
D
–40°C to 125°C
TBD
OPA2836IDGST
Tape and Reel, 250
OPA2836
2
MSOP-10
D
–40°C to 125°C
TBD
OPA2836IDGSR
Tape and Reel, 2500
OPA2836
2
RUN-10
RUN
–40°C to 125°C
TBD
OPA2836IRUNT
Tape and Reel, 250
OPA2836
2
RUN-10
RUN
–40°C to 125°C
TBD
OPA2836IRUNR
Tape and Reel, 2500
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
UNITS
VS– to VS+
Supply voltage
5.5
VI
Input voltage
±VS
VID
Differential input voltage
1V
Ii
Continuous input current
20 mA
IO
Continuous output current
100 mA
TJ
Maximum junction temperature
TA
Operating free-air temperature range
–40°C to 125°C
Storage temperature range
–65°C to 150°C
Continuous power dissipation
Tstg
See Thermal Characteristics Specification
150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD
ratings
300°C
HBM
TBD
CDM
TBD
MM
TBD
THERMAL INFORMATION
THERMAL METRIC
(1)
OPA825
OPA835
OPA2835
OPA2835
OPA2835
SOT23-6
(DBV)
RUN-10
SOIC-8
(D)
MSOP-10
(DGS)
RUN-10
(DGS)
6 PINS
10 PINS
8 PINS
10 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
129.2
θJB
Junction-to-board thermal resistance
39.4
ψJT
Junction-to-top characterization parameter
25.6
ψJB
Junction-to-board characterization parameter
38.9
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
2
UNITS
194
°C/W
有关传统和新的热度量的更多信息,请参阅 IC 封装热度量 应用报告 SPRA953。
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :OPA836, OPA2836
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
SPECIFICATIONS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
MHz
C
Small-signal bandwidth
VOUT = 50 mVPP, G = 1
254
VOUT = 100 mVPP, G = 1
200
VOUT = 100 mVPP, G = 2
100
VOUT = 100 mVPP, G = 5
26
VOUT = 100 mVPP, G = 10
11
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
110
MHz
C
Large-signal bandwidth
VOUT = 1 VPP, G = 2
60
MHz
C
Bandwidth for 0.1dB flatness
VOUT = 1 VPP, G=2
25
MHz
C
260/240
V/µs
C
ns
C
Slew rate, Rise/Fall
Rise/Fall time
4/4.5
Settling time to 1%, Rise/Fall
Settling time to 0.1%, Rise/Fall
VOUT = 1VSTEP, G = 2
Settling time to 0.01%, Rise/Fall
Overshoot/Undershoot
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
2nd Order Intermodulation Distortion
ns
C
ns
C
50/45
ns
C
5/3
%
C
dBc
C
f = 10 kHz, VIN_CM = mid-supply – 0.5V
-133
f = 100 kHz, VIN_CM = mid-supply – 0.5V
-120
f = 1 MHz, VIN_CM = mid-supply – 0.5V
-84
f = 10 kHz, VIN_CM = mid-supply – 0.5V
-137
f = 100 kHz, VIN_CM = mid-supply – 0.5V
-130
f = 1 MHz, VIN_CM = mid-supply – 0.5V
-105
3rd Order Intermodulation Distortion
f = 1 MHz, 200 kHz Tone Spacing, VOUT
Envelope = 1VPP, VIN_CM = mid-supply –
0.5V
Input voltage noise
f = 100 KHz
Voltage Noise 1/f corner frequency
Input current noise
15/15
30/25
f = 1 MHz
Current Noise 1/f corner frequency
C
C
C
dBc
C
-90
dBc
C
-90
dBc
C
C
C
4.6
nV/√Hz
300
Hz
0.75
pA/√Hz
TBD
Hz
C
Overdrive recovery time, Over/Under
Overdrive = 0.5 V
55/60
ns
C
Closed-loop output impedance
f = 100 kHz
0.02
Ω
C
Channel to channel crosstalk (OPA2836)
f = 10 kHz
TBD
dB
C
(1)
PRODUCT PREVIEW
AC PERFORMANCE
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :OPA836, OPA2836
3
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
SPECIFICATIONS: VS+ = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
100
125
MAX
UNITS
TEST
LEVEL (1)
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
±65
TA = 25°C
Input referred offset voltage
Input offset voltage drift (2)
TA = 0°C to 70°C
±680
TA = –40°C to 85°C
±760
TA = –40°C to 125°C
±1060
TA = 0°C to 70°C
±1
TA = –40°C to 85°C
±1
±6
±1.1
±6.6
650
1000
TA = –40°C to 125°C
Input bias current
PRODUCT PREVIEW
Input bias current drift
Input offset current
Input offset current drift (2)
±400
A
µV
B
±6.2
TA = 25°C
300
TA = 0°C to 70°C
190
1400
TA = –40°C to 85°C
120
1500
TA = –40°C to 125°C
120
1800
TA = 0°C to 70°C
±0.33
±2
TA = –40°C to 85°C
±0.32
±1.9
TA = –40°C to 125°C
±0.37
±2.1
TA = 25°C
±30
±180
TA = 0°C to 70°C
±30
±200
TA = –40°C to 85°C
±30
±215
TA = –40°C to 125°C
±30
±240
TA = 0°C to 70°C
±77
±460
TA = –40°C to 85°C
±95
±575
TA = –40°C to 125°C
±100
±600
TA = 25°C
VS– – 0.2
TA = –40°C to 125°C
VS– – 0.2
µV/°C
B
A
nA
nA/°C
B
B
A
nA
B
pA/°C
B
VS-
V
A
VS-
V
B
A
INPUT
Common-mode input range low
Common-mode input range high
TA = 25°C
VS+ – 1.2
VS+ – 1.1
V
TA = –40°C to 125°C
VS+ – 1.2
VS+ – 1.1
V
B
94
114
dB
A
100||1.2
kΩ || pF
C
200||1
kΩ || pF
C
Common-mode rejection ratio
Input impedance common mode
Input impedance differential mode
OUTPUT
Linear output voltage low
Linear output voltage high
Output saturation voltage, High / Low
Linear output current drive
TA = 25°C, G = 5
VS- + 0.15
VS- + 0.2
V
A
TA = –40°C to 125°C, G = 5
VS- + 0.15
VS- + 0.2
V
B
V
A
TA = 25°C, G = 5
VS+ – 0.25
VS+ – 0.2
TA = –40°C to 125°C, G = 5
VS+ – 0.25
VS+ – 0.2
TA = 25°C, G = 5
V
B
80/40
mV
C
mA
A
TA = 25°C
±40
±45
TA = –40°C to 125°C
±40
±45
B
POWER SUPPLY
Specified operating voltage
2.5
Quiescent operating current
TA = 25°C
0.8
TA = –40°C to 125°C
0.6
Power supply rejection (±PSRR)
(1)
(2)
4
95
0.95
108
5.5
V
B
1.15
mA
A
1.4
mA
B
dB
A
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :OPA836, OPA2836
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
SPECIFICATIONS: VS+ = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VOUT = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted
PARAMETER
CONDITIONS
MIN
UNITS
TEST
LEVEL (1)
VS– + 1.4 VS– + 2.1
V
A
VS– + 1.4
V
A
TYP
MAX
POWER DOWN
Enable voltage threshold
Specified "on" above VS- + 2.1 V
Disable voltage threshold
Specified "off" below VS- + 0.7 V
Powerdown pin bias current
PD = VS-+ 0.7V
20
500
nA
A
Powerdown quiescent current
PD = VS-+ 0.7V
0.5
1.5
µA
A
Turn-on time delay
Time from PD = high to VOUT = 90%
of final value
200
ns
C
Turn-off time delay
Time from PD = low to VOUT = 10% of
original value
25
ns
C
PRODUCT PREVIEW
VS– + 0.7
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :OPA836, OPA2836
5
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VOUT = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
MHz
C
AC PERFORMANCE
Small-signal bandwidth
VOUT = 50 mVPP, G = 1
290
VOUT = 100 mVPP, G = 1
205
VOUT = 100 mVPP, G = 2
100
VOUT = 100 mVPP, G = 5
28
VOUT = 100 mVPP, G = 10
11.8
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
118
MHz
C
Large-signal bandwidth
VOUT = 2 VPP, G = 2
87
MHz
C
Bandwidth for 0.1dB flatness
VOUT = 2 VPP, G = 2
29
MHz
C
560/580
V/µs
C
Slew rate, Rise/Fall
Rise/Fall time
3/3
ns
C
22/22
ns
C
30/30
ns
C
Settling time to 0.01%, Rise/Fall
40/45
ns
C
Overshoot/Undershoot
7.5/5
%
C
dBc
C
Settling time to 1%, Rise/Fall
Settling time to 0.1%, Rise/Fall
PRODUCT PREVIEW
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
2nd Order Intermodulation Distortion
3rd Order Intermodulation Distortion
VOUT = 2V Step, G = 2
f = 10 kHz
–133
f = 100 kHz
–120
f = 1 MHz
–85
f = 10 kHz
–140
f = 100 kHz
–130
f = 1 MHz
–105
f = 1 MHz, 200 kHz Tone Spacing,
VOUT Envelope = 2VPP
Signal to Noise Ratio, SNR
f = 1kHz, VOUT = 1 VRMS, 22kHz
bandwidth
Total Harmonic Distortion, THD
f = 1kHz, VOUT = 1 VRMS
Input voltage noise
f = 100 KHz
Voltage Noise 1/f corner frequency
f > 1 MHz
Input current noise
Current Noise 1/f corner frequency
C
C
C
dBc
C
–79
dBc
C
–91
dBc
C
0.00013
-117.6
0.00003
C
%
C
dBc
C
%
C
-130
dBc
C
C
4.6
nV/√Hz
300
Hz
0.75
pA/√Hz
TBD
Hz
C
Overdrive recovery time, Over/Under
Overdrive = 0.5 V
55/60
ns
C
Closed-loop output impedance
f = 100 kHz
0.02
Ω
C
Channel to channel crosstalk (OPA2836)
f = 10 kHz
TBD
dB
C
(1)
6
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :OPA836, OPA2836
OPA836, OPA2836
ZHCS019A – MARCH 2011 – REVISED MARCH 2011
www.ti.com.cn
SPECIFICATIONS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VOUT = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
100
122
MAX
UNITS
TEST
LEVEL (1)
DC PERFORMANCE
±65
TA = 25°C
Input referred offset voltage
TA = 0°C to 70°C
±685
TA = –40°C to 85°C
±765
TA = –40°C to 125°C
±1080
TA = 0°C to 70°C
Input offset voltage drift (2)
TA = –40°C to 85°C
TA = –40°C to 125°C
Input bias current
Input bias current drift
Input offset current
±1.05
±6.3
±1
±6.1
±1.1
±6.8
650
1000
TA = 25°C
300
TA = 0°C to 70°C
190
1400
TA = –40°C to 85°C
120
1550
TA = –40°C to 125°C
120
1850
TA = 0°C to 70°C
±0.34
±2
TA = –40°C to 85°C
±0.34
±2
TA = –40°C to 125°C
±0.38
±2.3
TA = 25°C
±30
±180
TA = 0°C to 70°C
±30
±200
TA = –40°C to 85°C
±30
±215
TA = –40°C to 125°C
±30
±250
±80
±480
TA = –40°C to 85°C
±100
±600
TA = –40°C to 125°C
±110
±660
TA = 25°C
VS– – 0.2
TA = –40°C to 125°C
VS– – 0.2
TA = 0°C to 70°C
Input offset current drift (2)
dB
±400
A
A
µV
µV/°C
B
B
A
nA
nA/°C
B
B
PRODUCT PREVIEW
Open-loop voltage gain (AOL)
A
nA
B
pA/°C
B
VS-
V
A
VS-
V
B
INPUT
Common-mode input range low
Common-mode input range high
TA = 25°C
VS+ – 1.2
VS+ – 1.1
V
A
TA = –40°C to 125°C
VS+ – 1.2
VS+ – 1.1
V
B
97
116
dB
A
200||1.2
kΩ || pF
C
200||1
kΩ || pF
C
Common-mode rejection ratio
Input impedance common mode
Input impedance differential mode
OUTPUT
Linear output voltage low
Linear output voltage high
Output saturation voltage, High / Low
Linear output current drive
TA = 25°C, G =
VS- + 0.15
VS- + 0.2
V
A
TA = –40°C to 125°C, G = 5
VS- + 0.15
VS-+ 0.2
V
B
V
A
TA = 25°C, G = 5
VS+ – 0.25
VS+ – 0.2
TA = –40°C to 125°C, G = 5
VS+ – 0.25
VS+ – 0.2
TA = 25°C, G = 5
V
B
100/50
mV
C
mA
TA = 25°C
±40
±50
TA = –40°C to 125°C
±40
±50
A
B
POWER SUPPLY
Specified operating voltage
2.5
TA = 25°C
Quiescent operating current
TA = –40°C to 125°C
0.9
0.65
Power supply rejection (±PSRR)
(1)
(2)
1.0
97
108
5.5
V
B
1.2
mA
A
1.5
mA
B
dB
A
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
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SPECIFICATIONS: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VOUT = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply. TA = 25°C. Unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
VS–+1.4
VS–+2.1
UNITS
TEST
LEVEL (1)
V
A
V
A
POWER DOWN
Enable voltage threshold
Specified "on" above 2.1 V
Disable voltage threshold
Specified "off" below 0.7 V
VS–+0.7
VS–+1.4
Powerdown pin bias current
20
500
nA
A
Powerdown quiescent current
0.5
1.5
µA
A
170
ns
C
35
ns
C
Turn-on time delay
Time from PD = high to VOUT = 90%
of final value
Turn-off time delay
Time from PD = low to VOUT = 10% of
original value
PRODUCT PREVIEW
8
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DEVICE INFORMATION
PIN CONFIGURATIONS
OPA836 (TOP VIEW)
OPA836 (TOP VIEW)
SOT23-6 (DBV)
RUN-10
VS+
VOUT
1
6
VS+
VS-
2
5
PD
VIN+
3
4
VIN-
+ -
VOUT
1
VIN-
2
VIN+
3
PD
4
10
9
FB1
8
FB2
7
FB3
6
FB4
1k
- +
750
250
5
OPA2836 (TOP VIEW)
OPA2836 (TOP VIEW)
SOIC-8 (D)
DGS-10
VOUT1
1
VIN1-
2
VIN1+
3
VS-
4
+
+
VOUT1
1
VOUT2
VIN1-
2
6
VIN2-
VIN1+
3
5
VIN2+
VS-
4
PD1
5
8
VS+
7
10
+
+
PRODUCT PREVIEW
VS-
VS+
9
VOUT2
8
VIN2-
7
VIN2+
6
PD2
OPA2836 (TOP VIEW)
RUN-10
VS+
VOUT1
1
VIN1-
9
VOUT2
2
8
VIN2-
VIN1+
3
7
VIN2+
PD1
4
6
PD2
10
+ -
- +
5
VS-
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PIN FUNCTIONS
PIN
NUMBER
DESCRIPTION
NAME
OPA836 DBV PACKAGE
1
VOUT
Amplifier output
2
VS–
Negative power supply input
3
VIN+
Amplifier non-inverting input
4
VIN–
Amplifier inverting input
5
PD
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
6
VS+
Positive power supply input
OPA836 RUN PACKAGE
1
VOUT
Amplifier output
2
VIN–
Amplifier inverting input
3
VIN+
Amplifier non-inverting input
4
PD
Amplifier Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
PRODUCT PREVIEW
5
VS–
Negative power supply input
6
FB4
Connection to bottom of 250 Ω internal gain setting resistors
7
FB3
Connection to junction of 750 and 250 Ω internal gain setting resistors
8
FB2
Connection to junction of 1k and 750 Ω internal gain setting resistors
9
FB1
Connection to top of 1kΩ internal gain setting resistors
10
VS+
Positive power supply input
OPA2836 D PACKAGE
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
VS–
5
VIN2+
Negative power supply input
Amplifier 2 non-inverting input
6
VIN2–
Amplifier 2 inverting input
7
VOUT2
Amplifier 2 output
8
VS+
Positive power supply input
OPA2836 DSG PACKAGE
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
VS–
Negative power supply input
5
PD1
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
6
PD2
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
7
VIN2+
Amplifier 2 non-inverting input
8
VIN2–
Amplifier 2 inverting input
9
VOUT2
Amplifier 2 output
10
VS+
Positive power supply input
OPA2836 RUN PACKAGE
10
1
VOUT1
Amplifier 1 output
2
VIN1–
Amplifier 1 inverting input
3
VIN1+
Amplifier 1 non-inverting input
4
PD1
Amplifier 1 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
5
VS–
Negative power supply input
6
PD2
Amplifier 2 Power Down, low = low power mode, high = normal operation (PIN MUST BE DRIVEN)
7
VIN2+
Amplifier 2 non-inverting input
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PIN FUNCTIONS (continued)
PIN
NUMBER
DESCRIPTION
NAME
8
VIN2–
Amplifier 2 inverting input
9
VOUT2
Amplifier 2 output
10
VS+
PRODUCT PREVIEW
Positive power supply input
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VO = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
SMALL SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE
21
21
VS = 2.7 V,
VO = 100 mVpp,
G = 10
18
RL = 1 kW
12
RL = 1 kW
15
G=5
Gain Magnitude - dB
Gain Magnitude - dB
15
VS = 2.7 V,
VO = 1 Vpp,
G = 10
18
9
6
G=2
3
G=5
12
9
6
G=2
3
G=1
0
0
G=1
-3
-3
G = -1
-6
-6
-9
0
-9
10
f - Frequency - MHz
100
1
10
f - Frequency - MHz
100
Figure 1.
Figure 2.
FREQUENCY RESPONSE WITH CAPACITIVE LOAD
SERIES OUTPUT RESISTOR
vs
CAPACITIVE LOAD
1000
100
VS = 2.7 V,
G = 1,
R F = 0W
VS = 2.7 V,
G = 1,
RF = 0 W
CL = 10 pF
RO = 49.9 W
RL = 1 kW,
CL = 22 pF
0
Gain Magnitude - dB
0
1000
RO = 40.2 W
CL = 56 pF
RO = 24.9 W
CL = 100 pF
-3
RO = 16.9 W
CL = 220 pF
RO = 10 W
CL = 560 pF
-6
RL = 1 kW
RO - Output Resistor - W
PRODUCT PREVIEW
3
1
G = -1
10
RO = 5 W
CL = 22 pF
RO = 0 W
-9
0
1
10
f - Frequency - MHz
100
1000
1
10
Figure 3.
12
100
CL - Capacitive Load - pF
1000
Figure 4.
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VO = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
SLEW RATE
vs
OUTPUT VOTAGE STEP
OUTPUT VOLTAGE SWING
vs
LOAD RESISTANCE
300
3
VS = 2.7 V,
G = 5,
2.5 RF = 1 kW
VO = High
Falling
VO - Output Voltage - V
Slew Rate - V/ms
VS = 2.7 V,
G = 2,
250 RF = 1 kW
RL = 1 kW
200
Rising
150
100
2
1.5
1
0.5
50
VO = Low
0.6
0.7
0.8
Voltage Step -V
0.9
0
10
1
Figure 5.
Figure 6.
OUTPUT SATURATION VOLTAGE
vs
LOAD CURRENT
OUTPUT IMPEDANCE
vs
FREQUENCY
10000
VS = 2.7 V,
G = 5,
RF = 1 kW
10000
VS = 2.7 V,
G=1
1000
ZO - Output Impedance - W
VSAT - Saturation Voltage - V
1000
RL - Load Resistance - W
1
0.1
100
PRODUCT PREVIEW
0
0.5
VO = High
VO = Low
0.01
100
10
1
0.1
0.001
0.1
1
10
IL - Load Currebt - mA
100
0.01
0.01
0.1
Figure 7.
1
10
100
f - Frequency - MHz
1000
10000
Figure 8.
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TYPICAL PERFORMANCE GRAPHS: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = +2.7V, VS– = 0V, VO = 1VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
3
2.5
VS = 2.7 V,
G = 1,
RF = 0 W
VS = 2.7 V,
G = 1,
RF = 1 kW
2.5
RL = 1 kW
VO - Output Voltage - V
VO - Output Voltage - V
2 RL = 1 kW
VO = 1.5 Vpp
1.5
VO = 2 Vpp
2
1.5
1
VO = 0.5 Vpp
0.5
VO = 0.5 Vpp
1
0.5
0
0
0
500
t - Time - ns
0
1000
500
t - Time - ns
Figure 9.
Figure 10.
POWER DOWN RESPONSE
3
3.75
VS = 2.7 V,
G = 2,
RF = 1 kW,
3.25
VP
0.5
2.25
1.75
0.25
1.25
0.75
0.25
0
-0.25
VPDO - Power Down Voltage - V
2.5
2.75
VO - Output Voltage - V
PRODUCT PREVIEW
OUTPUT OVERDRIVE RECOVERY
0.75
VI - Input Voltage - V
1000
RL = 1 kW
2
VO
1.5
1
0.5
-0.75
-0.25
0
500
1000
t - Time - ns
1500
-1.25
2000
0
0
Figure 11.
14
500
t - Time - ns
1000
Figure 12.
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VO = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
SMALL SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE
21
21
G = 10
18
18
RL = 1 kW
15
G=5
12
9
6
G=2
3
0
VS = 5 V,
VO = 2 Vpp,
G = 10
Gain Magnitude - dB
Gain Magnitude - dB
15
VS = 5 V,
VO = 100 mVpp,
RL = 1 kW
G=5
12
9
6
G=2
3
0
G=1
-3
-3
G=1
-6
-6
G = -1
G = -1
-9
0
10
f - Frequency - MHz
100
0
1
10
f - Frequency - MHz
100
1000
Figure 13.
Figure 14.
FREQUENCY RESPONSE WITH CAPACITIVE LOAD
SERIES OUTPUT RESISTOR
vs
CAPACITIVE LOAD
100
VS = 5 V,
G = 1,
RF = 0 W
VS = 5 V,
G = 1,
RF = 0 W
CL = 10 pF
RO = 49.9 W
RL = 1 kW
RL = 1 kW
CL = 22 pF
0
Gain Magnitude - dB
1000
RO = 0 W
CL = 56 pF
RO = 24.9 W
CL = 100 pF
-3
RO = 16.9 W
CL = 220 pF
RO = 10 W
-6
RO - Output Resistor - W
3
1
PRODUCT PREVIEW
-9
10
CL = 560 pF
RO = 5 W
CL = 22 pF
RO = 40.2 W
-9
0
1
10
f - Frequency - MHz
100
1000
1
10
Figure 15.
100
CL - Capacitive Load - pF
1000
Figure 16.
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VO = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
5
5
VS = 5 V,
4.5 G = 1,
RF = 1 kW
4 R = 1 kW
4.5
4
VO - Output Voltage - V
VO - Output Voltage - V
VO = 4 Vpp
L
VO = 4 Vpp
3.5
3
VS = 5 V,
G = 1,
RF = 0 W
2.5
RL = 1 kW
2
1.5
1
3.5
3
2.5
VO = 0.5 Vpp
2
1.5
1
0.5
0.5
VO = 0.5 Vpp
0
0
0
500
t - Time - ns
1000
0
1000
Figure 18.
OUTPUT OVERDRIVE RECOVERY
SLEW RATE
vs
OUTPUT VOLTAGE STEP
700
6.25
5.75
5.25
600
1
4.75
3.75
3.25
2.75
0.5
2.25
1.75
0.25
1.25
0.75
Falling
Rising
500
Slew Rate - V/ms
0.75
VS = 5 V,
G = 2,
RF = 1 kW
RL = 1 kW
4.25
VO - Output Voltage - V
PRODUCT PREVIEW
Figure 17.
1.25
VI - Input Voltage - V
500
t - Time - ns
400
300
200
0.25
0
-0.25
-0.25
0
500
1000
t - Time - ns
1500
-0.75
-1.25
2000
100
0
0
2
3
4
Voltage Step -V
Figure 19.
16
1
Figure 20.
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TYPICAL PERFORMANCE GRAPHS: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +5V, VS– = 0V, VO = 2VPP, RF = 0Ω, RL = 1kΩ, G = 1V/V, Input and Output
Referenced to mid-supply unless otherwise noted. TA = 25°C.
OUTPUT VOLTAGE SWING
vs
LOAD RESISTANCE
OUTPUT SATURATION VOLTAGE
vs
LOAD CURRENT
1
5
VS = 5 V,
G = 2,
RF = 1 kW
VS = 5 V,
G = 5,
RF = 1 kW
VO = High
VSAT - Saturation Voltage - V
VO - Output Voltage - V
4
3
2
VO = High
0.1
VO = Low
1
VO = Low
100
1000
0.01
0.1
10000
RL - Load Resistance - W
Figure 21.
10
IL - Load Currebt - mA
100
Figure 22.
OUTPUT IMPEDANCE
vs
FREQUENCY
POWER DOWN RESPONSE
5
10000
4.5
VS = 5 V,
G = 2,
RF = 1 kW
4
RL = 1 kW
VP
VS = 5 V,
G=1
VPDO - Power Down Voltage - V
1000
ZO - Output Impedance - W
1
PRODUCT PREVIEW
0
10
100
10
1
3.5
VO
3
2.5
2
1.5
1
0.1
0.5
0.01
0.01
0
0.1
1
10
100
1000
10000
0
f - Frequency - MHz
Figure 23.
500
t - Time - ns
1000
Figure 24.
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APPLICATION INFORMATION
Power down must be driven or tied high or low (maximum resistor value 100k) for proper operation and cannot
be left floating.
PRODUCT PREVIEW
18
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