Download Looking Beyond CMOS: Integrated Circuit Design with Nano Electro-Mechanical Switches

Looking Beyond CMOS:
Integrated Circuit Design with
Nano Electro-Mechanical Switches
Vladimir Stojanović (MIT)
in collaboration with
Tsu-Jae King Liu, Elad Alon (UC Berkeley)
Dejan Marković (UCLA)
MIEL 2010
Acknowledgements
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Circuit design
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Device design
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Fred Chen, Hossein Fariborzi
Matthew Spencer, Abhinav Gupta
Cheng Wang, Kevin Dwan
Hei Kam, Rhesa Nathanael, Vincent Pott, Jaeseok Jeon
Sponsors
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DARPA NEMS program
FCRP (C2S2, MSD)
MIT CICS
Berkeley Wireless Research Center
NSF
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CMOS is Scaling, Power Density is Not
Power Density Prediction circa 2000
Power Density (W/cm2)
10000
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100
Rocket Nozzle
Nuclear Reactor
Core 2
8086 Hot Plate
10 4004
P6
80088085 386
Pentium® proc
286
486
8080
1
1970
1980
1990
2000
2010
Year
S. Borkar, Intel
Since ~2000 supply voltage (Vdd) stuck at ~1V
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1000
Sun’s Surface
Leakage stops you from lowering threshold (Vth)
Vdd and Vt not scaling well  power/area not scaling
Performance limited by power, not number of transistors
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Parallelism to the Rescue
IBM CELL processor
Lower supply,
balanced Vth
Parallelize to recover performance
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Parallelism allows slower, more efficient units
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Helps scale performance for fixed power
Will this last forever?
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Subthreshold leakage: Game Over for CMOS
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Leakage and sub-threshold slope define minimum
energy/op for CMOS
Parallelism cannot reduce power if already operating at
minimum energy
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NEM Switches to the Rescue
Measured MEM Switch I-V Curve
MEM Switch Energy vs. VDD
Etotal=Edynamic
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NEM switches show zero leakage & sharp sub-threshold slope
Could potentially enable reduced E/op with scaling
R. Nathanael et al., “4-Terminal Relay Technology for Complementary Logic,” IEDM 2009
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NEM Switch Structure and Operation
Tungsten Channel
Tungsten Body
Poly-SiGe Gate
Poly-SiGe Anchor
Poly-SiGe Beam
/Flexure
Tungsten Source/Drain
OFF Switch:
|Vgb| < Vpo (pull-out voltage)
ON Switch:
|Vgb| > Vpi (pull-in voltage)
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NEM Switch as a Logic Element
Gate
Source
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4-terminal design mimics MOSFET operation
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Body
Drain
Electrostatic actuation is ambipolar
Non-inverting logic is possible
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Actuation independent of source/drain voltages
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NEM Switch Model
Anchor
Spring k
Mechanical
Model
Damper b
Mass m
G
Cgc
S
D
Rs
Cgb
Rcs
Rcd
Rd
Cdb
Csb
B
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Lumped Verilog-A model for circuit design and simulation:
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Mechanical dynamics: spring (k), damper (b), mass (m)
Electrical parasitics: non-linear gate-body (Cgb), gate-channel
(Cgc), and source/drain-body cap (Cs,db), contact (Rcs,d)
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NEM Switch Characteristics
tPI[s]
Model
1.E-06
Model
Experiment
L=50mm
40mm
14mm
10
15
1.E-07
0
5
VDD [V]
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Simple electro-mechanical model matches experiment well
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Mechanical “pull-in” delay scales with geometry and overdrive voltage
“Pull-in” voltage (threshold) scales with switch geometry
Constant E-field scaling
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Mechanical delay and VPI scale linearly
*H. Kam et al., “Design and Reliability of a Micro-Relay Technology…,” IEDM 2009
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Digital Circuit Design with NEMS
NEMS: 12 switches
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CMOS: delay set by electrical time constant
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Quadratic delay penalty for stacking devices
Buffer & distribute logical/electrical effort over many stages
NEMS: delay dominated by mechanical movement
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Can stack ~100-200 devices before td,elec ≈ td,mech
So, want all to switch simultaneously
 Implement logic as a single complex gate
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Need to Compare at Block Level
NEMS: 12 switches
4 gate delays
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Delay Comparison vs. CMOS
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1 mechanical delay
Single mechanical delay vs. several electrical gate delays
For reasonable load, NEMS delay unaffected by fan-out/fan-in
Area Comparison vs. CMOS
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Larger individual devices
But often need fewer devices to implement same function
F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008
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Example: NEMS Adder
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Full adder cell:
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12 NEMS vs. 24
transistors
XOR “free”
Complementary signals
avoid extra mechanical
delay (to invert)
NEMS all sized minimally
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N-bit NEMS Adder
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Ripple carry configuration
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Cascade full adder cells to
create larger complex gate
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Stack N NEMS, but still
single mechanical delay
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Performance gap to
CMOS shrinks to ~10x for
32-bit add
(10ns delay at 90nm)
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Scaled NEMS vs. CMOS Adders
Energy/op vs. Delay/op across Vdd
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9x
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Compare vs.
Sklansky CMOS
adder*
30x less capacitance
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10x
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2.4x lower Vdd
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Lower device Cg, Cd
Fewer devices
No leakage energy
For similar area: >9x lower E/op, >10x greater delay
F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008
*D. Patil et. al., “Robust Energy-Efficient Adder Topologies,” in Proc. 18th IEEE Symp.
on Computer Arithmetic (ARITH'07).
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Parallelism helps
Energy/op vs. Delay/op across Vdd & CL
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Can extend energy
benefit up to
GOP/s throughput
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As long as
parallelism is
available
Area overhead
bounded
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CMOS needs to be
parallelized at
some point too
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Contact Resistance
Energy/op vs. Delay/op across Vdd & CL
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Low contact R
not critical
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Good news for
reliability…
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NEMS Circuit Demonstration
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Test Devices
Logic
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Timing
Elements
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Latches, FFs
Memory
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Adders,
Compressors
SRAM, DRAM
I/O
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ADC, DAC
F. Chen et al., “Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for
VLSI Applications,” ISSCC 2010.
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Things We Learned…
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Layout Matters
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Unbalanced current flow:
flexures burn up!
Parasitic capacitors: can
affect Vpi (DIBL-like effect)
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Measured Inverter VTC
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VTC looks digital, suggests composability
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NEMS Latch Shows Composability
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Designed as if we used MOSFETS, but that is
not always optimal…
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Switch-based Carry Generation
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Demonstrates propagate-generate-kill logic as a
single complex gate
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Measured DRAM Results
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Simultaneous read and write
Read latency = tmech,on (decoder) + tmech,off (WLRD switch)
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Measured DAC Results
Code = “Vin” 1 1
Code = 0 0 “Vin”
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Resistive divider based DAC
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2-bit thermometer coded output
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NEM switch scaling – next design
1um litho
NEM switch size
120um x 150um
0.25um litho
Scaled NEMS size
20um x 20um
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Conclusions
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NEMS unique features enable scaling post-CMOS
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t
Reliability improving
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Nearly ideal Ion/Ioff
Switching delay largely independent of electrical
Need to adapt circuit design style
Circuit level insights critical (contact R)
Demonstrated simple circuits
Can start thinking about building more complex systems
Potentially order of magnitude lower E/op than CMOS
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Next steps: scaling and improved device design, testing larger
digital blocks
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