Download Designing VLSI Circuits and Systems with Nano Electro-Mechanical Relays

CMOS ET Workshop 2011
Designing VLSI Circuits and Systems
with Nano Electro-Mechanical Relays
Vladimir Stojanović (MIT)
in collaboration with
Tsu-Jae King Liu, Elad Alon (UC Berkeley)
Dejan Marković (UCLA)
June 16, 2011
Subthreshold Leakage: Game Over for CMOS
20
15
10

Etotal
Edynamic
5
Eleakage
0.1

Normalized Energy/op
Normalized Energy/op
25
0.2
0.3
0.4
VDD (V)
0.5
11
More parallelism
does not help
10
1x
9
8x
2x
8
0
1
2 3 4
1/throughput
5
6
Leakage and sub-threshold slope define minimum
energy/op for CMOS
Parallelism cannot reduce power/throughput if already
operating at minimum energy
2
NEM Relays to the Rescue
Measured MEM Relay I-V Curve
MEM Relay Energy vs. VDD
Etotal=Edynamic



NEM relays show zero leakage & sharp sub-threshold slope
Could potentially enable reduced E/op with scaling
Emin set by contact bond energy

~2aJ/switch (50x better than 90nm CMOS)
R. Nathanael et al., “4-Terminal Relay Technology for Complementary
3 Logic,” IEDM 2009
3
NEM Relay Structure and Operation
Tungsten Body
Tungsten Channel
Poly-SiGe Gate
Poly-SiGe Anchor
Poly-SiGe Beam
/Flexure
Tungsten Source/Drain
OFF Relay:
|Vgb| < Vpo (pull-out voltage)
ON Relay:
|Vgb| > Vpi (pull-in voltage)
4
Power-gating CMOS with NEM Relays
B
G
6
G
85μm
55μm
7
DVG = 2V
VG (V)
8
S
D
VDD (V)
5
1.2
G
0.8
G
0.4
VEXT,R
SyncCMOS (V)
VH
0
3
A
R OSC
2
1
0
-0.1
-0.05
0.05
0
0.1
R1
C1
R2
C2
0.15
VG
Vb
Time (s)
3% Duty Cycle
8
COSC
External
pulse gen
Self-driven pulse generator
VDD
Power gate
to CMOS logic
Voltage (V)
6
H. Fariborzi et al.
CICC 2010
4
Power-gating input (VOSC)
2
Gated CMOS VDD
0
0
0.5
1
1.5
2
Time (s)
2.5
3
3.5
5
Energy Gain Over CMOS Limited to Large Toff
8
10
VEXT,M
7
VEXT,R
10
sleep VG
sleep VIO
6
10
CM
T
off
(s)
5
CR
VDD
γCM
10
VEXT,M CMOS LOGIC
Energy gain
,  p ,f ,CL
4
10
VDD
CMOS LOGIC
βCL
,  p ,f ,CL
eCR
βCL
1
3
10
(a)
2
10
2
5
10
(b)
VIO=VNOM VIO=VEXT,M
1
10


32 45
65
90
130
180
Technology node (nm)
250
EM kRon, M I off Toff
GG 

Energy gain
ER
VDD
Ton
Large Toff

Switching overhead negligible
6
Area Savings More Significant
2
10
1
10
0
10
90nm
CMOS
Scaled
Relay
Peak
Current
density
Ion [A/mm 2 ]
-1
10
Current
Relay
-2
10
Ton overhead
MOS 10s
MOS 1ms
MOS 10s
MOS 1ms
-3
10
1%
1%
10%
10%
-4
10
Ton Ron,R
Relay 10s 10k
Relay 1ms 10k
Relay 10s 1k
Relay 1ms 1k
-5
10
-6
10 -2
10

-1
0
1
10
10
10
MOS technology node and relay device pitch [  m]
2
10
Relays fabricated in metal backend - no area overhead
 Today: 1 mA/mm2 (ready for low-power apps)
 Scaled: 10-100 mA/mm2 (ready for high-power apps)
7
NEM Relay as a Logic Element
Anchor
Spring k
Mechanical
Model
Damper b
Mass m
G
Cgc
S
D
Rs
Cgb
Rcs

Simple model
B

Mechanical – spring, mass, damper

Electrical – RC
4-terminal relay mimics MOSFET switch


Rd
Cdb
Csb

Rcd
Electrostatic actuation is ambipolar
Non-inverting logic is possible

Actuation independent of source/drain voltages
8
Digital Circuit Design with NEM Relays
NEMS: 12 switches


CMOS: delay set by electrical time constant

Quadratic delay penalty for stacking devices

Buffer & distribute logical/electrical effort over many stages
NEMS: delay dominated by mechanical movement

Can stack ~100-200 devices before td,elec ≈ td,mech

So, want all to switch simultaneously

 Implement logic as a single complex gate
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Need to Compare at Block Level
NEMS: 12 relays
4 gate delays


1 mechanical delay
Delay Comparison vs. CMOS

Single mechanical delay vs. several electrical gate delays

For reasonable load, NEMS delay unaffected by fan-out/fan-in
Area Comparison vs. CMOS

Larger individual devices

But often need fewer devices to implement same function
F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008
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Example: 32-bit NEMS Adder

Ripple carry configuration


Cascade full adder cells to
create larger complex gate
Stack 32 NEMS, but still
single mechanical delay
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Scaled NEMS vs. CMOS Adders
Energy/op vs. Delay/op across Vdd

Compare vs Sklansky
CMOS adder*


9x
10x

30x less capacitance

Lower device Cg, Cd

Fewer devices
2.4x lower Vdd


90nm technology
No leakage energy
For similar area: >9x lower E/op, >10x greater delay
Patil et. al., “Robust Energy-Efficient Adder Topologies,” in Proc. 18th IEEE Symp.
on Computer Arithmetic (ARITH'07).
*D.
12
Parallelism: Trade Area for Performance
Energy/op vs. Delay/op across Vdd & CL

Can extend energy
benefit up to GOP/s
throughput


As long as parallelism
is available
Area overhead bounded

CMOS needs to be
parallelized at some
point too
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Contact Resistance
Energy/op vs. Delay/op across Vdd & CL

Low contact R not
critical

Good news for
reliability…

Relays with W
contacts lived through
65 B cycles
14
NEM Relay Circuit Technology Platform
ISSCC 2010 – TD Award
F. Chen et al, ISSCC2010
M. Spencer et al, JSSC Jan’11
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NEMS VLSI design infrastructure
P-cell
Spectre
Verilog-A
Verilog-A
Model
Schematic
Vout
Device
A
A
B
Layout
Verilog
B
Logic
Synthesis
Synthesis
Place & Route
Place
Route
LVS
DRC


Verilog-A model and Logic Synthesis created for NEMS technology
The flow supports multiple device designs and foundries
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Toward full systems - NEM Relay scaling
1um litho
Relay size
120um x 150um
0.25um litho
Scaled Relay size
20um x 20um
Sematech
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Conclusions



NEMS unique features enable energy scaling beyond-CMOS

Nearly ideal Ion/Ioff

Switching delay largely independent of electrical

Need to adapt circuit design style

Reliability improving

Circuit level insights critical (contact R)

Demonstrated simple circuits

Started building more complex and scaled systems
Potentially order of magnitude lower E/op than CMOS

Next steps: Large scale demonstration >10k relay uC block with
scaled relays
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Acknowledgements


Circuit design

Fred Chen, Hossein Fariborzi

Matthew Spencer, Abhinav Gupta

Cheng Wang, Kevin Dwan
Device design


Hei Kam, Rhesa Nathanael, Vincent Pott, Jaeseok Jeon
Sponsors

DARPA NEMS program

FCRP (C2S2, MSD)

MIT CICS

Berkeley Wireless Research Center

NSF
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Contact Reliability Experiments
Contact resistance [Ω]
1.E+06
100k specification
1.E+05
1.E+04
1.E+03
L=25m
Measured in ambient
1.E+02
1.E+0 1.E+3 1.E+6 1.E+9
No. of on/off cycles

Higher contact R, hard contact (W) improves reliability


Limits power dissipation, material flow
Current endurance record: 65 billion cycles

Theory/experiments predict >1015 cycles @ 1V VDD
H. Kam et al., “Design and Reliability of a Micro-Relay Technology…,” IEDM 2009
H. Kam et al., “A Predictive Contact Reliability Model for MEM Logic Switches,” IEDM 2010
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