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Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator ADG3304 FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS SPI®, MICROWIRE™ level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces VCCA VCCY A1 Y1 A2 Y2 A3 Y3 A4 Y4 EN GND 04860-001 Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current < 5 μA No direction pin Figure 1. GENERAL DESCRIPTION www.BDTIC.com/ADI The ADG3304 is a bidirectional logic level translator that contains four bidirectional channels. It can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-compatible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCAcompatible logic levels on the A side. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. The EN pin is referred to the VCCA supply voltage and driven high for normal operation. The ADG3304 is available in compact 14-lead TSSOP, 12-ball WLCSP, and 20-lead LFCSP. It is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range. PRODUCT HIGHLIGHTS 1. Bidirectional level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Available in 14-lead TSSOP, 12-ball WLCSP, and 20-lead LFCSP. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADG3304 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Driving Requirements..................................................... 16 Absolute Maximum Ratings............................................................ 6 Output Load Requirements ...................................................... 16 ESD Caution.................................................................................. 6 Enable Operation ....................................................................... 16 Pin Configurations and Function Descriptions ........................... 7 Power Supplies ............................................................................ 16 Typical Performance Characteristics ............................................. 8 Data Rate ..................................................................................... 17 Test Circuits..................................................................................... 12 Applications..................................................................................... 18 Terminology .................................................................................... 15 Layout Guidelines....................................................................... 18 Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 19 Level Translator Architecture ................................................... 16 Ordering Guide .......................................................................... 20 REVISION HISTORY 12/05—Rev. A to Rev. B Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 6 Changes to Figure 3 and Table 4..................................................... 7 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 21 www.BDTIC.com/ADI 6/05—Rev. 0 to Rev. A Added LFCSP Package.......................................................Universal 1/05—Revision 0: Initial Version Rev. B | Page 2 of 20 ADG3304 SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V, TA = 25°C. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage 2 Input Low Voltage2 Output High Voltage Output Low Voltage Capacitance2 Leakage Current Y Side Input High Voltage2 Input Low Voltage2 Output High Voltage Output Low Voltage Capacitance2 Leakage Current Enable (EN) Input High Voltage2 Input Low Voltage2 Leakage Current B Version 1 Typ Symbol Test Conditions/Comments Min VIHA VIHA VILA VOHA VOLA CA ILA, Hi-Z VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 VCCA − 0.4 VY = VCCY, IOH = 20 μA, see Figure 29 VY = 0 V, IOL = 20 μA, see Figure 29 f = 1 MHz, EN = 0, see Figure 34 VA = 0 V/VCCA, EN = 0, see Figure 31 VCCA − 0.4 0.4 9 ±1 VCCY − 0.4 VIHEN VIHEN VILEN ILEN VCCY − 0.4 VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 VCCA − 0.4 ±1 0.4 ±1 V V V μA 3 1 1.8 pF μs 6 2 2 10 3.5 3.5 ns ns ns 2 4 3 Mbps ns ns 0.4 6 www.BDTIC.com/ADI VEN = 0 V/VCCA, VA = 0 V, see Figure 33 CEN tEN RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y), VY = 0 V/VCCY (Y→A), see Figure 36 SWITCHING CHARACTERISTICS2 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation V V V pF μA V V V V pF μA 0.4 VA = VCCA, IOH = 20 μA, see Figure 30 VA = 0 V, IOL = 20 μA, see Figure 30 f = 1 MHz, EN = 0, see Figure 35 VY = 0 V/VCCY, EN = 0, see Figure 32 Unit V 0.4 VIHY VILY VOHY VOLY CY ILY, Hi-Z Capacitance2 Enable Time2 Max RS = RT = 50 Ω, CL = 50 pF, see Figure 37 Propagation Delay Rise Time tP, A→Y tR, A→Y Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Y→A Level Translation Propagation Delay Rise Time tP, Y→A tR, Y→A 4 1 7 3 ns ns Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 3 7 2 3.5 2 ns Mbps ns ns 50 Rev. B | Page 3 of 20 ADG3304 Parameter 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Test Conditions/Comments Min B Version 1 Typ Max Unit 8 2 2 11 5 5 2 4 4 ns ns ns Mbps ns ns 5 8 ns 2 2 3.5 3.5 2 3 3 ns ns Mbps ns ns 9 3 2 18 5 5 2 5 10 5 2 2 9 4 4 2 4 4 12 7 3 25 12 5 2 5 ns ns ns Mbps ns 15 ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 50 RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y www.BDTIC.com/ADI RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 40 ns ns ns Mbps ns ns tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y Rev. B | Page 4 of 20 25 ADG3304 Parameter Y→A Translation Symbol Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Test Conditions/Comments RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A Min Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 2 35 ns 5 2.5 16 6.5 3 6.5 23.5 ns ns Mbps ns ns 7 10 ns 2.5 2 4 5 1.5 2 4 ns ns Mbps ns ns 5 1 3 8 4 5 2 3 3 ns ns ns Mbps ns ns 0.17 5.5 5.5 5 V V μA 0.27 5 μA 0.1 0.1 5 5 μA μA RS = RT = 50 Ω, CL = 15 pF, see Figure 38 VCCA VCCY ICCA ICCY 1 14 60 www.BDTIC.com/ADI Three-State Mode Power Supply Current Unit RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y Quiescent Power Supply Current Max 25 Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Translation POWER REQUIREMENTS Power Supply Voltages B Version 1 Typ IHi-Z, A IHi-Z, Y 60 VCCA ≤ VCCY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 Temperature range is as follows: B version: −40°C to +85°C for the TSSOP and LFCSP; −25°C to +85°C for the WLCSP. Guaranteed by design, not production tested. Rev. B | Page 5 of 20 1.15 1.65 ADG3304 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Extended Industrial (B Version) TSSOP and LFCSP Industrial (B Version) WLCSP Storage Temperature Range Junction Temperature θJA Thermal Impedance (4-Layer Board) 14-Lead TSSOP 12-Ball WLCSP 20-Lead LFCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to (VCCA + 0.3 V) −0.3 V to (VCCY + 0.3 V) −0.3 V to +7 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C Only one absolute maximum rating can be applied at any one time. −25°C to +85°C −65°C to +150°C 150°C 89.21°C/W 120°C/W 30.4°C/W 300°C 260°C www.BDTIC.com/ADI ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 20 ADG3304 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A1 2 A2 3 ADG3304 12 Y2 A3 4 TOP VIEW (Not to Scale) 11 Y3 Y1 VCCY A1 20 19 18 17 16 c Y2 13 Y1 VCCA NC A2 A3 A4 NC A2 2 Y3 EN A3 Y4 GND A4 PIN 1 INDICATOR 1 2 3 4 5 ADG3304 TOP VIEW (Not to Scale) 10 Y4 NC 6 9 NC GND 7 8 EN NC = NO CONNECT 4 TOP VIEW (BALLS AT THE BOTTOM) Not to Scale Figure 2. 14-Lead TSSOP Pin Configuration Figure 3. 12-Ball WLCSP Pin Configuration NC NC GND EN NC 5 04860-003 A4 6 7 8 9 10 3 15 NC 14 Y2 13 Y3 12 Y4 11 NC NC = NO CONNECT NOTES 1. THE EXPOSED PADDLE CAN BE TIED TO GND OR LEFT FLOATING. DO NOT TIE IT TO VCCA or VCCY. Figure 4. 20-Lead LFCSP_VQ Pin Configuration Table 3. 14-Lead TSSOP and 20-lead LFCSP Pin Function Descriptions TSSOP 1 2 3 4 5 6, 9 7 8 10 11 12 13 14 Pin No. LFCSP 19 20 2 3 4 1, 5, 6, 7, 10, 11, 15, 16 8 9 12 13 14 17 18 Mnemonic VCCA A1 A2 A3 A4 NC GND EN Y4 Y3 Y2 Y1 VCCY Description Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY). Input/Output A1. Referenced to VCCA. Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. No Connect. Ground. Active High Enable Input. Input/Output Y4. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Input/Output Y1. Referenced to VCCY. Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V). www.BDTIC.com/ADI Table 4. 12-Ball WLCSP Pin Function Descriptions Bump No. a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 Mnemonic Y1 Y2 Y3 Y4 VCCY VCCA EN GND A1 A2 A3 A4 Description Input/Output Y1. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y4. Referenced to VCCY. Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V). Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY). Active High Enable Input. Ground. Input/Output A1. Referenced to VCCA. Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. Rev. B | Page 7 of 20 04860-057 14 VCCY 1 b 1 04860-002 VCCA a A1 VCCA VCCY Y1 NC BALL a1 INDICATOR ADG3304 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 3.0 TA = 25°C 1 CHANNEL CL = 50pF 0.9 2.5 0.8 VCCA = 3.3V, VCCY = 5V 0.7 2.0 0.6 ICCY (mA) ICCA (mA) TA = 25°C 1 CHANNEL CL = 15pF 0.5 0.4 VCCA = 1.8V, VCCY = 3.3V 0.3 VCCA = 3.3V, VCCY = 5V 1.5 1.0 VCCA = 1.8V, VCCY = 3.3V 0.2 0.5 0.1 VCCA = 1.2V, VCCY = 1.8V 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 VCCA = 1.2V, VCCY = 1.8V 0 0 15 20 25 30 35 40 45 50 Figure 8. ICCY vs. Data Rate (Y→A Level Translation) 1.6 TA = 25°C 1 CHANNEL CL = 50pF 9 10 DATA RATE (Mbps) Figure 5. ICCA vs. Data Rate (A→Y Level Translation) 10 5 04860-007 0 04860-004 0 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V 1.4 8 20Mbps 1.2 7 ICCY (mA) 1.0 www.BDTIC.com/ADI 5 4 10Mbps 0.6 VCCA = 1.8V, VCCY = 3.3V 3 0.8 0.4 5Mbps 2 VCCA = 1.2V, VCCY = 1.8V 1 0 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 0 53 63 73 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY =1.8V 0.9 0.8 0.7 ICCA (mA) 2.0 1.5 1.0 0.6 20Mbps 0.5 0.4 0.3 VCCA = 1.8V, VCCY = 3.3V 10Mbps 5Mbps 0.2 0.5 VCCA = 1.2V, VCCY = 1.8V 0 5 10 15 20 25 30 35 40 0.1 45 DATA RATE (Mbps) 50 1Mbps 0 04860-006 0 43 1.0 VCCA = 3.3V, VCCY = 5V ICCA (mA) 33 Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V) Level Translation TA = 25°C 1 CHANNEL CL = 15pF 2.5 23 CAPACITIVE LOAD (pF) Figure 6. ICCY vs. Data Rate (A→Y Level Translation) 3.0 13 04860-012 1Mbps 04860-005 0 0.2 13 23 33 43 CAPACITIVE LOAD (pF) 53 Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V) Level Translation Figure 7. ICCA vs. Data Rate (Y→A Level Translation) Rev. B | Page 8 of 20 04860-013 ICCY (mA) VCCA = 3.3V, VCCY = 5V 6 ADG3304 9 7 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 8 7 TA = 25°C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 50Mbps 50Mbps 5 ICCA (mA) ICCY (mA) 6 5 30Mbps 4 4 30Mbps 3 20Mbps 3 20Mbps 2 2 10Mbps 10Mbps 1 1 33 43 53 CAPACITIVE LOAD (pF) 63 0 04865-016 23 73 13 53 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 3.5 VCCA = 1.2V, VCCY = 1.8V 7 50Mbps 3.0 RISE TIME (ns) ICCA (mA) 43 Figure 14. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V) Level Translation 5.0 4.0 33 CAPACITIVE LOAD (pF) Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V) Level Translation 4.5 23 04860-021 5Mbps 5Mbps 0 13 2.5 2.0 30Mbps 6 5 4 www.BDTIC.com/ADI 1.5 VCCA = 1.8V, VCCY = 3.3V 3 20Mbps 1.0 2 10Mbps 0.5 VCCA = 3.3V, VCCY = 5V 5Mbps 23 33 43 CAPACITIVE LOAD (pF) 53 0 13 04860-017 0 13 Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V) Level Translation 33 43 53 CAPACITIVE LOAD (pF) 63 73 Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation) 4.0 12 TA = 25°C 1 CHANNEL VCCA = 3.3V 10 V CCY = 5V 23 04860-023 1 50Mbps 3.5 TA = 25°C 1 CHANNEL DATA RATE = 50kbps VCCA = 1.2V, VCCY = 1.8V 3.0 FALL TIME (ns) 30Mbps 6 20Mbps 4 2.5 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 1.0 10Mbps 2 0.5 0 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 13. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V) Level Translation 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 04860-024 5Mbps 04860-020 ICCY (mA) 8 Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Rev. B | Page 9 of 20 ADG3304 12 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 VCCA = 1.2V, VCCY = 1.8V 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 8 6 VCCA = 1.8V, VCCY = 3.3V 4 2 1 VCCA = 3.3V, VCCY = 5V 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) 0 13 04860-025 18 23 33 43 53 63 73 CAPACITIVE LOAD (pF) 04860-028 VCCA = 3.3V, VCCY = 5V 0 13 Figure 20. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation) 9 4.0 TA = 25°C 8 1 CHANNEL DATA RATE = 50kbps PROPAGATION DELAY (ns) TA = 25°C 1 CHANNEL DATA RATE = 50kbps 3.5 3.0 2.5 VCCA = 1.2V, VCCY = 1.8V 2.0 1.5 VCCA = 1.8V, VCCY = 3.3V 7 VCCA = 1.2V, VCCY = 1.8V 6 5 4 www.BDTIC.com/ADI 1.0 0.5 3 VCCA = 1.8V, VCCY = 3.3V 2 VCCA = 3.3V, VCCY = 5V 1 0 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 0 13 18 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) 04860-029 VCCA = 3.3V, VCCY = 5V 04860-026 FALL TIME (ns) VCCA = 1.2V, VCCY = 1.8V 10 PROPAGATION DELAY (ns) RISE TIME (ns) 7 DATA RATE = 50kbps TA = 25°C 1 CHANNEL Figure 21. Propagation Delay (tPLH) vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation) 9 TA = 25°C 1 CHANNEL 8 DATA RATE = 50kbps 14 PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 8 VCCA = 1.8V, VCCY = 3.3V 4 VCCA = 3.3V, VCCY = 5V VCCA = 1.2V, VCCY = 1.8V 7 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 VCCA = 3.3V, VCCY = 5V 2 1 2 0 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 Figure 22. Propagation Delay (tPHL) vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y (A→Y Level Translation) Rev. B | Page 10 of 20 53 04860-030 6 04860-027 PROPAGATION DELAY (ns) TA = 25°C 1 CHANNEL 12 DATA RATE = 50kbps ADG3304 TA = 25°C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL 400mV/DIV Figure 26. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps) Figure 23. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps) TA = 25°C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL www.BDTIC.com/ADI 5ns/DIV 04860-038 200mV/DIV CL = 50pF 1 CHANNEL 1V/DIV Figure 27. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps) Figure 24. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps) 500mV/DIV TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL CL = 50pF 1 CHANNEL 3ns/DIV 04860-039 TA = 25°C DATA RATE = 50Mbps 3ns/DIV 04860-041 TA = 25°C DATA RATE = 25Mbps 3ns/DIV 800mV/DIV 3ns/DIV Figure 28. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps) Figure 25. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps) Rev. B | Page 11 of 20 04860-042 5ns/DIV 04860-040 04860-037 400mV/DIV TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL ADG3304 TEST CIRCUITS EN VCCA ADG3304 VCCY 0.1μF 0.1μF EN ADG3304 VCCA A VCCY Y 0.1μF 0.1μF K2 K1 GND IOH A K Y A IOL Figure 29. VOH/VOL Voltages at Pin A EN ADG3304 VCCA Figure 32. Three-State Leakage Current at Pin Y VCCY 0.1μF 0.1μF VCCA K2 ADG3304 VCCY 0.1μF Y A 04860-046 04860-043 GND 0.1μF www.BDTIC.com/ADI K1 A Y GND A IOL 04860-044 EN ADG3304 GND Figure 33. EN Pin Leakage Current Figure 30. VOH/VOL Voltages at Pin Y VCCA EN K 04860-047 IOH EN VCCA VCCY ADG3304 VCCY 0.1μF 0.1μF A A Y A Y K GND 04860-045 04860-048 CAPACITANCE METER GND Figure 34. Capacitance at Pin A Figure 31. Three-State Leakage Current at Pin A Rev. B | Page 12 of 20 ADG3304 EN VCCA ADG3304 VCCY A Y CAPACITANCE METER 04860-049 GND Figure 35. Capacitance at Pin Y A→Y DIRECTION VCCA 0.1μF VCCY ADG3304 + 10μF + 10μF 0.1μF 1MΩ A VA K1 Y VY K2 50pF 1MΩ SIGNAL SOURCE EN Z0 = 50Ω RS GND VEN 50Ω RT 50Ω Y→A DIRECTION www.BDTIC.com/ADI VCCA 0.1μF VCCY ADG3304 + 10μF + 10μF 0.1μF 1MΩ K1 A VA Y VY K2 15pF 1MΩ SIGNAL SOURCE EN Z0 = 50Ω RS 50Ω GND VEN RT 50Ω VEN tEN1 VCCA 0V VCCA/VCCY VA/VY 0V VCCY/VCCA 90% VY/VA tEN2 VCCA 0V VA/VY VCCA/VCCY 0V VCCY/VCCA VY/VA 10% 0V NOTES 1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2 IN BOTH A→Y AND Y→A DIRECTIONS. Figure 36. Enable Time Rev. B | Page 13 of 20 04860-050 VEN 0V ADG3304 EN VCCY ADG3304 VCCA SIGNAL SOURCE RS 50Ω 0.1μF Z0 = 50Ω V A EN + 10μF 0.1μF + 10μF Y RT 50Ω VCCY VA VY SIGNAL SOURCE A Y VY Z0 = 50Ω RS 50Ω RT 50Ω 15pF 50pF + 10μF 0.1μF + 10μF 0.1μF A ADG3304 VCCA GND GND VY VA 50% tP,A→Y tP,A→Y VA VY tP,Y→A tP,Y→A 90% 50% 10% tF,A→Y tR,A→Y 04860-051 90% 50% 10% Figure 37. Switching Characteristics (A→Y Level Translation) tF,Y→A www.BDTIC.com/ADI Rev. B | Page 14 of 20 tR,Y→A Figure 38. Switching Characteristics (Y→A Level Translation) 04860-052 50% ADG3304 TERMINOLOGY VIHA Logic input high voltage at Pin A1 to Pin A4. TF, A→Y Fall time when translating logic levels in the A→Y direction. VILA Logic input low voltage at Pin A1 to Pin A4. DMAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. VOHA Logic output high voltage at Pin A1 to Pin A4. TSKEW, A→Y Difference between propagation delays on any two channels when translating logic levels in the A→Y direction. VOLA Logic output low voltage at Pin A1 to Pin A4. CA Capacitance measured at Pin A1 to Pin A4 (EN = 0). tPPSKEW, A→Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the A→Y direction. ILA, Hi-Z Leakage current at Pin A1 to Pin A4 when EN = 0 (high impedance state at Pin A1 to Pin A4). VIHY Logic input high voltage at Pin Y1 to Pin Y4. tP, Y→A Propagation delay when translating logic levels in the Y→A direction. VILY Logic input low voltage at Pin Y1 to Pin Y4. tR, Y→A Rise time when translating logic levels in the Y→A direction. VOHY Logic output high voltage at Pin Y1 to Pin Y4. tF, Y→A Fall time when translating logic levels in the Y→A direction. VOLY Logic output low voltage at Pin Y1 to Pin Y4. CY Capacitance measured at Pin Y1 to Pin Y4 (EN = 0). DMAX, Y→A Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1. ILY, Hi-Z Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high impedance state at Pin Y1 to Pin Y4). tSKEW, Y→A Difference between propagation delays on any two channels when translating logic levels in the Y→A direction. VIHEN Logic input high voltage at the EN pin. VILEN Logic input low voltage at the EN pin. tPPSKEW, Y→A Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y→A direction. CEN Capacitance measured at EN pin. VCCA VCCA supply voltage. ILEN Enable (EN) pin leakage current. VCCY VCCY supply voltage. tEN Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to Pin Y4. ICCA VCCA supply current. www.BDTIC.com/ADI ICCY VCCY supply current. tP, A→Y Propagation delay when translating logic levels in the A→Y direction. IHi-Z, A VCCA supply current during three-state mode (EN = 0). tR, A→Y Rise time when translating logic levels in the A→Y direction. IHi-Z, Y VCCY supply current during three-state mode (EN = 0). Rev. B | Page 15 of 20 ADG3304 THEORY OF OPERATION The ADG3304 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCA-compatible logic levels to VCCY-compatible logic levels available at the Y pins. Similarly, because the device is capable of bidirectional translation, when driving the Y pins, the VCCYcompatible logic levels are translated to VCCA-compatible logic levels available at the A pins. When EN = 0, Pin A1 to Pin A4 and Pin Y1 to Pin Y4 are three-stated. When EN is driven high, the ADG3304 goes into normal operation mode and performs level translation. INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3304, the circuit that drives the input of the ADG3304 channels should have an output impedance of less than or equal to 150 Ω and a minimum peak current driving capability of 36 mA. OUTPUT LOAD REQUIREMENTS The ADG3304 level translator is designed to drive CMOScompatible loads. If current-driving capability is required, it is recommended to use buffers between the ADG3304 outputs and the load. ENABLE OPERATION The ADG3304 provides three-state operation at the A and Y I/O pins by using the enable pin (EN), as shown in Table 5. LEVEL TRANSLATOR ARCHITECTURE The ADG3304 consists of four bidirectional channels. Each channel can translate logic levels in either the A→Y or the Y→A direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 39 shows a simplified block diagram of a bidirectional channel. Table 5. Truth Table EN 0 1 1 VCCA VCCY T1 2 P High impedance state. In normal operation, the ADG3304 performs level translation. www.BDTIC.com/ADI 6kΩ A A I/O Pins Hi-Z1 Normal operation2 While EN = 0, the ADG3304 enters into three-state mode. In this mode, the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical, especially on battery-operated systems. The EN input pin can be driven with either VCCA-compatible or VCCY-compatible logic levels. T2 U1 Y I/O Pins Hi-Z1 Normal operation2 U2 ONE-SHOT GENERATOR Y N POWER SUPPLIES T4 U3 T3 04860-053 6kΩ U4 Figure 39. Simplified Block Diagram of an ADG3304 Channel The logic level translation in the A→Y direction is performed using a level translator (U1) and an inverter (U2), while the translation in the Y→A direction is performed using Inverter U3 and Inverter U4. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1 to T2) for a rising edge, or the NMOS transistors (T3 to T4) for a falling edge. This charges/discharges the capacitive load faster, which results in faster rise and fall times. For proper operation of the ADG3304, the voltage applied to the VCCA must be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG3304 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, VCCA can be greater than VCCY due to a significant increase in the current taken from the VCCA supply. For optimum performance, the VCCA pin and VCCY pin should be decoupled to GND as close as possible to the device. The inputs of the unused channels (A or Y) should be tied to their corresponding VCC rail (VCCA or VCCY) or to GND. Rev. B | Page 16 of 20 ADG3304 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see the Absolute Maximum Ratings section). Table 6 shows the guaranteed data rates at which the ADG3304 can operate in both directions (A→Y or Y→A level translation) for various VCCA and VCCY supply combinations. Table 6. Guaranteed Data Rate (Mbps) 1 VCCY VCCA 1.2 V (1.15 V to 1.3 V) 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V) 1 1.8 V (1.65 V to 1.95 V) 25 - 2.5 V (2.3 V to 2.7 V) 30 45 - 3.3 V (3.0 V to 3.6 V) 40 50 60 - The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction. www.BDTIC.com/ADI Rev. B | Page 17 of 20 5V (4.5 V to 5.5 V) 40 50 50 50 - ADG3304 APPLICATIONS The ADG3304 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals are connected to the Y pins. The ADG3304 can provide level translation in both directions from A→Y or Y→A on all four channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG3304 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. It also allows simultaneous data flow in both directions on the same part, for example, when two channels translate in A→Y direction while the other two translate in Y→A direction. This simplifies the design by eliminating the timing requirements for the direction signal and reducing the number of ICs used for level translation. 100nF VCCA 1.8V VCCY A1 I/OL1 3.3V I/OH1 Y1 ADG3304 MICROPROCESSOR/ MICROCONTROLLER/ DSP GND I/OL2 A2 Y2 I/OH2 I/OL3 A3 Y3 I/OH3 I/OL4 A4 Y4 I/OH4 EN GND GND CS 100nF PERIPHERAL DEVICE 1 100nF VCCA VCCY A1 Y1 3.3V I/OH1 ADG3304 A2 Y2 I/OH2 A3 Y3 I/OH3 A4 Y4 I/OH4 EN GND GND PERIPHERAL DEVICE 2 04860-055 Figure 40 shows an application where two microprocessors operating at 1.8 V and 3.3 V, respectively, can transfer data simultaneously using two full-duplex serial links, TX1/RX1 and TX2/RX2. 100nF 100nF Figure 41. 1.8 V to 3.3 V Level Translation Circuit Using the Three-State Feature 100nF LAYOUT GUIDELINES VCCA 1.8V TX1 A1 www.BDTIC.com/ADI VCCY Y1 3.3V RX1 ADG3304 GND RX1 A2 Y2 TX1 Y3 RX2 TX2 A3 RX2 A4 Y4 TX2 EN GND GND MICROPROCESSOR/ MICROCONTROLLER/ DSP 04860-056 MICROPROCESSOR/ MICROCONTROLLER/ DSP Figure 40. 1.8 V to 3.3 V Level Translation Circuit on Two Full-Duplex Serial Links When the application requires level translation between a microprocessor and multiple peripheral devices, the ADG3304 I/O pins can be three-stated by setting EN = 0. This feature allows the ADG3304 to share the data buses with other devices without causing contention issues. Figure 41 shows an application where a 1.8 V microprocessor is connected to a 3.3 V peripheral device using the three-state feature. As with any high speed digital IC, the printed circuit board layout is important for the overall performance of the circuit. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA pin and the VCCY pin. The parasitic inductance of the high speed signal track may cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path (GND) is also recommended. Rev. B | Page 18 of 20 ADG3304 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.05 1.00 0.80 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 42. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 0.65 0.59 0.53 SEATING PLANE 1.67 1.61 1.55 C B A 1 www.BDTIC.com/ADI 0.36 0.32 0.28 BALL 1 IDENTIFIER 2.07 2.01 1.95 TOP VIEW (BALL SIDE DOWN) 2 0.50 BSC BALL PITCH 3 0.17 0.15 0.13 BOTTOM VIEW (BALL SIDE UP) Figure 43. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 20 1 16 15 2.25 2.10 SQ 1.95 3.75 BCS SQ 0.75 0.55 0.35 12° MAX 1.00 0.85 0.80 SEATING 0.50 PLANE BSC PIN 1 INDICATOR 11 10 0.80 MAX 0.65 TYP 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF 6 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 44. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters Rev. B | Page 19 of 20 111105-0 4 0.28 0.24 0.20 ADG3304 ORDERING GUIDE Model ADG3304BRUZ 2 ADG3304BRUZ-REEL2 ADG3304BRUZ-REEL72 ADG3304BCPZ-REEL2 ADG3304BCPZ-REEL72 ADG3304BCBZ-REEL2 ADG3304BCBZ-REEL72 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −25°C to +85°C −25°C to +85°C Package Description 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 14-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12-Ball Wafer Level Chip Scale Package [WLCSP] 12-Ball Wafer Level Chip Scale Package [WLCSP] Branding on these packages is limited to three characters due to space constraints. Z = Pb-free part. www.BDTIC.com/ADI © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04860-0-12/05(B) Rev. B | Page 20 of 20 Branding 1 SDC SDC Package Option RU-14 RU-14 RU-14 CP-20-1 CP-20-1 CB-12 CB-12