Download ODMB Version 1 Modifications (M.Matveev) December 13, 2012

ODMB Version 1 Modifications (M.Matveev)
December 13, 2012
A. Mechanical fit and front panel
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The PCB needs to be 93 mil thick
PCB cuts along the top and bottom of the are needed (crate rails are built for 62 mil boards)
J1 (LVMB connector) needs to be moved lower for ~ 10 mm for easier cable connection
J2 is incompatible with the Xilinx cable receptacle; needs to be replaced with the smaller one
(Molex 87833-1420 or FCI 98464-G61-14). Pin assignment should be corrected per Xilinx JTAG
cable spec http://www.xilinx.com/support/documentation/data_sheets/ds593.pdf
5. Suggest an individual green LED for each active power on board (P5V; P3.3V; P2V5; P1V0; P1V8;
P1V2; VCCR; VCCT; P3.3VOTX; P3.3VORX); to be placed on the bottom of the front panel.
6. Suggest to replace a two-row LED matrix with individual LEDs or a one-row matrixes; then it
would be easier to place the LED names on the front panel (LED on the left and its name on the
right)
7. Attach front panel to the PCB in the third point (in the middle; need an extra hole)
B. Schematic Page 1 (VME backplane Interface)
1. Remove RG2 and ST52
2. Replace IC26, IC14, (both SN 74ALVC16245) with SN74ALVTH16245 with VCC=2.5V.
3. Suggest to latch VME_ADDR[23..1] and LWORD signals with the inversed AS strobe (then
two SN74ALVTH16374 are needed instead of IC28 and IC27). C_VME_AS_B,
C_VME_DS0_B, C_VME_DS1_B should be translated thru the SN74ALVTH16245.
4. Remove T1, connect VME_DIR to pins 1&24 of IC14.
C. Schematic Page 2 (CCB backplane Interface)
1. IC34, IC36, IC38 are the GTLP16612 devices with the A port assigned for TTL and the B
port for GTLP. Ports A and B must be reverted for a correct interface to the CCB (J6 is a
GTLP interface!). Control interface needs to be modified. This is a major problem.
2. C_CCB_L1ARST should be connected to J6-B2 (former CCB_Reserved4). J6-D4 is a
C_CCB_EVCNTRES signal
3. Replace IC33, IC35, IC37, IC39 (SN74ALVC16245) with the SN74ALVTH16245
(VCCA=2.5V)
D. Schematic Page 3 (TMB backplane interface)
1. Replace IC41-IC45 (SN74ALVC16245) with the SN74ALVTH16245 (VCCA=2.5V)
E. Schematic Page 4 (FPGA interface)
1. CCB_Hardreset signal from IC33-26 is expected to arrive to the PROGRAM_B pin of the
FPGA IC32-L8 to reconfigure it from the PROM; suggest to provide it thru jumper
2. J2 needs to be modified (part and pin assignment) to match the Xilinx JTAG cable.
3. 100/100Ohm Thevenin termination is needed for the CCLK line
4. Replace IC29 (SN74ALVC16245) with the SN74ALVTH16245 (VCCA=2.5V)
F. Schematic Page 5 (FPGA interface)
1. Suggest to apply P2V5 instead of P5V to R11-R22.
2. Jumpers ST17-ST39 can be removed, with pull-downs directly connected to AD[22:0] lines.
3. Suggest to replace two-row LED matrix with individual LEDs or one-row matrixes; use yellow
LED for DTACK signal; add dedicated LEDs for all active powers on board (above); add yellow
LED for JTAG TCK signal.
G. Schematic Page 6 (Clocks)
1. QZ1 pin 1 should be connected to P3V3 or jumper; or use a different part (always enabled).
Suggest a 3.3V part instead of 5V.
2. Remove FD_CLR and FD_PRE signals, T6 and T7 transistors.
Connect IC13-13 and IC13-10 to 3.3V permanently.
3. Pin 2 of QZ3 is actually Chip Enable; a jumper to GND
can disable it completely.
4. The 40MHz clock from CCB is now coming directly to QPLL
IC12-1,2. I would add an intermediate LVDS receiver SN65LVDT2
with embedded 100 Ohm termination for this clock; the output
of this chip would go to a jumper; then either IC13-9 or
LVDT2-5 would be connected to IC12-3. The LVDS inputs of
IC12 then are unused (pin to 2.5V and pin 2 to GND).
5. Connect IC12-27 to 2.5V permanently, remove the line QPLL_MODE to FPGA.
Then "mode"=1 (160MHZ). Also remove ST9.
6. Remove connection from the FPGA to IC12-4 (QPLL_EXTCONTROL). ST11 remains in
place.
7. Add 4.7KOhm resistor (to 2.5V) to IC12-6.
8. Provide IC12-9 output not only to FPGA (this connection exists),
but directly to one of the green LEDs on the front panel; same
circuitry as for DONE and INIT_B signals.
9. IC7 (CDC857) needs to be replaced or removed.
10. IC32 part on this page needs to be fixed (signal names)
11. CCLK=80MHz is too high for configuration. Use a 40Mhz part with VCC=2.5V. Then don’t
need IC31.
H. Schematic Page 7 (Optical Interface)
1. 100KOhm terminators (100 pcs) are not needed.
I. Schematic Page 8 (PROM, DAC, ADC, Test points)
1. IC8 and IC10 are the +5V devices. For communication with the 2.5V FPGA an intermediate
level converter (SN74ALVTH16245) is needed.
J. Schematic Page 9 (Voltage regulators)
1. Tab (case) in RG3, RG4, RG5 is VOUT, not GND.
K. Schematic Page 10 (LVMB Interface)
L. Replace IC3, IC5, IC6 (SN74ALVC16245) with the SN74ALVTH16245 (VCCA=2.5V)
M. Schematic Page 11 (Discrete Logic Interface)
1. TDO output from the JTAG is not present. Needs to be implemented for emergency PROM
loading since access to PROM is indirect through the FPGA.