Download 1 - SLAC

1) JP2, ~ps_on jumper doesn’t seem to have any effect – check to see if related to
VR2 and VR8 error in pin-out. NOT. 68K only pulls down to 1.2V, 2.5V
guaranteed to turn off – change R56 to 10K. SN001, SN002, and SN003 done.
C00 and C01 schematics modified.
2) VR2 and VR8 are pinned out incorrectly. 1,2,3,A,4,5,6 in datasheet/sch –
1,2,3,4,5,6 in layout. Pins 5 and 6 (component datasheet numbering) need to be
soldered into pads 4 and 5 of board, 6 stays open.SN001-003 done.
PADS part decal fixed, pin numbering is 1,2,3,A,4,5 – was 1,2,3,A,5,6.
3) Change R55 to 4.02K. Changes v_mgt_supply to 2.9V from 2V. Need to change
schematic in C01, so that the 2.5 slice regulators operate from 3.3V bus like the
CE regulators do. SN001-003 done.
C00 and C01 schematics modified.
4) Voltage drop across planes – 1.2V is 1.14 at FPGA’s – change to R50 to 20K,
increase by 50mV. 1.5V is at 1.41, increase by 50mV – change R51 to 12.1K.
SN001-003 done.
C00 and C01 schematics modified.
5) If power supplies stay by front panel – will want to be using the remote sensing
on the power supplies.
6) Slice to CE MGT lines don’t have the TX/RX cross – Slice TX should go to CE
RX. All 8 lanes.
C01 schematics modified, top labels read ce_tx/rx_srx/tx_p/m showing
source and destination cross.
7) ~ RELOAD_FPGA_FIRMWARE needs to be pulled up. If FPGA not
programmed signal is in an undefined state. Added 1K pull-up between 1 and 5
of S(1-8)U2’s. SN001-003 done.
C01 schematics modified with 4.7k resistor to 3.3v in slices.
8) Weak pull-ups on un-programmed FPGA pins insufficient to guaranty state. Need
to add pull-up on ~RELOAD_FPGA_FIRMWARE in slices, and on
~GRACEFUL_REBOOT in CE’s.
C01 schematics modified, s1-8 done above, ce1-2 added 4.7k to 3.3v and
0.1uf to gnd.
9) Increase value of pullups on ~COLD_BOOT, used to reset all 10 FPGA’s –
change to 47K each.
C01 schematics modified, s1-8 changed to 47k to 3.3v, ce1-2 with 47k to
2.5v.
10) Fix PCB symbol for 45 degree connectors – rows offset from one another.
TTP to do
11) Fix/agree/check alpha-numeric on fibers, DC-DC’s to convert to numerics. Leave
as alpha-numerics, just need to fix the DC-DC’s in step 2.
TTP to do
12) Fix board outline to get better mating of PWR/GND connectors in Zone 3.
TTP to do
13) Check pull-up’s on JTAG chain.
Done.
14) Add JTAG down-loadable re-programmability to the various Xilinx FPGA. Need
to determine how. Change programming scheme from Master-serial to slave serial
with partitions, revisions, and compression. This will involve PU/PD on mode
bits: 111 = slave, 000 = master – to revert back. FPGA CCLK needs to be end
terminated at FPGA, and PROM CLK and CLKOUT need terminations as well as
selection resistors to choose which mode to use. Will also need logic to do the
rev_sel, 00 at power-up/cold_boot, 01 at other boot. Will also need a driver to
switch JTAG programming between the cable and the FPGA, where the FPGA
can JTAG reprogram the 2nd ( unprotected) partition of the PROM.
JTAG pins connected to bank 1 of RCE’s. Note that the hexswitch pins have been
moved and re-arranged to have the rce_slice JTAG pins in a block. Added buffer
to each CE to allow the RCE to reprogram the Prom’s only, also one RCE is
connected to the slices, and can reprogram the slice proms and fpgas.
15) See what to do for RTM signals/connectors.
Will be done on the RTM.
16) Check power/current levels to see if we want to stay with current DC-DC current
ratings. Seems fine as is?
Check to see if desired.
17) Add more temperature monitoring? Xilinx has internal diode.
Check to see if desired.
18) Remove TP’s from RLDRAM.
Done.
19) Check power planes. The 12V feed to Front Panel DC-DC’s seems starved.
TTP to do.
20) Change logic of main feeds from enable to disable through jumpers.
Check to see if desired.
21) Add EEPROM powered from IPMB_3_3V and written by a CE for IPM
controller.
Check to see if desired.
22) Check with Matt what would be needed to ensure that board is compatible with all
architectures.
Mweaver/mlf to do.
23) Add LED 2, (Health) controlled from IPM per spec. Green, 521-9210F.
Done.
24) Add Heat-sink - 375024B00032
Done.
25) HSWAPEN needs to be pulled down to guaranty pre-configuration I/O pull-ups.
Done, added 4.7k pulldown.
26) Done termination resistor is recommended 330 Ohm,
Done, changed 4.7k to 330.
27) CCLK should be 50Ohm trace with 100Ohm up/down termination at end. Route
in series, not star.
TTP to do, locations of RCE CCLK added termination resistors per schematic
pages.
28) Virtex4 TMS and TDI already have pull-ups internal.
No Change.
29) Use revision control on PROMS, adding JTAG from FPGA to PROM. Will need
driver to enable/disable source of JTAG. Will probably want to add second
PROM to chain. Will we want same for FX20’s?
Revision control done in ISE, RCE’s have been set to rev control and
compression, slices not done. RCE’s can download proms and RCE2 can
reprogram slices.
30) Fix Xilinx symbols to add dedicated in/out properties on pins.
Done.
31) Fix FX60 ordering information, shouldn’t be ES4 anymore.
Done.
32) Fix front panel LED hole locations.
TTP to do.
33) LED1 label can be changed to OOS (Out-Of-Service) if desired, and Blue Led
label can be changed to HSWP.
DTark to do.
34) Change Part number for Blue Led to 521-9831F, LED1 to 521-9211F if only
yellow or else to 521-9768F if dual color Red/Yellow desired.
Done.
35) Need to determine final version of panel/switch/handles that will be used.
Done? Haven’t seen anything more available that is better.
36) Signals to RCE_RTM for TX_DIS on HFBR’s need to be added to FPGA’s on a
3.3V bank – Added to bank7.
Done.
37) On the next spin of the RCE, can you change the following zone 2 ethernet
connection? Move the signals labelled CE2_LANE15_{TX/RX} (currently
connected to J23 A5-D5) to connect to J23 A6-D6. I was mistaken about which
of the two base interfaces is actually connected in a
2 slot backplane.
Done.
38) Add ground pins for clipping on scope.
Added TP1-4, also checking into grounding the FMC connector clips.
39) Had to move the 4 hexswitch bits from bank 1 to bank to accommodate revision
selection voltage levels for the prom. Do the switches need pull-up resistors or is
that done in the CE?
40)