Download paper

185
2006 IEEE Electrical Performance of Electronic Packaging
Accurate System Voltage and Timing Margin
Simulation in CDR Based High Speed Designs
Frank Lambrecht, Qi Lin, Sam Chang, DanOh, Chuck Yuan, and Vladimir Stojanovic
Rambus Inc.
4438 El Camino Real, Los Altos, CA 94022
Phone: (650)-947-5326, FAX: (650)-947-5001, frankli rambus.com
Abstract-Accurate
variations
required
is
analysis
for
timing and voltage margin at a target
system
high
production
volume
of high
techniques
signaling
advanced
systems.
speed
such
bit
This
in
error rate across
turn
transmitter
as
requires
a
process, voltage,
statistical
equalization
and
and
simulation
receiver
temperature
framework to
feedback.
decision
links, one must also carefully model the clock-data recovery circuits
system voltage and timing
margin. In this paper, we first present a stochastic simulation
We then compare the simulation results based on
methodology for
modeling
circuits.
quadrature sampling based timing recovery
lab
model. Finally, we correlate the simulation
measurements to validate the proposed approach.
telecommunication
Furthermore,
(CDR)
impact
networking serial
on
modeling
simple
method,
results
to
I. INTRODUCTION
T
prediction
successfully prediction
advanced
circuit
of
rate
components
completely
voltage
becoming
is
timing
speeds.
example,
For
Within
this
complex
including
requires the
these
closed.
increasingly
figure
receiver
processing
Due
the
to
see
the resultant
architecture
effects
oltage Marginh at Different ODR
that
requires
-0
Fig.
channel
links
at
overall
150
statistical
includes
signal
multi-gigahertz
signaling
inter-symbol interference,
eye
adaptive
integrity
with
where the
and without
decision
analysis
to
bit
the
eye
error
diagram at
the
equalization
more
The
including
rate
considering
feedback
include
rates.
data
architecture
is
shown
receiver
[1].
behavioral
This
circuit
system performance.
Erro| Vs Voltage Margin at Differn t OD ROffset
s Pr obabiIity of r
RO f
E
-2
100
~~~~~~~~~~~
2100
large
speed
of the
1
we
modeling than was needed in the past in order to accurately predict
Probabiity of Eror vs.g
for high
consideration
a statistical eye diagram is shown in Figure
ni
receiver
important
complete
~~~~~~~~~~~~~~1501~~~00
22
0
100
1E 1-5 0
Received
I
eye with and without RX behavioral model post
processing
-10
Traditionally, the circuit effects have been taken into account in channel voltage and
timing budget as a separate budget
item. Simplified
driver models simulated with passive network models have
been used to characterize the channel
performance. Such an approach is no longer acceptable
for analysis of high-speed designs. As a result, accurate
of
system
speed links requires that we include increasingly more detailed
edct yst simulation
m p rfrma high
ce
models
of
these
ase and
architectural
blocks
capture the voltage
to
onthesim
fully
effects. abThese
timinglatonto
eas details
rem nt include discrete resolution such as
quantization from transmitter
equalization, decision feedback and feed forward equalization
and modeling of the algorithms used to determine
coefficients. We need to model the effects of recovered clock
sample
point
variation
and other sources of circuit based variation
inperformance. Typical clock recovery circuits are
to
responsive
various
contributors
to edge timing movement which include
data
variations, inter-symbol interference characteristics of the channel, and random
noise events on the channel. In
addition, filtering is typically applied to the phase update decision. These
recovered
effects
clocking
must be considered within a
broader framework for analysis of I/O
an
subsystem.
of
Examples
such
simulation
toolsets
are
described in [2-5]. For the
simulations presented here we use the Rambus developed LinkLab
LinkLab's CDR modeling methodology in the next section. We then signal integrity simulation toolset. We introduce the
show that simplified assumptions about clock timing for
recovered clock systems do not accurately predict system performance based on the simulation to lab measurement correlation.
IO
orrla10n
coefficients
pattern
1-4244-0668-41061$20.00 ©2006 IEEE17
171
186
II. MODELING METHODOLOGY
The LinkLab toolset statistically simulates high speed links in the time domain. A basic flowchart for such a simulation
methodology is shown in Fig. 2 below. The transmitter model captures the driver including equalizer covering different
equalization algorithms and quantization error as well as power constraints. The channel block integrates all the passive circuit
components including motherboard trace and device models such as Ri/Ci, package and connectors. The determination of ISI
probability density function can be obtained as in [6], when generalized to the data pattern set under consideration. After passing
receiver linear equalizer, the signal is processed by analog decision feedback equalizer (DFE). It selects from the various
schemes of DFE based on the circuit design under consideration. The last step is to feed the statistical description of the received
waveform into the CDR with the random and deterministic jitter components. Additional effects are also modeled including
transmit and receive PLL phase variations due to noise effects and imperfect reference clock, termination thermal noise and
other variation sources. The system voltage/timing margin calculation computes the bathtubs of bit error rate (BER) vs time and
voltage offsets as well as a statistical eye diagram.
Input Pulse
|
Tx Equalizer
Channel SParameters
TX Jitter
-N
ISI Probability Density Function
DFE[1
System Voltage/Timing Margin
|Crosstalk and RX Jitter
Fig. 2 Simulation flowchart
Within the flowchart of Fig. 2 we will be focusing on impact of accurate CDR behavioral modeling. Recovered clock phase
is most impacted by the timing and voltage noise distorted waveforms input to the phase recovery circuit. The major contributors
to timing and voltage noise can be broken in three sets: i) due to channel, package, and parasitic inter-symbol interference, ii)
effective receiver referenced voltage noise distribution from transmitter and receiver jitter from thermal, power supply and
reference clock noise sources, and iii) recovered clock sample point distribution. To these we also add the behavioral effects of
transmit and receive signal processing circuits which include both corrective and additional noise sources. Total received signal
error can be described by Eq. (1), where xjISI, xjitTx,XjitRx represent interference, and receiver voltage noise from transmitter and
receiver jitter, respectively. As seen in Fig. 3, data pulses are labeled as bk, edge jitter values asSk, channel pulse response
samples asPk, and channel impulse response samples as hk. Indexes sbS and sbE mark the beginning and end of the channel
pulse/impulse response.
X +
7i
Xk =
sE
Xk
X
xJ.ItTx
k
k
bk
=
+
xitRX
bk-n p,
n=-sbS
sbE
>
Z kn
b
n=-sbS
Ek-n+l
(hn-I
X(n
sbE
k
(1it)
bE
E
n= -sbS
;(a)
kn
(hn
-
hn lgY
Tn)kX
£k
n-
I
bk
T-1 (k+l)T >(b)
b
T
+ k + I)T
TX ~
~
~ ~ bT
bkkk
Fig. 3 Jittered pulse decomposition. A symbol transmitted with jitter is converted to
symbol's widths (b) are equaltoEkTX
a
symbol with
k+]TX.
no
jitter (a), plus
a
noise term where the noise-
and
We apply superposition principles to add the effects of residual ISI in generating an effective statistical eye description. From
these resultant distributions as sampled by the clock recovery circuits we are able to generate stochastic descriptions of the
received clock timing. This is shown in Fig 4. This variation in receiver timing is then used to condition the incoming data eye
distributions to result in final bit error rate and margin predictions.
172
.HS
CL=a3ble.~ PSahdoretCMVA->l m,
P-UP
n 0.8X-
p-dn
p-no-valid
transitions
p-earlIy'
0.4
0
\ _,
p-late
%
I
p-hold
0.20
-Pholdi
9~ s _J '- -28
Pdnli
Accumulate-resz
filter, length 4
0.6-
187
50
100
150
200
250
Phase count
Fig. 4 (left) The raw input probabilities (p-early, p-late, p-no-valid transition) are converted by a filter to state transition probabilities (p-up, p-dn, phold) for each possible phase position; (right) First-order Markov chain phase-state model. Each state represents a different phase position, and the arcs
are the probability of transition, given that position.
This simulation framework can be extended to include additional design features for modeling and optimization. As in [7]
where we model the impact of low power design techniques on the bit error rate of high speed links through delay variation
modeling and do sample trade-offs for a 15 Gbps link over 8" of FR4. These methods enable tradeoffs in speed, equalization
approach, and power to be made while predicting the bit error rate of the link.
III. RESULTS AND DISCUSSION
For the simulation and lab correlation in this paper we use 4-tap differential transmit equalization and receiver architecture
shown in Figure 5. A random data pattern was simulated, where each bit is assumed to be independent of the previous bit. For
the lab analysis we used a 2 31 PRBS data patterns. Given the limited time history of residual ISI for a passive link, this is a
valid comparison.
as
t
PLL
f
Eqtializer Driverl
Phs
oto
A i 4hase Detector
Fig. 5 I/O architecture
The 30" backplane channel used in this analysis is shown in Fig. 6. The backplane and paddle card designs are manufactured in
a 14 layer FR4 PCB. The backplane trace used was located on an upper layer leaving approximately a 100 mil via stub on this
net. On the paddle card a 60 mil via stub remained on the net. The connector pinset chosen used the longest length (GH on
HMZD connector). This length and transfer characteristic is typical for a long backplane serial link application, where the
channel has -18dB insertion loss at 2.5 GHz. For this channel to operate at 5 Gbps, one must use advanced signaling to recover
the data at the receiver.
I Hi=-L16
Short SMVA
_=r
Cable~
~
~ ~ ~ ~~~~~~~~~Cbl
PaddleCard
[dB] (Vi ctim=n
blue,
FEXT=-
green,
retd)
NEXT=
1O
_20 -
1
L=3"
9
---20
-T
T
2
3
4
Connector
HMZD
Connector
0
.GF
1
4
5
Fig. 6 Typical high speed backplane channel and its transfer function
Lab and LinkLab simulation results are shown in Fig. 7 below. In addition to the 30" backplane channel an additional result
is shown for a shorter 16" backplane trace. This (+/- mV) voltage margin is defined to be at the bit error rate of 10A-15. This can
173
188
also be thought of as the positive or negative differential offset that can be applied to the receiver required to increase the bit
error rate to the 10- 15 level.
250
16"- Sim
200
30"- Sim
16"- Lab
30"- Lab
-
150
E
100
50
2.9
3.4
3.9
4.4
Data Rate (Gbs)
4.9
5.4
5.9
Fig. 7 Lab vs. simulation comparison
Fig. 8 shows the system voltage margin result with additional simulation results using a receiver model which samples data
in quadrature rather than using the more complete CDR behavioral model. As can be seen in this plot, the difference between
including and not including the CDR model has an effect of (+/-) 5-19 mV or 10-38 mV peak-peak for these speeds and channel.
We can see that this difference is not constant across frequency and also varies with channel choice, a simplified single offset
term would lead to overly pessimistic simulation results for most channels.
160
0
Quadrature-
140
. .
BER Vs
additional ItN offset, 4A4 Gbps
With CDR Model
~~~~~Lab Data
120
E
-m
80
w
0With CDR
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
20
Lab Data
3
3.5
4
4.5
Data Rate (Gbps)
5
5.5-5
-50
0
50
100
150
additional voftd offset [mVJ
Quadrature Timing Model, and Lab Data
-100
Fig. 8 (left) Margin Results vs Data Rate using Stochastic CDR model, using Simplified
Voltage Bathtub plot for same 3 data sets at 4.4Gbps frequency point.
(right) Sample
As we have seen, the signal integrity analysis of high speed links is becoming more challenging. Additional complexity in
the behavioral modeling of JO circuits is required. Within this new framework is a strong interdependence between channel and
circuit design. This paper describes a general approach to such simulations and describes behavioral simulation of a clock data
recovery block. We show the accuracy benefits of such modeling for a sample long backplane channel at speeds of 3.4 -5.4
Gbps.
RiEFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
J. Zerbe, Qi Lin, V. Stajonovic, A. Ho, R. Kollipara, F. Lambrecht, C. Werner, "Comparison of adaptive and non-adaptive equalization
methods in high-performance backplanes", DesignCon '05
V. Stojanovic, M. Horowitz, "Modeling and analysis of high-speed links", CICC '03, pp.589-94
V. Stojanovic, A. Amirkhany, M.A. Horowitz, "Optimal linear precoding with theoretical and practical data rates in high-speed serial-link
backplane communication", ICC '04, pp.2799-2806
B.K. Casper, M. Haycock, R. Mooney, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes", IEEE
on VLS,I Circuits, 2002
A. Sanders, M. Resso, J. D'Ambrosia, "Channel compliance testing utilizing novel statistical eye methodology", DesignCon '04
D. Oh, "Multiple Edge Responses for Fast and Accurate System Simulations", IEEE Electrical Performance of Electronic Packages
Conference '06, submitted for publication.
H. Hatamkhani, F. Lambrecht, V. Stojanovic, C.K. Yang "Power Centric Design of High-Speed I/Os" 43rd Design Automation
Conference, 2006.Paper 50.4
~Symposium
174