Download STEVAL-PSQ001V1

STEVAL-PSQ001V1
Power management for CPU, FPGA and memory
based on the PM6680A
Data Brief
Features
■
Input: 5 - 36 VDC, surge protection
■
Output voltages:
– Output1 (Vcore) selectable from: 0.9, 1.0,
1.2, 1.5, 1.8 or 2.5 V, 4 A continuously (6 A
peak), tolerance: 3%
– Output2 (Vi/o) selectable from: 1.0, 1.2, 1.5,
1.8, 2.5 V or 3.3 V, 2 A continuously
(3 A peak), tolerance: 3%
– Output3 Vsys: 3.3 V 0.4 A (0.8 A peak),
tolerance: 4%
– Output3 Vaux: 2.5 V, 0.4 A, tolerance: 2%
■
Analog 5: 5 V, 0.8 A, tolerance: 4%
■
Analog 3.3 V: 3.3 V, 0.15 A, tolerance: 2%
STEVAL-PSQ001V1
Description
reset. This limit is typically ± 3 or 5 %. On the
other hand, digital device consumption can
change very fast (approx. several amps in several
hundred nanoseconds). The power supply must
be capable of reacting very quickly with a
minimum of over/under voltage, especially in
cases where very low voltage output is required.
There is additional stress placed on power
supplies in digital applications for industrial use.
The industrial standard bus is 24 V, but this
voltage fluctuates and the maximum required
input voltage level can be up to 36 V. Additional
surge protection is also mandatory for power
supply input in industrial applications. The
purpose of this evaluation board is to address all
of required parameters outlined above. This
means satisfying industrial input requirements
(operating voltage of up to 36 V) and generating
several output voltages for middle power
applications (up to several amps). The main
output voltage level can be set easily.
The main purpose of this evaluation board is to
show basic principles used for design of the power
supply and to give users a working prototype for
testing and daily use. The trend in recent years in
the supply of MCUs, CPUs, memories, FPGAs
etc. is to reduce the supply voltage, increase
supply current and provide various voltage levels
for different devices in one platform. A typical
example of this is the FPGA. FPGAs contain core
parts which operate with low level voltage,
interface parts placed between the core and the
output, system parts, etc. It is important to note
that each family of parts has a slightly different
voltage level and the trend is toward decreasing
voltage for each new family. The lowest operating
voltage currently is 1 V, and this can be expected
to drop to 0.9 V or 0.8 V in the near future. The
situation is similar with other parts of digital
solutions. Typically, the main CPU, memory, and
interfaces require different supply voltage levels.
Low operating voltage also bring another
challenge - transient. Digital devices are typically
sensitive to voltage level. If voltage drops below or
crosses over established limits, the device is
February 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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GND io
S32
S33
FB1
S8
0.9V
S9
1V
R107
9k1
R101 1k
Vio 0.9 - 2.5V/2A
S34
S35
Input
R108
820k
R102
R10
2 2k
S10
1.2V
R103 3k
S11
1.5V
R1043k
R10
3k
S12
1.8V
R105 R106
7k5 110k
C22
330u/6.3V
C18
10u/50V
Vin
R11
300R
C21
100pF
C20
560pF
L3 4.7uH/3A
C35
D8
STPS2L40
R40
R4
0 10R
100n
R39
R3
9 10R
D1
SMAJ33A
1
8
7
3
6
5
4V7
R24 10R
R23 10R
R2
VLDO
R28
R2
8 10k
2
4
D10
C36
100pF
R29
100k
Vin
VLDO
STS4DNF60
Q1
C1
47uF/50V
D3
R34 10k
R3
R31 10k
R3
R35
51k
S3
CH2 EN/SUS
1
R30
R3
0 0R
5
7
27
2
8
17
12
13
11
10
9
R25
10R
U5
PM6680
PGOOD2
R10 1k2
C19
100n
C15
470n
VLDO
C9
220p
C3
220p
C31
220n
R37
R3
7 47R
C8
4.7u/35V
C2
4.7u/35V
C14
4.7u/10V
36V
D5
L5 10uH/1A
36V
BOOT2
SHDN
FB2
PGOOD2
COMP2
OUT2
V5SW
CSENSE2
LGATE2
PHASE2
HGATE2
3
S4
R36
51k
U1 L5970AD
Vcc
COMP
COMP
Vcc
U3 L5970AD
5k6
R42
LGATE1
PHASE1
HGATE1
BOOT1
D7
OUT1
PGND
FB1
SGND1
SGND2
PGOOD1
COMP1
C30
100n
SKIP mode
S7
R26
10R
C17
100n
28
1
16
26
30
29
14
VLDO
20 R19 1k2
15
21
22
23
BAW56/SOT
CSENSE1
S6
5k6
R41
C16
3.3u/35V
R9
3R3
C10
22n
R5
10k
4
8
R1
4k7
C4
22n
Vin
CH1 EN/SUS
S5
8
4
SYNC
SY
2
1
Vin
19
Vin
SYNC
SY
2
GND
GN
D
7
FB
OUT
S1
1
5
Vin
D4
STPS2L40
1
5
R33
0R
R32 10k
VLDO
Q3
STS7NF60L
R22
R2
2 10R
R21
R2
1 10R
STS7NF60L
C25
100n
Q2
Vin
D6
STPS2L40
Vsys EN
S2
FB
OUT
Vanalog EN
INH
3
VREF
6
VREF
6
GND
7
INH
3
2
31
EN1
25
2
EN2
4
18
LDO5
O5
R7
240k
R3
20k
C27
100pF
C26
560pF
R20
300R
1
VIN
INH
4
C28
330u/6.3V
C29
330u/6.3V
C24
10u/50V
1n
1n
R206 R205
110k 7k5
C33
C32
R204 3k
R20
S17
2.5V
1
C13
10u/4V
C7
10u/6V
RST
R203 3k
S16
1.8V
MR
RSTIN
Vcc2
Vcc1
R208
6k8
R207
2k2
R2022k
R20
2k
S15
1.5V
1
U6
STM6719TEWB6F
PGOOD2
3
4
5
6
VOUT
OUT
U4
KF25_SOIC8
GND
BYPASS
SHDN
IN
VLDO
8
5
2
3
U2 LK112_33
Vaux
C12
100n
C6
100n
5
FB2R
C11
100u/6V
C5
47uF/10V
100n
R38 10R
R38
3.3uH/6A L4
C34
C23
10u/50V
Vin
R8
10k
R4
5k6
R27 10R
R27
STPS2L40
D9
D6A
STPS1L40M
R6
18k
L2 15uH/1.5A
D4A
STPS1L40M
R2
120k
L1 15uH/1.5A
GND
GND
GND
GN
GN
GND
2
3
6
7
J16
3
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1
NC
Vcc
VREF
32
SKIP
SK
IP
24
FSEL
FSE
L
3
Vss
S21
R209
110k
GND
R201
R20
1 1k
S14
1.2V
STPS2L40
J15
J1
Reset GND
J14 Reset
S31
S30
S29
S28
Vcore GND
FB2R
FB2
Vcore 0.9 - 2.5V/4A
S24
S25
S26
S27
S13
1V
S23
Vaux 2.5V/400mA
Vsys 3.3V/400mA
S22
Vsys
GND Analog
S20
3.3V/150mA
Vaux
D11
S18
5V/400mA
S19
V5V
Figure 1.
2
1
6
Circuit schematic
STEVAL-PSQ001V1
Circuit schematic
Schematic
STEVAL-PSQ001V1
2
Revision history
Revision history
Table 1.
Document revision history
Date
Revision
18-Feb-2008
1
Changes
Initial release.
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STEVAL-PSQ001V1
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