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STL7DN6LF3 Dual N-channel 60 V, 35 mΩ typ., 6.5 A STripFET™ III Power MOSFET in PowerFLAT™ 5x6 double island package Datasheet — production data Features Order code VDSS RDS(on) max ID STL7DN6LF3 60 V < 43 mΩ 6.5 A (1) 1. The value is rated according to Rthj-pcb 1 2 ■ Logic level VGS(th) ■ 175 °C junction temperature ■ 100% avalanche rated 3 4 PowerFLAT™ 5x6 double island Applications ■ Switching applications ■ Automotive Figure 1. Internal schematic diagram Description This device is a dual N-channel enhancement mode Power MOSFET produced using STMicroelectronics’ STripFET™ III technology, which is specifically designed to minimize onresistance and gate charge to provide superior switching performance. Top view Table 1. Device summary Order code Marking Package Packaging STL7DN6LF3 7DN6LF3 PowerFLAT™ 5x6 double island Tape and reel June 2012 Doc ID 023010 Rev 3 This is information on a product in full production. www.bdtic.com/ST 1/14 www.st.com 14 Contents STL7DN6LF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 .............................................. 8 Doc ID 023010 Rev 3 www.bdtic.com/ST STL7DN6LF3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V ID(1),(2) Drain current (continuous) at TC = 25 °C 20 A ID Drain current (continuous) at TC = 100 °C 16 A ID (4) Drain current (continuous) at Tpcb = 25 °C 6.5 A ID (4) Drain current (continuous) at Tpcb=100 °C 4.6 A Drain current (pulsed) 26 A Total dissipation at TC = 25°C 52 W Total dissipation at Tpcb = 25°C 4.3 W Not-repetitive avalanche current 6.5 A Single pulse avalanche energy 190 mJ Operating junction temperature Storage temperature -55 to 175 °C IDM (3),(4) PTOT (4) PTOT IAV EAS (5) TJ Tstg 1. Specified by design. Not subject to production test. 2. Current is limited by bonding, with an RthJC = 2.9 °C/W the chip is able to carry 22 A at 25 °C. 3. Pulse width limited by safe operating area 4. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 5. Starting TJ= 25 °C, ID= 8 A, VDD= 25 V, per channel, 100% tested. Table 3. Thermal resistance Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.9 °C/W Thermal resistance junction-pcb 35 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Doc ID 023010 Rev 3 www.bdtic.com/ST 3/14 Electrical characteristics 2 STL7DN6LF3 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. Symbol Parameter Test conditions Drain-source breakdown voltage (VGS= 0) ID = 250 µA IDSS Zero gate voltage drain current (VGS = 0) VDS = 60 V IGSS Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS= 10 V, ID= 3 A VGS= 5 V, ID= 3 A V(BR)DSS Table 5. Symbol Min. Typ. Max. 60 Unit V 1 µA ±100 nA 3 V 35 48 43 60 mΩ mΩ Min. Typ. Max. Unit 1 Dynamic Parameter Test conditions Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =25 V, f=1 MHz, VGS=0 - 432 93 10.5 - pF pF pF Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=30 V, ID = 6.5 A VGS =10 V Figure 13 - 8.8 2.1 1.9 - nC nC nC RG Intrinsic gate resistance f=1 MHz open drain - 6.3 - Ω Table 6. Symbol td(on) tr td(off) tf 4/14 On/off states Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=TBD, ID= 3 A, RG=4.7 Ω, VGS=10 V Figure 12 Min. Typ. - TBD TBD TBD TBD Doc ID 023010 Rev 3 www.bdtic.com/ST Max. Unit - ns ns ns ns STL7DN6LF3 Electrical characteristics Table 7. Symbol Parameter Test conditions Min Typ. Max Unit Source-drain current - 6.5 A (1) Source-drain current (pulsed) - 26 A (2) Forward on voltage ISD = 6.5 A, VGS=0 - 1.3 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 6.5 A, di/dt = 100 A/µs, VDD=6.5 V, Tj=150 °C - ISD ISDM VSD Source drain diode trr Qrr IRRM 24 23.3 1.94 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration= 300 µs, duty cycle 1.5% Doc ID 023010 Rev 3 www.bdtic.com/ST 5/14 Electrical characteristics STL7DN6LF3 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM13023v1 ID (A) Zth_AM13007v1 K s hi Tj=175°C Tc=25°C Single pulse is a re a n) o S( 0.2 D 0.1 R t in ax n io y m t b ra pe ed O imit L 10 δ=0.5 -1 10 0.05 0.02 0.01 1 10ms -2 10 100ms Single pulse 1s 0.1 0.1 Figure 4. 10 1 VDS(V) Output characteristics 10 -4 VGS=10V 25 -2 -3 10 10 10 Figure 5. AM13024v1 ID (A) -3 -1 0 10 10 1 10 tp (s) Transfer characteristics AM13025v1 ID (A) VDS=5V 25 5V 20 20 4V 15 15 10 10 5 5 0 0 Figure 6. 1 2 3 4 VDS(V) Normalized VDS vs temperature AM13010v1 VDS (norm) ID=1mA Figure 7. 1.06 35.2 1.02 35.0 0.98 34.8 0.94 34.6 34.4 25 75 125 2 TJ(°C) 3 4 VGS(V) AM13026v1 RDS(on) (mΩ) 35.4 -25 1 Static drain-source on-resistance 1.10 0.90 -75 6/14 0 0 2 VGS=10V 3 4 Doc ID 023010 Rev 3 www.bdtic.com/ST 5 ID(A) STL7DN6LF3 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM13027v1 VGS (V) Capacitance variations AM13028v1 C (pF) VDD=30V ID=6.5A 10 Ciss 8 100 6 Coss 4 2 0 0 2 4 8 6 10 10 Figure 10. Normalized gate threshold voltage vs temperature AM13014v1 VGS(th) ID=250µA (norm) 0 Qg(nC) 10 20 40 30 50 Crss VDS(V) Figure 11. Normalized on-resistance vs temperature AM13015v1 RDS(on) ID=4A VGS=10V (norm) 2.0 1.2 1.6 1.0 1.2 0.8 0.8 0.6 0.4 -75 0.4 0 -25 25 75 125 TJ(°C) -75 -25 25 75 Doc ID 023010 Rev 3 www.bdtic.com/ST 125 TJ(°C) 7/14 Test circuits 3 STL7DN6LF3 Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 16. Unclamped inductive waveform AM01471v1 Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDS VDD 90% VGS AM01472v1 8/14 0 10% Doc ID 023010 Rev 3 www.bdtic.com/ST AM01473v1 STL7DN6LF3 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 023010 Rev 3 www.bdtic.com/ST 9/14 Package mechanical data Table 8. STL7DN6LF3 PowerFLAT™ 5x6 double island (ribbon) type B mechanical data Dimensions (mm) Ref. Min. Typ. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 1.68 1.88 E2 3.50 3.70 D3 1.68 1.88 E3 3.50 3.70 E4 0.55 0.75 e 10/14 Max. 1.27 L 0.60 0.80 K 1.275 1.575 Doc ID 023010 Rev 3 www.bdtic.com/ST STL7DN6LF3 Package mechanical data Figure 18. PowerFLAT™ 5x6 double island (ribbon) type B drawing Bottom view Side view Top view 8256945_Rev.D_ribbon Doc ID 023010 Rev 3 www.bdtic.com/ST 11/14 Package mechanical data STL7DN6LF3 Figure 19. PowerFLAT™ 5x6 double island (ribbon) recommended footprint (dimensions are in mm) Footprint_ribbon 12/14 Doc ID 023010 Rev 3 www.bdtic.com/ST STL7DN6LF3 5 Revision history Revision history Table 9. Document revision history Date Revision Changes 28-Mar-2012 1 First release. 19-Jun-2012 2 Section 2.1: Electrical characteristics (curves) has been added. Updated Section 4: Package mechanical data and tile on the coverpage. 26-Jun-2012 3 Document status promoted from preliminary to production data. Doc ID 023010 Rev 3 www.bdtic.com/ST 13/14 STL7DN6LF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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