Download STL52N25M5

STL52N25M5
N-channel 250 V, 0.064 Ω, 28 A, PowerFLAT™ (5x6)
MDmesh™ V Power MOSFET
Features
Type
VDSS
RDS(on)
max.
ID(1)
STL52N25M5
250 V
< 0.076 Ω
28 A
1. This value is rated according Rthj-case.
■
Amongst the best RDS(on)* area
■
Very low profile package (1 mm max.)
■
Excellent switching performance
■
High dv/dt capability
■
100% avalanche tested
PowerFLAT™ (5x6)
Application
Figure 1.
Switching applications
Internal schematic diagram
Description
This device is N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL52N25M5
52N25M5
PowerFLAT™ (5x6)
Tape and reel
April 2011
Doc ID 17819 Rev 2
1/13
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13
Contents
STL52N25M5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
.............................................. 8
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STL52N25M5
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
VGS
Parameter
Value
Unit
Gate- source voltage
25
V
ID
(1)
Drain current (continuous) at TC = 25 °C
28
A
ID
(1)
Drain current (continuous) at TC = 100 °C
18
A
112
A
IDM (1),(2) Drain current (pulsed)
ID
(3)
Drain current (continuous) at TC = 25 °C
4.2
A
ID
(3)
Drain current (continuous) at TC = 100 °C
2.6
A
Drain current (pulsed)
16.8
A
PTOT (1)
Total dissipation at TC = 25 °C
110
W
(3)
Total dissipation at TC = 25 °C
2.5
W
IAR
Avalanche current, repetitive or not-repetitive
(pulse width limited by TJ max)
10
A
EAS
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAR, VDD = 50 V)
230
mJ
Peak diode recovery voltage slope
15
V/ns
- 55 to 150
°C
Value
Unit
IDM
(2),(3)
PTOT
dv/dt(4)
Operating junction temperature
Storage temperature
TJ
Tstg
1. This value is rated according Rthj-case.
2. Pulse width limited by safe operating area.
3. This value is rated according Rthj-a.
4. ISD ≤ 28 A, di/dt ≤ 400 A/µs, VDD = 150 V, VPeak < V(BR)DSS.
Table 3.
Symbol
Thermal data
Parameter
Rthj-case
Thermal resistance junction-case max
1.14
°C/W
(1)
Thermal resistance junction-amb max
50
°C/W
Maximum lead temperature for soldering purpose
300
°C/W
Rthj-a
TJ
1. When mounted on FR-4 board of 1inch², 2oz Cu
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Electrical characteristics
2
STL52N25M5
Electrical characteristics
(TC = 25 °C unless otherwise specified).
Table 4.
Symbol
V(BR)DSS
On /off states
Parameter
Test conditions
Drain-source
breakdown voltage
ID = 1 mA, VGS = 0
Min.
Typ.
Max.
Unit
250
V
IDSS
VDS = Max rating
Zero gate voltage
drain current (VGS = 0) VDS = Max rating, TC=125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
100
nA
4
5
V
0.064
0.076
Ω
Min.
Typ.
Max.
Unit
VGS = ± 25 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 100 µA
RDS(on)
Static drain-source onVGS = 10 V, ID = 13 A
resistance
Table 5.
Symbol
3
Dynamic
Parameter
Test conditions
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 50 V, f = 1 MHz,
VGS = 0
-
1770
110
17
-
pF
pF
pF
Co(er)(1)
Equivalent output
capacitance energy
related
VGS = 0, VDS = 0 to 80%
V(BR)DSS
-
93
-
pF
Co(tr)(2)
Equivalent output
capacitance time
related
VGS = 0, VDS = 0 to 80%
V(BR)DSS
-
178
-
pF
Rg
Gate input resistance
f=1 MHz open drain
-
2.5
-
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 200 V, ID = 28 A,
VGS = 10 V
(see Figure 14)
-
47
10
24
-
nC
nC
nC
1. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0
to 80% VDSS.
2. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0
to 80% VDSS.
4/13
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STL52N25M5
Electrical characteristics
Table 6.
Switching times
Symbol
Parameter
td(V)
tr(V)
tf(i)
tc(off)
Test conditions
Voltage delay time
Voltage rise time
Current fall time
Crossing time
Table 7.
Symbol
VDD = 125 V, ID = 14 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13)
(see Figure 18)
Parameter
Test conditions
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
IRRM
trr
Qrr
IRRM
Typ.
-
40
18
64
82
Max Unit
-
ns
ns
ns
ns
Source drain diode
ISD
ISDM (1)
trr
Qrr
Min.
Min. Typ. Max
Unit
-
28
112
A
A
ISD = 28 A, VGS = 0
-
1.6
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 28 A, di/dt = 100 A/µs
VDD= 60 V, TJ = 25 °C
(see Figure 15)
-
168
1.2
14.5
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 28 A, di/dt = 100 A/µs
VDD= 60 V TJ = 150 °C
(see Figure 15)
-
196
1.7
17
ns
µC
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
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Electrical characteristics
STL52N25M5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
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ON
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RA
ITE TIO
D N I
BY N
M TH I
A X SA
2 RE
A
IS
—S
—S
,I
M
/
PE
MS
4J #
4C #
MS
3INGLE
PULSE
Figure 4.
6$36
Output characteristics
!-V
)$
!
!-V
)$
!
6'36
6
6$36
6
6
Figure 6.
6$36
Gate charge vs gate-source voltage Figure 7.
!-V
6'3
6
6'3
6$$6
)$!
6'36
Static drain-source on resistance
!-V
2$3ON
/HM
6'36
6$3
6/13
1GN#
Doc ID 17819 Rev 2
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)$!
STL52N25M5
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
!-V
#
P&
#ISS
Output capacitance stored energy
!-V
%OSS
—*
#OSS
#RSS
Figure 10. Normalized gate threshold voltage
vs temperature
!-V
6'3TH
6$36
NORM
6$36
Figure 11. Normalized on resistance vs
temperature
!-V
2$3ON
NORM
)$—!
)$!
4* #
4* #
Figure 12. Normalized BVDSS vs temperature
!-V
"6$33
NORM
)$M!
4* #
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Test circuits
3
STL52N25M5
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
VDD
2200
µF
3.3
µF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
Inductive Load Turn - off
V(BR)DSS
Id
VD
90%Vds
90%Id
td(v)
IDM
Vgs
90%Vgs
on
ID
))
Vgs(I(t))
VDD
VDD
10%Id
10%Vds
Vds
tr(v)
AM01472v1
8/13
tf(i)
tc(off)
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AM05540v1
STL52N25M5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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9/13
Package mechanical data
Table 8.
STL52N25M5
PowerFLAT™ (5x6) mechanical data
mm
Dim.
Min.
Typ.
Max.
0.80
0.83
0.93
A1
0.02
0.05
A3
0.20
A
b
0.35
0.40
D
5.00
D1
4.75
D2
4.15
4.20
E
6.00
E1
5.75
4.25
E2
3.43
3.48
3.53
E4
2.58
2.63
2.68
e
L
1.27
0.70
0.80
Figure 19. PowerFLAT™ (5x6) drawing
10/13
0.47
Doc ID 17819 Rev 2
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0.90
STL52N25M5
Package mechanical data
Figure 20. Recommended footprint
AM08614v1
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11/13
Revision history
5
STL52N25M5
Revision history
Table 9.
12/13
Document revision history
Date
Revision
Changes
02-Aug-2010
1
First release.
26-Apr-2011
2
Updated RDS(on) value, and figures 2, 5, 7, 10, 11 and 12.
Updated Section 4.
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STL52N25M5
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