Download STL45N65M5

STL45N65M5
N-channel 650 V, 0.075 Ω typ., 22.5 A MDmesh™ V
Power MOSFET in PowerFLAT™ 8x8 HV package
Datasheet — preliminary data
Features
Order code
VDSS @
TJmax
RDS(on)
max
ID
STL45N65M5
710 V
< 0.086 Ω
22.5 A(1)
3
3
3
'
$
1. The value is rated according to Rthj-case and limited by
package.
■
100% avalanche tested
■
Low input capacitance and gate charge
■
Low gate input resistance
Applications
■
"OTTOMVIEW
0OWER&,!4˜X(6
Figure 1.
Internal schematic diagram
Switching applications
$
Description
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Table 1.
'
3
!-V
Device summary
Order code
Marking
Package
Packaging
STL45N65M5
45N65M5
PowerFLAT™ 8x8 HV
Tape and reel
September 2012
Doc ID 023354 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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Contents
STL45N65M5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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STL45N65M5
1
Electrical ratings
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
Drain-source voltage
650
V
VGS
Gate-source voltage
± 25
V
Drain current (continuous) at TC = 25 °C
22.5
A
ID
(1)
ID (1)
Drain current (continuous) at TC = 100 °C
18
A
(1),(2)
Drain current (pulsed)
90
A
ID
(3)
Drain current (continuous) at Tamb = 25 °C
3.8
A
ID
(3)
Drain current (continuous) at Tamb = 100 °C
2.4
A
Total dissipation at Tamb = 25 °C
2.8
W
Total dissipation at TC = 25 °C
160
W
IDM
PTOT (3)
PTOT
(1)
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
9
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
810
mJ
Peak diode recovery voltage slope
15
V/ns
- 55 to 150
°C
150
°C
Value
Unit
0.78
°C/W
45
°C/W
dv/dt (4)
Tstg
Storage temperature
Tj
Max. operating junction temperature
1. The value is rated according to Rthj-case and limited by package.
2. Pulse width limited by safe operating area.
3. When mounted on FR-4 board of inch², 2oz Cu.
4. ISD ≤ 22.5 A, di/dt ≤ 400 A/µs, VDD = 400 V, VDS(peak) < V(BR)DSS.
Table 3.
Symbol
Rthj-case
Rthj-amb(1)
Thermal data
Parameter
Thermal resistance junction-case max
Thermal resistance junction-ambient max
1. When mounted on FR-4 board of inch², 2oz Cu.
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Electrical characteristics
2
STL45N65M5
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
On /off states
Parameter
Test conditions
Drain-source
breakdown voltage
ID = 1 mA, VGS = 0
Min.
Typ.
Max.
Unit
650
V
IDSS
Zero gate voltage
VDS = 650 V
drain current (VGS = 0) VDS = 650 V, TC=125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
±100
nA
4
5
V
0.075
0.086
Ω
Min.
Typ.
Max.
Unit
-
3470
82
7
-
pF
pF
pF
-
79
-
pF
-
280
-
pF
-
2
-
Ω
-
82
18.5
35
-
nC
nC
nC
VGS = ± 25 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source onVGS = 10 V, ID = 14.5 A
resistance
Table 5.
Symbol
Dynamic
Parameter
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
Co(er)(1)
Equivalent output
capacitance energy
related
Co(tr)(2)
3
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0
VGS = 0,
VDS = 0 to 80% V(BR)DSS
Equivalent output
capacitance time
related
RG
Intrinsic gate
resistance
f = 1 MHz open drain
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 520 V, ID = 17.5 A,
VGS = 10 V
(see Figure 16)
1. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss
when VDS increases from 0 to 80% VDSS
2. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when
VDS increases from 0 to 80% VDSS
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STL45N65M5
Electrical characteristics
Table 6.
Symbol
td (v)
tr (v)
tf (i)
tc(off)
Switching times
Parameter
Test conditions
Voltage delay time
Voltage rise time
Current fall time
Crossing time
Table 7.
Symbol
VDD = 400 V, ID = 22.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 20)
Parameter
Test conditions
Source-drain current
ISDM (1),(2) Source-drain current (pulsed)
trr
Qrr
IRRM
trr
Qrr
IRRM
Typ.
-
79.5
11
9.3
16
Min.
Typ.
Max. Unit
-
ns
ns
ns
ns
Source drain diode
ISD (1)
VSD (3)
Min.
Max. Unit
-
22.5
90
A
A
1.5
V
Forward on voltage
ISD = 22.5 A, VGS = 0
-
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 22.5 A, di/dt= 100 A/µs
VDD = 100 V (see Figure 17)
-
346
6
35
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 22.5 A, di/dt= 100 A/µs
VDD = 100 V, Tj = 150 °C
(see Figure 17)
-
432
8.4
39
ns
µC
A
1. The value is rated according to Rthj-case and limited by package.
2. Pulse width limited by safe operating area
3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
2.1
STL45N65M5
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM14956v1
ID
(A)
Zth PowerFLAT 8x8 HV
K
δ=0.5
n)
Op
Lim erat
ite ion
d b in
y m this
ax ar
RD ea
is
S(
o
Tj=150°C
Tc=25°C
Single pulse
10
0.2
10µs
0.1
100µs
-1
10
0.05
0.02
1
1ms
0.01
Single pulse
10ms
-2
0.1
0.1
Figure 4.
10
1
10 -5
10
VDS(V)
100
Output characteristics
Figure 5.
AM14957v1
ID
(A)
-4
VGS=10V
80
-2
-3
10
tp (s)
10
10
Transfer characteristics
AM14958v1
ID
(A)
VDS=25V
80
7V
60
60
40
40
20
20
6V
0
0
Figure 6.
5
10
15
20
0
25
VDS(V)
3
Gate charge vs gate-source voltage Figure 7.
VGS
(V)
AM14960v1
VDS
VDD=520V
ID=17.5A
VDS
12
(V)
5
4
7
6
8
9
VGS(V)
Static drain-source on-resistance
AM14959v1
RDS(on)
(Ω)
500
0.081
10
400
8
300
0.076
6
200
4
0.071
100
2
0
0
6/17
20
40
60
80
100
0
Qg(nC)
0.066
0
5
10
15
Doc ID 023354 Rev 1
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20
25
ID(A)
STL45N65M5
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
Output capacitance stored energy
AM14961v1
C
(pF)
AM14962v1
Eoss (µJ)
16
10000
14
Ciss
1000
12
10
8
100
Coss
6
4
10
Crss
2
1
0.1
1
100
10
Figure 10. Normalized gate threshold voltage
vs. temperature
AM05459v2
VGS(th)
(norm)
1.10
0
0
VDS(V)
ID=250µA
100
200 300
400 500 600
VDS(V)
Figure 11. Normalized on-resistance vs.
temperature
AM05460v2
RDS(on)
(norm)
2.1
VGS=10V
ID=17.5V
1.9
1.00
1.7
1.5
1.3
0.90
1.1
0.80
0.9
0.7
0.70
-50 -25
25
0
50
75 100
TJ(°C)
Figure 12. Drain-source diode forward
characteristics
0
25
50
75 100
TJ(°C)
Figure 13. Normalized VDS vs. temperature
AM05461v1
VSD
(V)
0.5
-50 -25
AM10399v1
VDS
(norm)
TJ=-50°C
1.08
1.2
ID = 1mA
1.06
1.0
1.04
0.8
1.02
TJ=25°C
1.00
0.6
TJ=150°C
0.98
0.4
0.96
0.2
0
0.94
0
10
20
30
40
50 ISD(A)
0.92
-50 -25
0
25
50
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75 100
TJ(°C)
7/17
Electrical characteristics
STL45N65M5
Figure 14. Switching losses vs. gate
resistance (1)
E
(μJ)
600
AM14963v1
Eon
ID=23A
VGS=10V
VDD=400V
500
400
Eoff
300
200
100
0
0
10
20
30
40
RG(Ω)
1. Eon including reverse recovery of a SiC diode
8/17
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STL45N65M5
3
Test circuits
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 17. Test circuit for inductive load
Figure 18. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 19. Unclamped inductive waveform
V(BR)DSS
AM01471v1
Figure 20. Switching time waveform
Concept waveform for Inductive Load Turn-off
Id
VD
90%Vds
90%Id
Tdelay-off
-off
IDM
Vgs
90%Vgs
on
ID
))
Vgs(I(t))
VDD
VDD
10%Vds
10%Id
Vds
Trise
AM01472v1
Tfall
Tcross -over
-
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AM05540v2
9/17
Package mechanical data
4
STL45N65M5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
10/17
Doc ID 023354 Rev 1
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STL45N65M5
Package mechanical data
Table 8.
PowerFLAT™ 8x8 HV mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.95
1.00
1.05
D
8.00
E
8.00
D2
7.05
7.20
7.30
E2
4.15
4.30
4.40
e
L
2.00
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.10
Doc ID 023354 Rev 1
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0.60
11/17
Package mechanical data
STL45N65M5
Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data
BOTTOM VIEW
b
CA B
L
bbb
0.40
E2
PIN#1 ID
D2
C
A
ccc C
A1
0.20±0.008
SIDE VIEW
SEATING
PLANE
0.08 C
D
A
B
E
INDEX AREA
aaa C
TOP VIEW
aaa C
8222871_Rev_B
12/17
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STL45N65M5
Package mechanical data
Figure 22. PowerFLAT™ 8x8 HV recommended footprint
0.60
7.70
4.40
7.30
2.00
1.05
Footprint
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Packaging mechanical data
5
STL45N65M5
Packaging mechanical data
Figure 23. PowerFLAT™ 8x8 HV tape
P2 (2.0±0.1)
T (0.30±0.05)
P0 (4.0±0.1)
D0 ( 1.55±0.05)
D1 ( 1.5 Min)
P1 (12.00±0.1)
W (16.00±0.3)
F (7.50±0.1)
B0 (8.30±0.1)
E (1.75±0.1)
A0 (8.30±0.1)
K0 (1.10±0.1)
Note: Base and Bulk quantity 3000 pcs
8229819_Tape_revA
Figure 24. PowerFLAT™ 8x8 HV package orientation in carrier tape.
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STL45N65M5
Packaging mechanical data
Figure 25. PowerFLAT™ 8x8 HV reel
8229819_Reel_revA
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15/17
Revision history
6
STL45N65M5
Revision history
Table 9.
16/17
Document revision history
Date
Revision
20-Sep-2012
1
Changes
First release.
Doc ID 023354 Rev 1
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STL45N65M5
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