Download STL18N55M5

STL18N55M5
N-channel 550 V, 0.205 Ω, 13 A PowerFLAT™ 8x8 HV
MDmesh™ V Power MOSFET
Features
Type
VDSS @
TJmax
RDS(on)
max
ID
STL18N55M5
600 V
< 0.270 Ω
13 A (1)
3
3
3
"OTTOMVIEW
'
$
1. The value is rated according to Rthj-case
■
100% avalanche tested
■
Low input capacitance and gate charge
■
Low gate input resistance
0OWER&,!4˜X(6
Application
■
Switching applications
Description
Figure 1.
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Internal schematic diagram
$
'
3
!-V
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL18N55M5
18N55M5
PowerFLAT™ 8x8 HV
Tape and reel
October 2011
Doc ID 17468 Rev 2
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Contents
STL18N55M5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STL18N55M5
1
Electrical ratings
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
550
V
VGS
Gate-source voltage
± 25
V
Drain current (continuous) at TC = 25 °C
13
A
Drain current (continuous) at TC = 100 °C
8
A
ID
(1)
ID (1)
IDM
(1),(2)
Drain current (pulsed)
52
A
ID(3)
Drain current (continuous) at Tamb = 25 °C
2.4
A
ID(3)
Drain current (continuous) at Tamb = 100 °C
1.5
A
9.6
A
Total dissipation at Tamb = 25 °C
3
W
Total dissipation at TC = 25 °C
90
W
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
4
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
200
mJ
Peak diode recovery voltage slope
15
V/ns
- 55 to 150
°C
150
°C
Value
Unit
1.38
°C/W
45
°C/W
IDM(2),(3) Drain current (pulsed)
PTOT
(3)
PTOT(1)
dv/dt (4)
Storage temperature
Tstg
Max. operating junction temperature
Tj
1. The value is rated according to Rthj-case
2. Pulse width limited by safe operating area
3. When mounted on FR-4 board of inch², 2oz Cu
4. ISD ≤ 13 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD=400 V
Table 3.
Symbol
Rthj-case
Thermal data
Parameter
Thermal resistance junction-case max
Rthj-amb(1) Thermal resistance junction-amb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu
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Electrical characteristics
2
STL18N55M5
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4.
Symbol
On /off states
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source
breakdown voltage
ID = 1 mA, VGS = 0
IDSS
Zero gate voltage
drain current
VDS = 550 V
VDS = 550 V, TC=125 °C
VGS = 0
1
100
µA
µA
IGSS
Gate-body leakage
current
VGS = ± 25 V, VDS = 0
100
nA
4
5
V
0.205
0.270
Ω
Min.
Typ.
Max.
Unit
-
1352
38
3.7
-
pF
pF
pF
-
98
-
pF
-
35
-
pF
VGS(th)
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
Table 5.
Symbol
3
VGS = 10 V, ID = 6 A
V
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Ciss
Coss
Crss
550
Co(tr)(1)
Equivalent
capacitance time
related
Co(er)(2)
Equivalent
capacitance energy
related
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0
VDS = 0 to 440 V, VGS = 0
RG
Intrinsic gate
resistance
f = 1 MHz open drain
-
1.7
-
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 440 V, ID = 6.5 A,
VGS = 10 V
(see Figure 15)
-
31
6.3
14
-
nC
nC
nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as
Coss when VDS increases from 0 to 80% VDSS
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STL18N55M5
Electrical characteristics
Table 6.
Symbol
td(off)
tr(V)
tc(off)
tf(i)
Switching times
Parameter
Test conditions
Turn-off delay time
Rise time
Cross time
Fall time
Table 7.
VDD = 400 V, ID = 9A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 16),
(see Figure 19)
Parameter
ISD
ISDM (1)
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
IRRM
trr
Qrr
IRRM
Typ.
-
29
9.5
23
13
Min.
Typ.
Max
Unit
-
ns
ns
ns
ns
Source drain diode
Symbol
trr
Qrr
Min.
Test conditions
Max. Unit
-
13
52
A
A
ISD = 13 A, VGS = 0
-
1.5
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 13 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 16)
-
238
2.8
23.5
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 13 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 16)
-
278
3.3
24
ns
µC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
STL18N55M5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM10370v1
ID
(A)
Zth PowerFLAT 8x8 HV
K
δ=0.5
Tj=150°C
Tc=25°C
Single pulse
is
0.2
S(
on
)
Op
Lim era
ite tion
d
by in th
ma is a
x R re
a
D
10
1
10µs
0.1
-1
10
0.05
100µs
0.02
0.01
1ms
Single pulse
10ms
-2
0.1
0.1
10
1
Figure 4.
100
10 -5
10
VDS(V)
Output characteristics
Figure 5.
AM08664v1
ID
(A)
-4
7.5V
-2
-3
10
tp (s)
10
10
Transfer characteristics
AM08665v1
ID
(A)
VGS=10V
VDS=20V
7V
20
20
6.5V
15
15
6V
10
10
5.5V
5
5
5V
0
0
0
5
Figure 6.
10
15
VDS(V)
Gate charge vs gate-source voltage Figure 7.
AM08666v1
VGS
(V)
VGS
VDD=440V
ID=6.5A
12
VDS
8
6
0
5
10
15
20
25
30
35
7
8
9
VGS(V)
AM10371v1
0.25
0.23
0.22
250
0.21
200
0.20
50
0
6
Static drain-source on resistance
0
Qg(nC)
VGS=10V
0.24
300
100
2
5
RDS(on)
(Ω)
350
150
4
4
450
400
10
6/14
3
0.19
0.18
0.17
0.16
0.15
0
2
4
6
8
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10
12
ID(A)
STL18N55M5
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
Output capacitance stored energy
AM08668v1
C
(pF)
AM08669v1
Eoss
(µJ)
4.0
10000
3.5
Ciss
1000
3.0
2.5
2.0
100
1.5
Coss
1.0
10
Crss
1
0.1
1
100
10
0
0
VDS(V)
Figure 10. Normalized gate threshold voltage
vs temperature
AM08670v1
VGS(th)
(norm)
0.5
100
200
300
400
500
VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM08671v1
RDS(on)
(norm)
ID=250µA
1.10
2.1
ID =6.5A
VGS=10V
1.9
1.00
1.7
1.5
0.90
1.3
1.1
0.80
0.9
0.7
0.70
-50 -25
25
0
50
TJ(°C)
75 100
0.5
-50 -25
0
25
50
75 100
TJ(°C)
Figure 12. Switching losses vs gate resistance Figure 13. Normalized BVDSS vs temperature
(1)
AM08673v1
E
(μJ)
AM08672v1
BVDSS
(norm)
140
120
Eon
ID=9A
VCL=400V
VGS=10V
1.07
ID =1mA
1.05
1.03
100
Eoff
80
1.01
60
0.99
40
0.97
20
0.95
0
0
10
20
30
40
RG(Ω)
0.93
-50 -25
0
25
50
75 100
TJ(°C)
1. Eon including reverse recovery of a SiC diode
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Test circuits
3
STL18N55M5
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 16. Test circuit for inductive load
Figure 17. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 18. Unclamped inductive waveform
AM01471v1
Figure 19. Switching time waveform
Inductive Load Turn - off
V(BR)DSS
Id
VD
90%Vds
90%Id
Tdelay-off
-off
IDM
Vgs
90%Vgs
on
ID
Vgs(I(t))
))
VDD
VDD
10%Vds
10%Id
Vds
Trise
AM01472v1
8/14
Tfall
Tcross --over
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AM05540v1
STL18N55M5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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Package mechanical data
Table 8.
STL18N55M5
PowerFLAT™ 8x8 HV mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.95
1.00
1.05
D
8.00
E
8.00
D2
7.05
7.20
7.30
E2
4.15
4.30
4.40
e
L
10/14
2.00
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.10
Doc ID 17468 Rev 2
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0.60
STL18N55M5
Package mechanical data
Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data
BOTTOM VIEW
b
CA B
L
bbb
0.40
E2
PIN#1 ID
D2
C
A
ccc C
A1
0.20±0.008
SIDE VIEW
SEATING
PLANE
0.08 C
D
A
B
E
INDEX AREA
aaa C
TOP VIEW
aaa C
8222871_Rev_B
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Package mechanical data
STL18N55M5
Figure 21. PowerFLAT™ 8x8 HV recommended footprint
0.60
7.70
4.40
7.30
2.00
1.05
Footprint
12/14
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STL18N55M5
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
03-May-2010
1
First release
2
Section 4: Package mechanical data has been updated
Document status promoted from preliminary data to datasheet
Inserted new section: Electrical characteristics (curves)
Minor text changes.
04-Oct-2011
Changes
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STL18N55M5
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