Download STL12N65M5

STL12N65M5
N-channel 650 V, 0.42 Ω, 8.5 A PowerFLAT™ 8x8 HV
MDmesh™ V Power MOSFET
Features
Order code
VDSS @
TJmax
RDS(on)
max
ID
STL12N65M5
710 V
< 0.47 Ω
8.5 A (1)
3
3
3
"OTTOMVIEW
'
$
1. The value is rated according to Rthj-case
■
100% avalanche tested
■
Low input capacitance and gate charge
■
Low gate input resistance
0OWER&,!4˜X(6
Applications
■
Switching applications
Description
Figure 1.
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low onresistance, which is unmatched among siliconbased Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Internal schematic diagram
$
'
3
!-V
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL12N65M5
12N65M5
PowerFLAT™ 8x8 HV
Tape and reel
November 2011
Doc ID 17450 Rev 2
1/17
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17
Contents
STL12N65M5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
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STL12N65M5
1
Electrical ratings
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
650
V
VGS
Gate-source voltage
± 25
V
Drain current (continuous) at TC = 25 °C
8.5
A
ID
(1)
ID (1)
Drain current (continuous) at TC = 100 °C
5.4
A
(1),(2)
Drain current (pulsed)
34
A
ID
(3)
Drain current (continuous) at Tamb = 25 °C
1.8
A
ID
(3)
Drain current (continuous) at Tamb = 100 °C
1
A
7.2
A
Total dissipation at Tamb = 25 °C
3
W
Total dissipation at TC = 25 °C
70
W
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
2.5
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
150
mJ
Peak diode recovery voltage slope
15
V/ns
- 55 to 150
°C
150
°C
Value
Unit
1.78
°C/W
45
°C/W
IDM
IDM(2),(3) Drain current (pulsed)
PTOT
(3)
PTOT(1)
dv/dt (4)
Tstg
Storage temperature
Tj
Max. operating junction temperature
1. The value is rated according to Rthj-case
2. Pulse width limited by safe operating area
3. When mounted on FR-4 board of inch², 2oz Cu.
4. ISD ≤ 8.5 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 400 V.
Table 3.
Symbol
Rthj-case
Thermal data
Parameter
Thermal resistance junction-case max
Rthj-amb(1) Thermal resistance junction-amb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu.
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Electrical characteristics
2
STL12N65M5
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
On /off states
Parameter
Test conditions
Drain-source
breakdown voltage
(VGS = 0)
ID = 1 mA
Min.
Typ.
Max.
Unit
650
V
IDSS
VDS = 650 V
Zero gate voltage
drain current (VGS = 0) VDS = 650 V, TC=125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0)
100
nA
4
5
V
0.42
0.47
Ω
Min.
Typ.
Max.
Unit
-
900
22
2
-
pF
pF
pF
-
64
-
pF
-
21
-
pF
VGS = ± 25 V
VGS(th)
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
Table 5.
Symbol
VGS = 10 V, ID = 4.3 A
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Ciss
Coss
Crss
3
Co(tr)(1)
Equivalent
capacitance time
related
Co(er)(2)
Equivalent
capacitance energy
related
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0
VDS = 0 to 520 V, VGS = 0
RG
Intrinsic gate
resistance
f = 1 MHz open drain
-
2.5
-
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 520 V, ID = 4.25 A,
VGS = 10 V
(see Figure 16)
-
20
4.8
8.3
-
nC
nC
nC
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as
Coss when VDS increases from 0 to 80% VDSS
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STL12N65M5
Electrical characteristics
Table 6.
Symbol
Switching times
Parameter
Test conditions
Turn-off delay time
Rise time
Cross time
Fall time
td(off)
tr
tc
tf
Table 7.
VDD = 400 V, ID = 5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 17),
(see Figure 20)
Parameter
ISD
ISDM (1)
Source-drain current
Source-drain current (pulsed)
VSD (2)
Forward on voltage
IRRM
trr
Qrr
IRRM
Typ.
-
22.6
17.6
23.4
15.6
Min.
Typ.
Max
Unit
-
ns
ns
ns
ns
Source drain diode
Symbol
trr
Qrr
Min.
Test conditions
Max. Unit
-
8.5
34
A
A
ISD = 8.5 A, VGS = 0
-
1.5
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 8.5 A, di/dt = 100 A/µs
VDD = 100 V (see Figure 17)
-
230
2.2
19
ns
µC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 8.5 A, di/dt = 100 A/µs
VDD = 100 V, Tj = 150 °C
(see Figure 17)
-
280
2.7
19
ns
µC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
STL12N65M5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM10355v1
ID
(A)
Zth PowerFLAT 8x8 HV
K
δ=0.5
Tj=150°C
Tc=25°C
Single pulse
is
ea )
ar S(on
D
t
R
in ax
n
io y m
t
b
ra
pe ed
O mit
Li
10
0.2
s
hi
1
10µs
0.1
100µs
-1
10
0.05
1ms
0.02
0.01
10ms
0.1
Single pulse
-2
0.01
0.1
Figure 4.
10
1
10 -5
10
VDS(V)
100
Output characteristics
Figure 5.
AM05575v1
ID
(A)
VGS=10V
-4
-2
-3
10
tp (s)
10
10
Transfer characteristics
AM05576v1
ID
(A)
14
12
12
10
VDS= 20V
7V
10
8
8
6
6
6V
4
4
2
2
5V
0
0
Figure 6.
5
10
15
20
25
0
0
30 VDS(V)
Gate charge vs gate-source voltage Figure 7.
AM05578v1
VGS
(V)
600
VDD=520V
12
500
ID=4.25A
VDS
2
4
8
6
10
VGS(V)
Static drain-source on resistance
AM10356v1
RDS(on)
(Ω)
VGS=10V
0.46
0.45
10
400
0.44
8
300
6
0.43
0.42
200
4
0.41
100
2
0
0
6/17
5
10
15
20
0
Qg(nC)
0.40
0.39
0
1
2
3
4
5
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6
7
8
ID(A)
STL12N65M5
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
Output capacitance stored energy
AM05579v1
C
(pF)
AM05580v1
Eoss (µJ)
4.0
3.5
1000
Ciss
3.0
2.5
100
2.0
Coss
10
1.5
1.0
Crss
1
0.1
1
100
10
0.5
0
0
VDS(V)
Figure 10. Normalized gate threshold voltage
vs temperature
AM05581v1
VGS(th)
(norm)
1.10
100
200 300
400 500 600
VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM05501v2
RDS(on)
(norm)
2.1
ID= 4.25 A
1.9
1.00
VGS= 10 V
1.7
1.5
1.3
0.90
1.1
0.80
0.9
0.7
0.70
-50 -25
25
0
50
75 100
TJ(°C)
Figure 12. Source-drain diode forward
characteristics
0
25
50
75 100 125 TJ(°C)
Figure 13. Normalized BVDSS vs temperature
AM05584v1
VSD
(V)
0.5
-50 -25
AM05583v1
BVDSS
(norm)
TJ=-50°C
1.07
1.2
TJ=25°C
1.0
1.05
1.03
0.8
1.01
0.6
0.99
TJ=150°C
0.4
0.97
0.2
0
0
0.95
10
20
30
40
50
ISD(A)
0.93
-50 -25
0
25
50
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75 100
TJ(°C)
7/17
Electrical characteristics
STL12N65M5
Figure 14. Switching losses vs gate resistance
(1)
AM05585v1
E
(μJ)
60
Eon
ID=5A
VDD=400V
50
40
30
Eoff
20
10
0
0
10
20
30
40
RG(Ω)
1. Eon including reverse recovery of a SiC diode
8/17
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STL12N65M5
3
Test circuits
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 17. Test circuit for inductive load
Figure 18. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 19. Unclamped inductive waveform
V(BR)DSS
AM01471v1
Figure 20. Switching time waveform
Concept waveform for Inductive Load Turn-off
Id
VD
90%Vds
90%Id
Tdelay-off
-off
IDM
Vgs
90%Vgs
on
ID
Vgs(I(t))
))
VDD
VDD
10%Vds
10%Id
Vds
Trise
AM01472v1
Tfall
Tcross -over
-
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AM05540v2
9/17
Package mechanical data
4
STL12N65M5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
10/17
Doc ID 17450 Rev 2
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STL12N65M5
Package mechanical data
Table 8.
PowerFLAT™ 8x8 HV mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.95
1.00
1.05
D
8.00
E
8.00
D2
7.05
7.20
7.30
E2
4.15
4.30
4.40
e
L
2.00
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.10
Doc ID 17450 Rev 2
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0.60
11/17
Package mechanical data
STL12N65M5
Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data
BOTTOM VIEW
b
CA B
L
bbb
0.40
E2
PIN#1 ID
D2
C
A
ccc C
A1
0.20±0.008
SIDE VIEW
SEATING
PLANE
0.08 C
D
A
B
E
INDEX AREA
aaa C
TOP VIEW
aaa C
8222871_Rev_B
12/17
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STL12N65M5
Package mechanical data
Figure 22. PowerFLAT™ 8x8 HV recommended footprint
0.60
7.70
4.40
7.30
2.00
1.05
Footprint
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Packaging mechanical data
5
STL12N65M5
Packaging mechanical data
Figure 23. PowerFLAT™ 8x8 HV tape
P2 (2.0±0.1)
T (0.30±0.05)
P0 (4.0±0.1)
D0 ( 1.55±0.05)
D1 ( 1.5 Min)
P1 (12.00±0.1)
W (16.00±0.3)
F (7.50±0.1)
B0 (8.30±0.1)
E (1.75±0.1)
A0 (8.30±0.1)
K0 (1.10±0.1)
Note: Base and Bulk quantity 3000 pcs
8229819_Tape_revA
Figure 24. PowerFLAT™ 8x8 HV package orientation in carrier tape
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STL12N65M5
Packaging mechanical data
Figure 25. PowerFLAT™ 8x8 HV reel
8229819_Reel_revA
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Revision history
6
STL12N65M5
Revision history
Table 9.
Document revision history
Date
Revision
30-Apr-2010
1
First release
2
Document status promoted from preliminary data to datasheet:
– Added Section 2.1: Electrical characteristics (curves)
– Added Section 5: Packaging mechanical data
Minor text changes
22-Nov-2011
16/17
Changes
Doc ID 17450 Rev 2
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STL12N65M5
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