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a
CMOS 1.8 V to 5.5 V, 2.5 2:1 Mux/SPDT Switch in SOT-23
ADG719
FEATURES
1.8 V to 5.5 V Single Supply
4 (Max) On Resistance
0.75 (Typ) On Resistance Flatness
Automotive Temperature Range: –40°C to +125°C
–3 dB Bandwidth > 200 MHz
Rail-to-Rail Operation
6-Lead SOT-23 Package and 8-Lead SOIC Package
Fast Switching Times:
tON = 12 ns
tOFF = 6 ns
Typical Power Consumption (< 0.01 W)
TTL/CMOS Compatible
FUNCTIONAL BLOCK DIAGRAM
ADG719
S2
D
S1
IN
SWITCHES SHOWN FOR A LOGIC “1” INPUT
APPLICATIONS
Battery-Powered Systems
Communication Systems
Sample-and-Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
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GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG719 is a monolithic CMOS SPDT switch. This switch
is designed on a submicron process that provides low power
dissipation yet gives high switching speed, low on resistance, and
low leakage currents.
1. 1.8 V to 5.5 V Single-Supply Operation. The ADG719 offers
high performance, including low on resistance and fast switching
times, and is fully specified and guaranteed with 3 V and 5 V
supply rails.
The ADG719 can operate from a single-supply range of 1.8 V to
5.5 V, making it ideal for use in battery-powered instruments and
with the new generation of DACs and ADCs from Analog Devices.
2. Very Low RON (4 Ω Max at 5 V and 10 Ω Max at 3 V).
At 1.8 V operation, RON is typically 40 Ω over the temperature range.
Each switch of the ADG719 conducts equally well in both
directions when on. The ADG719 exhibits break-before-make
switching action.
3. Automotive Temperature Range: –40°C to +125°C
Because of the advanced submicron process, –3 dB bandwidths
of greater than 200 MHz can be achieved.
The ADG719 is available in a 6-lead SOT-23 package and an
8-lead µSOIC package.
4. On Resistance Flatness (RFLAT(ON)) (0.75 Ω typ).
5. –3 dB Bandwidth > 200 MHz.
6. Low Power Dissipation. CMOS construction ensures low
power dissipation.
7. Fast tON /tOFF.
8. Tiny 6-lead SOT-23 and 8-lead µSOIC packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADG719–SPECIFICATIONS1 (V
Parameter
+25C
DD
B Version
–40C to
+85C
–40C to
+125C
Unit
0 V to VDD
V
5
7
Ω typ
Ω max
0.1
0.4
0.4
1.2
1.5
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
2.5
4
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON)) 0.75
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Channel On Leakage ID, IS (On)
± 0.01
± 0.25
± 0.01
± 0.25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
0.005
DYNAMIC CHARACTERISTICS2
tON
7
= 5 V 10%, GND = 0 V.)
Ω typ
Ω max
Ω typ
Ω max
nA typ
± 0.35
1
± 0.35
5
nA typ
VS = 0 V to VDD, IS = –10 mA
VS = 0 V to VDD, IS = –10 mA
VDD = 5.5 V
VS = 4.5 V/1 V, VD = 1 V/4.5 V;
nA max
Test Circuit 2
VS = VD = 1 V or VS = VD = 4.5 V;
nA max
Test Circuit 3
V min
V max
± 0.1
µA typ
µA max
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF,
VS1 = VS2 = 3 V; Test Circuit 5
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF; Test Circuit 8
Off Isolation
–67
–87
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
Channel-to-Channel Crosstalk
–62
–82
dB typ
dB typ
Bandwidth –3 dB
CS (Off)
CD, CS (On)
200
7
27
MHz typ
pF typ
pF typ
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3
6
Break-Before-Make Time Delay, tD 8
1
POWER REQUIREMENTS
IDD
VS = 0 V to VDD, IS = –10 mA;
Test Circuit 1
2.4
0.8
12
tOFF
Test Conditions/Comments
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
0.001
1.0
µA typ
µA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. B
ADG719
SPECIFICATIONS1
(VDD = 3 V 10%, GND = 0 V.)
Parameter
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
6
B Version
–40C to
–40C to
+85C
+125C
0 V to VDD
On Resistance Match Between
Channels (∆RON)
0.1
0.4
2.5
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Channel On Leakage ID, IS (On)
7
10
± 0.01
± 0.25
± 0.01
± 0.25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
0.005
DYNAMIC CHARACTERISTICS2
tON
10
12
0.4
Unit
Test Conditions/Comments
V
Ω typ
Ω max
VS = 0 V to VDD, IS = –10 mA;
Test Circuit 1
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = –10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = VD = 1 V or VS = VD = 3 V;
Test Circuit 3
± 0.35
1
± 0.35
5
nA typ
nA max
nA typ
nA max
2.0
0.8
V min
V max
± 0.1
µA typ
µA max
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2 V; Test Circuit 5
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
RL = 50 Ω, CL = 5 pF; Test Circuit 8
Off Isolation
–67
–87
ns typ
ns max
ns typ
ns max
ns typ
ns min
dB typ
dB typ
Channel-to-Channel Crosstalk
–62
–82
dB typ
dB typ
Bandwidth –3 dB
CS (Off)
CD, CS (On)
200
7
27
MHz typ
pF typ
pF typ
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15
tOFF
4
8
Break-Before-Make Time Delay, tD 8
1
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
POWER REQUIREMENTS
IDD
0.001
1.0
NOTES
1
Temperature range is as follows: B Version: –40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
VS = 0 V to VDD, IS = –10 mA
–3–
µA typ
µA max
ADG719
ABSOLUTE MAXIMUM RATINGS 1
TERMINOLOGY
(TA = 25°C, unless otherwise noted.)
VDD
GND
S
D
IN
RON
∆RON
Most Positive Power Supply Potential
Ground (0 V) Reference
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic Resistance between D and S
On Resistance Match between Any Two Channels
i.e., RON max – RON min
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance,
as measured over the specified analog signal range.
IS (Off)
Source Leakage Current with the Switch Off
ID, IS (On)
Channel Leakage Current with the Switch On
VD (VS)
Analog Voltage on Terminals D and S
CS (Off)
Off Switch Source Capacitance
CD, CS (On) On Switch Capacitance
tON
Delay between Applying the Digital Control
Input and the Output Switching On
tOFF
Delay between Applying the Digital Control
Input and the Output Switching Off
tD
Off Time or On Time Measured between the
90% Points of Both Switches, when Switching
From One Address State to Another
Crosstalk
A Measure of Unwanted Signal That Is Coupled
through from One Channel to Another as a Result
of Parasitic Capacitance
Off Isolation A Measure of Unwanted Signal Coupling through
an Off Switch
Bandwidth
The Frequency at Which the Output is Attenuated
by –3 dBs
On Response The Frequency Response of the On Switch
Insertion Loss Loss due to On Resistance of Switch
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or
. . . . . . . . . . . . . . . . . . . . . . . 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
µSOIC Package, Power Dissipation . . . . . . . . . . . . . . . 315 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
SOT-23 Package, Power Dissipation . . . . . . . . . . . . . . 282 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 91.99°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
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Table I. Truth Table
ADG719 IN
Switch S1
Switch S2
0
1
ON
OFF
OFF
ON
PIN CONFIGURATIONS
8-Lead SOIC
(RM-8)
6-Lead SOT-23
(RT-6)
IN 1
VDD 2
GND 3
ADG719
TOP VIEW
(Not to Scale)
6
S2
5
D
4
S1
8
D 1
ADG719
S2
NC
TOP VIEW
GND 3 (Not to Scale) 6 IN
S1 2
VDD 4
7
5
NC
NC = NO CONNECT
ORDERING GUIDE
Model
Temperature Range
Brand*
Package Description
Package Option
ADG719BRM
ADG719BRT
–40°C to +125°C
–40°C to +125°C
S5B
S5B
µSOIC (MicroSmall Outline IC) [MSOP]
SOT-23 (Plastic Surface Mount)
RM-8
RT-6
*Branding on these packages is limited to three characters due to space constraints.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG719 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
Typical Performance Characteristics– ADG719
6.0
0.15
5.5
VDD = 2.7V
VDD = 5V
VD = 4.5V/1V
VS = 1V/4.5V
TA = 25C
5.0
4.5
0.10
4.0
CURRENT – nA
RON – VDD = 4.5V
VDD = 3.0V
3.5
3.0
2.5
VDD = 5.0V
2.0
ID, I S (ON)
0.05
1.5
0
1.0
0.5
IS (OFF)
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–0.05
5.0
0
10
20
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
TPC 1. On Resistance vs. VD (VS), Single Supplies
80
90
0.15
VDD = 3V
VD = 3V/1V
VS = 1V/3V
VDD = 3V
5.5
5.0
+85C
4.5
0.10
+25C
CURRENT – nA
4.0
–40C
RON – 70
TPC 4. Leakage Currents vs. Temperature
6.0
3.5
3.0
2.5
0.05
ID, I S (ON)
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2.0
1.5
0
1.0
0.5
0
30
40
50
60
TEMPERATURE – C
IS (OFF)
1.0
1.5
2.0
2.5
0.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
0
–0.05
3.0
TPC 2. On Resistance vs. VD (VS) for Different
Temperatures, VDD = 3 V
0
10
20
30
40
50
60
TEMPERATURE – C
70
80
90
TPC 5. Leakage Currents vs. Temperature
6.0
10m
5.5
VDD = 5V
VDD = 5V
5.0
1m
4.5
100
3.5
I SUPPLY – A
RON – 4.0
+85C
3.0
2.5
+25C
2.0
–40C
10
1
100n
1.5
1.0
10n
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1n
5.0
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
TPC 3. On Resistance vs. VD (VS) for Different
Temperatures, VDD = 5 V
REV. B
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
TPC 6. Supply Current vs. Input Switching Frequency
–5–
ADG719
0
–30
VDD = 5V, 3V
–40
VDD = 5V
–60
ON RESPONSE – dB
OFF ISOLATION – dB
–50
–70
–80
–90
–100
–2
–4
–110
–120
–130
10k
100k
1M
10M
FREQUENCY – Hz
–6
10k
100M
TPC 7. Off Isolation vs. Frequency
100k
1M
10M
FREQUENCY – Hz
100M
TPC 9. On Response vs. Frequency
12
–30
VDD = 5V, 3V
–40
10
–50
6
–70
QINJ – pC
CROSSTALK – dB
8
–60
–80
–90
4
VDD 3V
2
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–100
0
–110
VDD 5V
–2
–120
–130
10k
100k
1M
10M
FREQUENCY – Hz
–4
100M
0
1
2
3
4
5
VS – V
TPC 8. Crosstalk vs. Frequency
TPC 10. Charge Injection vs. Source Voltage
–6–
REV. B
ADG719
Test Circuits
IDS
V1
S
IS (OFF)
D
ID (OFF)
S
A
VS
D
ID (ON)
S
A
VD
VS
RON = V1/I DS
Test Circuit 1. On Resistance
A
VS
Test Circuit 2. Off Leakage
0.1F
D
VD
Test Circuit 3. On Leakage
VDD
VIN
50%
50%
VDD
S
D
IN
VS
VOUT
RL
300
90%
90%
VOUT
CL
35pF
GND
tOFF
tON
Test Circuit 4. Switching Times
0.1F
S1
VS1
VDD
VIN
VDD
D2
D
S2
VS2
50%
0V
CL2
35pF
RL2
300
IN
VOUT
50%
VOUT
50%
0V
tD
GND
VIN
50%
tD
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Test Circuit 5. Break-Before-Make Time Delay, tD
VDD
0.1F
VDD
0.1F
NETWORK
ANALYZER
NETWORK
ANALYZER
VDD
S
IN
50
50
VOUT
GND
RL
50
D
50
VS
VOUT
R
50
IN
GND
CHANNEL-TO-CHANNEL
VOUT
VOUT
OFF ISOLATION = 20 LOG
VS
CROSSTALK = 20 LOG
Test Circuit 6. Off Isolation
VS
Test Circuit 7. Channel-to-Channel Crosstalk
VDD
0.1F
NETWORK
ANALYZER
VDD
S
50
IN
VS
D
VIN
RL
50
GND
INSERTION LOSS = 20 LOG
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Test Circuit 8. Bandwidth
REV. B
S1
S2
VS
D
VIN
VDD
RL
50
–7–
ADG719
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function A(s). Because the
switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with CDS and the load capacitance. The
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
APPLICATIONS INFORMATION
The ADG719 belongs to Analog Devices’ new family of
CMOS switches. This series of general-purpose switches has
improved switching times, lower on resistance, higher bandwidths, low power consumption, and low leakage currents.
ADG719 Supply Voltages
Functionality of the ADG719 extends from 1.8 V to 5.5 V single
supply, which makes it ideal for battery-powered instruments
where power efficiency and performance are important design
parameters.
The dominant effect of the output capacitance, CD, causes the
pole breakpoint frequency to occur first. Therefore, in order to
maximize bandwidth, a switch must have a low input and
output capacitance and low on resistance. The On Response
vs. Frequency plot for the ADG719 can be seen in TPC 9.
It is important to note that the supply voltage effects the input
signal range, the on resistance, and the switching times of the part.
By taking a look at the Typical Performance Characteristics and the
Specifications, the effects of the power supplies can be clearly seen.
Off Isolation
For VDD = 1.8 V operation, RON is typically 40 Ω over the
temperature range.
Off isolation is a measure of the input signal coupled through an
off switch to the switch output. The capacitance, CDS, couples the
input signal to the output load when the switch is off, as shown
in Figure 2.
On Response vs. Frequency
Figure 1 illustrates the parasitic components that affect the ac performance of CMOS switches (the switch is shown surrounded by a
box). Additional external capacitances will further degrade some
performance. These capacitances affect feedthrough, crosstalk,
and system bandwidth.
CDS
D
S
VOUT
VIN
CD
CLOAD
RLOAD
CDS
D
S
VIN
Figure 2. Off Isolation Is Affected by External Load
Resistance and Capacitance
VOUT
RON
CD
CLOAD
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RLOAD
The larger the value of CDS, the larger the values of feedthrough
that will be produced. TPC 7 illustrates the drop in off isolation as
a function of frequency. From dc to roughly 200 kHz, the switch
shows better than –95 dB isolation. Up to frequencies of 10 MHz,
the off isolation remains better than –67 dB. As the frequency
increases, more and more of the input signal is coupled through to
the output. Off isolation can be maximized by choosing a switch
with the smallest CDS possible. The values of load resistance and
capacitance also affect off isolation, since they contribute to the
coefficients of the poles and zeros in the transfer function of the
switch when open.
Figure 1. Switch Represented by Equivalent Parasitic
Components
The transfer function that describes the equivalent diagram of
the switch (Figure 1) is of the form A(s) shown below:
 s( RON CDS ) + 1 
A( s ) = RT 

 s( RT RON CT ) + 1
where:
RT = RLOAD ( RLOAD + RON )


s( RLOAD CDS )
A( s ) = 

1
s
(
R
)
(
C
+
C
+
C
)
+
LOAD
LOAD
D
DS


CT = CLOAD + CD + CDS
–8–
REV. B
ADG719
OUTLINE DIMENSIONS
8-Lead Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4.90
BSC
3.00
BSC
1
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
0.80
0.40
8ⴗ
0ⴗ
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
6-Lead Plastic Surface Mount Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
2.90 BSC
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6
5
4
1
2
3
2.80 BSC
1.60 BSC
PIN 1
0.95 BSC
1.30
1.15
0.90
1.90
BSC
1.45 MAX
0.15 MAX
0.50
0.30
SEATING
PLANE
0.22
0.08
10ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MO-178AB
REV. B
–9–
0.60
0.45
0.30
ADG719
Revision History
Location
Page
7/02 Data Sheet changed from REV. A to REV. B.
Changes to Product Name ...............................................................................................................................................................1
Changes to FEATURES ..................................................................................................................................................................1
Additions to PRODUCT HIGHLIGHTS .......................................................................................................................................1
Changes to SPECIFICATIONS ......................................................................................................................................................2
Edits to ABSOLUTE MAXIMUM RATINGS ................................................................................................................................4
Changes to TERMINOLOGY.........................................................................................................................................................4
Edits to ORDERING GUIDE .........................................................................................................................................................4
Added new TPCs 4 and 5 ................................................................................................................................................................5
Replaced TPC 10 ............................................................................................................................................................................6
TEST CIRCUITs 6, 7, and 8 replaced ............................................................................................................................................7
Updated RM-8 and RT-6 package outlines ......................................................................................................................................9
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–10–
REV. B
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–11–
PRINTED IN U.S.A.
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–12–
C00044–0–7/02(B)