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a 1 pC Charge Injection, 100 pA Leakage, CMOS ⴞ5 V/+5 V/+3 V Quad SPST Switches ADG611/ADG612/ADG613 FEATURES 1 pC Charge Injection ⴞ2.7 V to ⴞ5.5 V Dual Supply +2.7 V to +5.5 V Single Supply Automotive Temperature Range –40ⴗC to +125ⴗC 100 pA Max @ 25ⴗC Leakage Currents 85 ⍀ On-Resistance Rail-to-Rail Switching Operation Fast Switching Times 16-Lead TSSOP Packages Typical Power Consumption (<0.1 W) TTL/CMOS-Compatible Inputs FUNCTIONAL BLOCK DIAGRAMS ADG611 ADG612 S1 IN1 IN1 D1 S2 S2 IN2 IN2 D2 S3 S3 IN3 S2 D2 S3 IN3 D3 D3 S4 S4 IN4 D4 D1 IN2 D2 IN3 S1 IN1 D1 IN4 APPLICATIONS Automatic Test Equipment Data Acquisition Systems Battery-Powered Systems Communication Systems Sample and Hold Systems Audio Signal Routing Relay Replacement Avionics ADG613 S1 D3 S4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC “1” INPUT www.BDTIC.com/ADI GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG611, ADG612, and ADG613 are monolithic CMOS devices containing four independently selectable switches. These switches offer ultralow charge injection of 1 pC over full input signal range and typical leakage currents of 10 pA at 25°C. 1. Ultralow Charge Injection (1 pC typically) 2. Dual ± 2.7 V to ± 5.5 V or Single +2.7 V to +5.5 V Operation. 3. Automotive Temperature Range, –40°C to +125°C 4. Small 16-lead TSSOP package. They are fully specified for ± 5 V, +5 V, and +3 V supplies. They contain four independent single-pole/single-throw (SPST) switches. The ADG611 and ADG612 differ only in that the digital control logic is inverted. The ADG611 switches are turned on with a logic low on the appropriate control input, while a logic high is required to turn on the switches of the ADG612. The ADG613 contains two switches whose digital control logic is similar to the ADG611, while the logic is inverted on the other two switches. Each switch conducts equally well in both directions when ON and has an input signal range that extends to the supplies. The ADG613 exhibits break-before-make switching action. The ADG611/ADG612/ADG613 are available in small 16-lead TSSOP packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADG611/ADG612/ADG613–SPECIFICATIONS DUAL SUPPLY1(V DD = +5 V ⴞ 10%, VSS = –5 V ⴞ 10%, GND = 0 V, unless otherwise noted.) Parameter 25ⴗC ANALOG SWITCH Analog Signal Range On-Resistance (RON) Y Version –40ⴗC –40ⴗC to +85ⴗC to +125ⴗC VSS to VDD 85 115 2 4 25 40 On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 140 160 5.5 6.5 55 60 V Ω typ Ω max Ω typ Ω max Ω typ Ω max ± 0.25 ±2 ± 0.25 ±2 ± 0.25 ±6 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 µA typ µA max pF typ 0.005 CIN, Digital Input Capacitance Unit 2 Test Conditions/Comments VS = ± 3 V, IS = –1 mA Test Circuit 1 VS = ± 3 V, IS = –1 mA VS = ± 3 V, IS = –1 mA VDD = +5.5 V, VSS = –5.5 V VD = ± 4.5 V, VS = ⫿4.5 V; Test Circuit 2 VD = ± 4.5 V, VS = ⫿4.5 V; Test Circuit 2 VD = VS = ± 4.5 V, Test Circuit 3 VIN = VINL or VINH www.BDTIC.com/ADI 2 DYNAMIC CHARACTERISTICS tON Break-Before-Make Time Delay, tD 45 65 25 40 15 Charge Injection –0.5 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –65 dB typ Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth 680 MHz typ CS (OFF) CD (OFF) CD, CS (ON) 5 5 5 pF typ pF typ pF typ 0.001 µA typ µA max µA typ µA max tOFF 75 90 45 50 10 POWER REQUIREMENTS IDD 1.0 ISS 0.001 1.0 RL = 300 Ω, CL = 35 pF VS = 3.0 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 3.0 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 3.0 V, Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 1 nF, Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz, Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz, Test Circuit 8 RL = 50 Ω, CL = 5 pF, Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = –5.5 V Digital Inputs = 0 V or 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature range is as follows. Y Version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG611/ADG612/ADG613 SINGLE SUPPLY1 (V DD = 5 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) 25ⴗC Parameter ANALOG SWITCH Analog Signal Range On-Resistance (RON) Y Version –40ⴗC –40ⴗC to +85ⴗC to +125ⴗC Unit 0 V to VDD On-Resistance Match Between Channels (∆RON) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance2 DYNAMIC CHARACTERISTICS2 tON 210 290 3 10 ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 350 380 12 13 V Ω typ Ω max Ω typ Ω max ± 0.25 ±2 ± 0.25 ±2 ± 0.25 ±6 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 µA typ µA max pF typ 0.005 2 Break-Before-Make Time Delay, tD Charge Injection 1 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –62 dB typ Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth CS (OFF) CD (OFF) CD, CS (ON) 680 5 5 5 MHz typ pF typ pF typ pF typ 0.001 µA typ µA max 130 150 45 50 10 POWER REQUIREMENTS IDD 1.0 NOTES 1 Temperature ranges are as follows. Y Version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 VS = 3.5 V, IS = –1 mA; Test Circuit 1 VS = 3.5 V , IS = –1 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; Test Circuit 2 VS = 1 V/4.5 V, VD = 4.5 V/1 V; Test Circuit 2 VS = VD = 1 V or 4.5 V, Test Circuit 3 VIN = VINL or VINH www.BDTIC.com/ADI 70 100 25 40 25 tOFF Test Conditions/Comments –3– RL = 300 Ω, CL = 35 pF VS = 3.0 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 3.0 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 3.0 V, Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz Test Circuit 8 RL = 50 Ω, CL = 5 pF, Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 5.5 V Digital Inputs = 0 V or 5.5 V ADG611/ADG612/ADG613–SPECIFICATIONS SINGLE SUPPLY1 (V DD = 3 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.) Parameter 25ⴗC ANALOG SWITCH Analog Signal Range On-Resistance (RON) 380 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 Y Version –40ⴗC to +85ⴗC 420 –40ⴗC to +125ⴗC Unit 0 V to VDD 460 V Ω typ VS = 1.5 V, IS = –1 mA; Test Circuit 1 VDD = 3.3 V VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 2 VS = 1 V/3 V, VD = 3 V/1 V; Test Circuit 2 VS = VD = 1 V or 3 V, Test Circuit 3 ± 0.25 ±2 ± 0.25 ±2 ± 0.25 ±6 nA typ nA max nA typ nA max nA typ nA max 2.0 0.8 V min V max ± 0.1 µA typ µA max pF typ VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2 V, Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz Test Circuit 8 RL = 50 Ω, CL = 5 pF, Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz 0.005 CIN, Digital Input Capacitance Test Conditions/Comments 2 2 DYNAMIC CHARACTERISTICS tON Break-Before-Make Time Delay, tD 130 185 40 55 50 Charge Injection 1.5 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –62 dB typ Channel-to-Channel Crosstalk –90 dB typ –3 dB Bandwidth CS (OFF) CD (OFF) CD, CS (ON) 680 5 5 5 MHz typ pF typ pF typ pF typ 0.001 µA typ µA max tOFF 230 260 www.BDTIC.com/ADI 60 65 10 POWER REQUIREMENTS IDD 1.0 VDD = 3.3 V Digital Inputs = 0 V or 3.3 V NOTES 1 Temperature ranges are as follows. Y Version: –40°C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –4– REV. 0 ADG611/ADG612/ADG613 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6.5 V Analog Inputs2 . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Digital Inputs2 . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 10 mA 3 V operation 85°C to 125°C . . . . . . . . . . . . . . . . . 7.5 mA Operating Temperature Range Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +125°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C 16-Lead TSSOP, θJA Thermal Impedance . . . . . . . 150.4°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG611YRU ADG612YRU ADG613YRU –40°C to +125°C –40°C to +125°C –40°C to +125°C Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) RU-16 RU-16 RU-16 PIN CONFIGURATIONS Table I. ADG611/ADG612 Truth Table ADG611 In ADG612 In Switch Condition 0 1 1 0 ON OFF www.BDTIC.com/ADI IN1 1 16 IN2 D1 2 15 D2 14 S2 S1 3 VSS 4 0 1 Switch 1, 4 OFF ON Switch 2, 3 ON OFF S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG611/ADG612/ADG613 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 13 VDD TOP VIEW GND 5 (Not to Scale) 12 NC Table II. ADG613 Truth Table Logic ADG611 ADG612 ADG613 –5– WARNING! ESD SENSITIVE DEVICE ADG611/ADG612/ADG613 TERMINOLOGY VDD Most Positive Power Supply Potential VSS Most Negative Power Supply Potential IDD Positive Supply Current ISS Negative Supply Current GND Ground (0 V) Reference S Source Terminal. May be an input or output D Drain Terminal. May be an input or output IN Logic Control Input VD (VS) Analog Voltage on Terminals D, S RON Ohmic Resistance between D and S ∆RON On Resistance match between any two channels, i.e., RONMAX – RONMIN. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the Switch “OFF” ID (OFF) Drain Leakage Current with the Switch “OFF” ID, IS (ON) Channel Leakage Current with the Switch “ON” VINL Maximum Input Voltage for Logic “0” VINH Minimum Input Voltage for Logic “1” IINL(IINH) Input Current of the Digital Input. CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD (OFF) “OFF” Switch Drain Capacitance. Measured with reference to ground. CD, CS(ON) “ON” Switch Capacitance. Measured with reference to ground. CIN Digital Input Capacitance tON Delay between applying the digital control input and the output switching on. See Test Circuit 4. tOFF Delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. www.BDTIC.com/ADI On Response Frequency Response of the “ON” Switch Insertion Loss Loss Due to the ON Resistance of the Switch –6– REV. 0 Typical Performance Characteristics–ADG611/ADG612/ADG613 600 150 ⴞ2.7V ON RESISTANCE – ⍀ ⴞ4.5V ⴞ3V 100 ⴞ5.5V 50 2 3 400 VDD = 3.3V 300 VDD = 4.5V 200 +125ⴗC 4 0 5 100 0 –40ⴗC 0 –5 –4 –3 –2 –1 0 1 2 V D , VS – V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V D , VS – V 1 0 0 CURRENT – nA CURRENT – nA +125ⴗC +85ⴗC ID (OFF) –1 –2 IS, ID(ON) –3 –4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V D , VS – V IS, ID(ON) –3 TA = 25ⴗC 1.5 120 –1.0 TIME – ns 80 tON,V DD = +5V 60 VSS = –5V tOFF,V DD = +5V 40 VDD = +5V VSS = –5V VSS = 0V 20 –1.5 tOFF,V DD = +5V VSS = –5V –2.0 –5 –4 –3 –2 –1 0 1 2 3 VS – V TPC 7. Charge Injection vs. Source Voltage REV. 0 VDD = –5V VSS = +5V tON,V DD = +5V 4 5 100 120 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE – ⴗC TPC 8. tON/tOFF Times vs. Temperature –7– TA = 25ⴗC –4 VSS = 0V –0.5 80 TPC 6. Leakage Currents vs. Temperature, Single Supply –2 0 60 0 100 VDD = +5V VSS = 0V 40 TEMPERATURE – ⴗC 120 VDD = +3V VSS = 0V 1.0 0.5 –5 VDD = 5V VSS = 0V –6 20 0 TPC 5. Leakage Currents vs. Temperature, Dual Supply TPC 4. On Resistance vs. VD(VS) for Different Temperatures, Single Supply 2.0 ID (OFF) –2 –4 –5 VDD = +5V VSS = –5V –6 20 40 60 80 100 0 TEMPERATURE – ⴗC –40ⴗC +25ⴗC 0 –1 www.BDTIC.com/ADI 100 5 IS (OFF) 1 300 4 2 IS (OFF) 400 3 TPC 3. On Resistance vs. VD(VS) for Different Temperatures, Dual Supply 2 VDD = 5V VSS = 0V 200 +25ⴗC 50 TPC 2. On Resistance vs. VD(VS), Single Supply 600 500 +85ⴗC VDD = 5V TPC 1. On Resistance vs. VD(VS), Dual Supply Qinj – pC 150 100 ⴞ5V 0 –5 –4 –3 –2 –1 0 1 VD, VS – V 200 VDD = 3V ATTENUATION – dB ON RESISTANCE – ⍀ ⴞ3.3V VDD = +5V VSS = –5V VDD = 2.7V 500 200 ON RESISTANCE – ⍀ 250 TA = 25ⴗC VSS = 0V TA = 25ⴗC ON RESISTANCE – ⍀ 250 VDD = 5V VSS = 0V –6 –8 –10 –12 –14 –16 –18 0.3 1 10 100 FREQUENCY – MHz 1000 TPC 9. On Response vs. Frequency ADG611/ADG612/ADG613 0 APPLICATIONS Figure 1 illustrates a photodetector circuit with programmable gain. With the resistor values shown in the circuits, and using different combinations of switches, gains in the range of 2 to 16 can be achieved. –10 ATTENUATION – dB –20 –30 –40 –50 C1 –60 R1 33k⍀ –70 VDD = –5V VSS = +5V TA = +25ⴗC –80 –90 0.3 1 10 100 FREQUENCY – MHz 5V D1 1k VOUT 2.5V R2 510k⍀ TPC 10. Off Isolation vs. Frequency 5V D1 S1 0 (LSB) IN1 D2 R6 R7 120k⍀ 120k⍀ S3 D3 R8 120k⍀ S4 D4 R9 120k⍀ –10 S2 ATTENUATION – dB –20 IN2 –30 –40 R3 510k⍀ IN3 –50 –60 (MSB) IN4 –70 GND –80 VDD = +5V VSS = –5V TA = 25ⴗC –90 –100 0.3 R4 R5 240k⍀ 240k⍀ 1 2.5V R9 120k⍀ GAIN RANGE 2 TO 16 www.BDTIC.com/ADI 10 100 FREQUENCY – MHz Figure 1. Photodetector Circuit with Programmable Gain 1k TPC 11. Crosstalk vs. Frequency –8– REV. 0 ADG611/ADG612/ADG613 Test Circuits IDS V1 S VS IS (OFF) D S A RON = V1/IDS A VS Test Circuit 1. On Resistance VDD S NC VD D NC = NO CONNECT Test Circuit 2. Off Leakage 0.1F VDD VSS S VIN ADG611 50% 50% VIN ADG612 50% 50% VOUT D CL 35pF RL 300⍀ IN 90% VOUT 90% GND tOFF tON www.BDTIC.com/ADI Test Circuit 4. Switching Times VDD VSS 0.1F VIN 0.1F 50% 0V VDD VS1 VS2 VIN VSS S1 D1 S2 D2 VOUT1 RL2 300⍀ IN1, IN2 CL2 35pF RL1 300⍀ VOUT2 VOUT1 CL 35pF 50% 90% 90% 0V GND tD tD Test Circuit 5. Break-Before-Make Time Delay RS VDD VSS VDD VSS S D VIN IN GND ADG611 VOUT ON CL 1nF VS OFF ADG612 VIN VOUT QINJ = CL ⴛ ⌬VOUT Test Circuit 6. Charge Injection REV. 0 90% 0V 90% VOUT2 ADG613 –9– A VD Test Circuit 3. On Leakage VSS 0.1F VS ID (ON) ID (OFF) D ⌬VOUT ADG611/ADG612/ADG613 VSS VDD 0.1F VDD 0.1F NETWORK ANALYZER VSS VDD VSS 0.1F 0.1F VDD S S 50⍀ D 50⍀ 50⍀ IN VSS VIN1 VS VS D VIN RL 50⍀ GND VIN2 VOUT D S NC GND OFF ISOLATION = 20 LOG RL 50⍀ VOUT VOUT CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG |VS/VOUT| VS Test Circuit 7. Off Isolation Test Circuit 8. Channel-to-Channel Crosstalk VDD VSS 0.1F 0.1F VDD NETWORK ANALYZER VSS S 50⍀ IN VS D VIN RL 50⍀ GND VOUT VOUT WITH SWITCH www.BDTIC.com/ADI INSERTION LOSS = 20 LOG VOUT WITHOUT SWITCH Test Circuit 9. Bandwidth –10– REV. 0 ADG611/ADG612/ADG613 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0433 (1.10) MAX 8ⴗ 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0ⴗ BSC 0.0075 (0.19) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) www.BDTIC.com/ADI REV. 0 –11– PRINTED IN U.S.A. www.BDTIC.com/ADI –12– C02753–0–1/02(0)