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TCAM Dynamics System & Device Tutorial Renesas Electronics America Inc. Rob Raghavan, Computing and Communications Date June 24, 2010 Rev. 0.00 © 2010 Renesas Electronics America Inc. All rights reserved. 00000-A Packet Processing Dynamics 2 © 2010 Renesas Electronics America Inc. All rights reserved. Packet Switching Networks 3 © 2010 Renesas Electronics America Inc. All rights reserved. Gig E Switch Architecture Clock Distribution Clock Distribution Backplane Fabric / FPGA Backplane Fabric / ASIC © 2010 Renesas Electronics America Inc. All rights reserved. Packet Processor Network Chipset Processor (NPU) TCAM TCAM Associative Data SRAM Buffer SRAM Packets Out 4 CPU Packets In •ASIC •FPGA 3rd party NPU •Broadcom •Cavium •EZChip •Marvell •Wintegra •Xelerated CPU Associated Data Data Packet Analogy Payload Priority Source Address Steve B 200 Park Ave New York, NY John Q 100 Main St San Jose, CA 95135 USA Destination Address 5 © 2010 Renesas Electronics America Inc. All rights reserved. Data Packet Description Packet Header Source & Destination Addresses Packet Payload QoS, ACL, VPN, Billing, Flow Monitoring Data Voice Video Layer 2-4 (SPI) Layer 7 (DPI) 250-500 bits 5K+ bits • 10-40 Gbps • 10 Gbps • Packet HEADER Inspection • Packet PAYLOAD Inspection • Layer 2-4 (Network Awareness) • Layer 7 (Content Awareness) Malware & Intrusions •TCAMs can search all layers in a data packet and determine it’s destination & priority •This is becoming more important with Voice, Video, & Data transmissions 6 © 2010 Renesas Electronics America Inc. All rights reserved. Applications Packet Forwarding Shallow Packet Inspection (SPI) Extracts basic protocol information such as IP addresses (source, destination) 7 © 2010 Renesas Electronics America Inc. All rights reserved. Packet Classification Deep Packet Inspection (DPI) & SPI The process of categorizing packets into “flows” in an internet router is called packet classification Forward Information Base (FIB) Search TCAM 3 (Pointer) (Ingress) Header Payload trailer 1 Header Network Processor (NPU) NSE Payload Associative Data QDR SRAM trailer Source & Destination Address 4 (Next Switch Address) (Egress) 5 (Packet sent to next destination) Unicast Forwarding Header Payload trailer Forwarding is the relaying of packets from one network segment to another by nodes in a computer network 8 © 2010 Renesas Electronics America Inc. All rights reserved. Multicast Forwarding Packet Classification Search All packets belonging to the same flow obey a pre-defined rule and are processed in a similar manner by the router. TCAM 3 (Pointer) Associative Data QDR SRAM QoS, QoE, ACL, SLA (Ingress) Header Payload trailer 1 Network Processor (NPU) Header Payload trailer NSE 4 (Next Switch Address, QoS, QoE, ACL, SLA) (Egress) Priority Header Payload trailer 2 Quality of Service QoS provides preferential delivery service for the applications that need it by ensuring sufficient bandwidth Packet filtering Policy routing Accounting & billing Traffic rate limiting Header Payload trailer Traffic shaping Intrusion detection Packet classification is needed for services that require the capability to distinguish and isolate traffic in different flows for suitable processing. 9 © 2010 Renesas Electronics America Inc. All rights reserved. Access Control List An ACL is a common means by which access to and denial of services is controlled DRM Malware Protection IPS Application Acceleration Billing IPv6 QoS ACL Security 10+ Gbps The Increasing Need for Packet Processing Layers 2-4 10 © 2010 Renesas Electronics America Inc. All rights reserved. Layers 4-7 The Increasing Need for Deep Packet Processing 2005/06 L2-4 Security • Ingress ACL • Egress ACL L2-4 QoS • Policing (per protocol or per TOS byte) • ACL-based RTF • TCP-SYN Protection • PBR • Ctrl plane Policing • Policing • Video-on-demand • Shaping • IPTV • Packetized Voice • Gaming • Aggregation Level 1 • Aggregation Level 2 • Mobile services Billing L2-4 Routing • Router ACL • VLAN ACL • IPSec • ICMP Redirect 2010 • IPv4 database • IPv6 database L7 Security • IPS/IDS • Anti-Virus • Anti-Spam • Unified Threat Mgmt • Malware Protection L7 QoS/ Routing • Application Acceleration • Protocol Identif. • Datacenter Load Balancing 11 © 2010 Renesas Electronics America Inc. All rights reserved. TCAM Architecture & Portfolio 12 © 2010 Renesas Electronics America Inc. All rights reserved. What is a TCAM CAM stands for Content Addressable Memory In a standard memory device the operating system provides an address, and receives the data stored at the supplied address With a CAM, the operating system supplies the data, and the CAM returns a list of addresses where the data is stored, if it finds any A CAM searches the entire memory in one operation, so it is considerably faster than RAM Any switch capable of forwarding Ethernet frames at line-speed gigabit is using CAMs for lookups Binary CAMs search only for ones and zeros; a simple operation. MAC address tables in switches commonly get stored inside binary CAMs A TCAM is a Ternary CAM. This allows the operating system to match a third state, "X." The X state is a "mask," meaning its value can be anything. This lends itself well to networking, since netmasks operate this way. To calculate a subnet address we mask the bits we don't care about 13 © 2010 Renesas Electronics America Inc. All rights reserved. TCAM Architecture 0001 1101 0101 1110 1101/20 next-hop 30.40.50.62 0001 1101 0101 1110 1101 1100 1000 0110 0001 1101 0101 1110 1101 XXXX XXXX XXXX 14 © 2010 Renesas Electronics America Inc. All rights reserved. TCAM Roadmap ~ CY09 CY10/1H ASSP Quad Search 360Msps 20M CY10/2H ASSP 18M ASSP CY11/1H Dual Search 125Msps Dual Search 125Msps CY11/2H ASSP 80M ASSP 40M 4.5M ASSP CAM ASSP 5M Interlaken 600Msps Interlaken 600Msps Interlaken 600Msps Custom Custom Custom Custom Custom TCAM Gen 2 –18M Custom TCAM Gen 3 –18M Custom TCAM Gen 4 –20M Custom TCAM Gen 5 –80M Custom Custom Custom Custom Custom TCAM Gen 2 – 4.5M Custom TCAM Gen 3 – 4.5M Custom TCAM Gen 4 – 10M Custom TCAM Gen 5 – 40M Custom Custom Custom Custom TCAM Gen 2– 2.5M Custom TCAM Gen 4 – 5M Custom TCAM Gen 5– 5M Custom CAM 15 CY12/1H © 2010 Renesas Electronics America Inc. All rights reserved. CY12/2H TCAM2 products CAM2CR_256 CAM2CR_256 CAM2CR_256 Supplier Renesas Renesas Part No Cisco Part No Cisco BU Max Lookup Rate (MLU/s) Access Size (bits) Technology Package R8A20100ABG 15-8969-01 DSBU 62.5 4.5Mb 0.15um 256PBGA Power (W) Core Voltage I/O Voltage <2W 1.5V 2.5V (3.3V tolerant) CMOS 16 Renesas Renesas R8A20100ABG-IT R8A20100ABG-IG 15-11695-01 15-12039-01 DSBU DSBU 62.5 62.5 4.5Mb 4.5Mb 0.15um 0.15um 256PBGA 256PBGA (PbFree) <2W <2W 1.5V 1.5V 2.5V 2.5V (3.3V tolerant) (3.3V tolerant) CMOS CMOS © 2010 Renesas Electronics America Inc. All rights reserved. ToyCAM ToyCAM TurboCAM CAM2LP-18M Renesas Renesas rev1.1 Renesas Renesas R8A20120ABG 15-9634-01 DSBU 62.5 2.25Mb 0.15um 256PBGA R8A20120ABG-IT 15-11360-01 DSBU 62.5 2.25Mb 0.15um 256PBGA R8A20300ABG 15-9786-01 DSBU 125 4.5Mb 90nmLP 256PBGA R8A20320BG-A 15-9770-04 ISBU/ERBU 78 18Mb 90nmLP <1.2W 1.5V 2.5V (3.3V tolerant) CMOS <1.2W 1.5V 2.5V (3.3V tolerant) CMOS 2W~3W 1.2V 1.2V 2.5V 1.8V 1.2V TCAM3 products CAM3CR-4.5M 17 Supplier rev1.1 Renesas Renesas Part No Cisco Part No Cisco BU Max Lookup Rate (MLU/s) Access Size (bits) Technology Package R8A20220ABG 15-10068-01 GSBU 125 4.5Mb 130nm 304PBGA Power (W) Core Voltage I/O Voltage 3.6W 1.2V 2.5V (3.3V tolerant) CMOS CAM3CR rev1.1 Renesas rev1.2 Renesas CAM3CR-4.5M rev1.2 Renesas R8A20310ABG-A R8A20310BBG-A R8A20310BBA-A 15-10070-02 15-10764-02 15-10365-04 GSBU HFR GSR 125 125 75 18Mb 18Mb 18Mb 90nmG 90nmG 90nmG 360FCBGA 360FCBGA 360FCBGA (27mm) (27mm) (25mm) 7.5W 7.5W 3W 1.0V 1.0V 1.0V 2.5V 2.5V 2.5V (3.3V tolerant) (3.3V tolerant) (3.3V tolerant) CMOS CMOS CMOS © 2010 Renesas Electronics America Inc. All rights reserved. 360PKG Renesas R8A20330BG 15-10872-01 ISBU/DCBU 125 4.5Mb 90nmG 360PBGA 1.0V 2.5V (3.3V tolerant) CMOS TCAM4 products CAM4-20M CAM4-10M CAM4-5M Supplier Renesas Renesas Renesas Renesas Part No Cisco Part No Cisco BU Max Lookup Rate (MLU/s) Access Size (bits) Technology Package R8A20420BG 15-12241-01/'15-10019-01 CRBU/GSBU 250 20Mb 65nmG 576FCBGA (27mm) 16W 1.0V R8A20421BG 15-12235-01 GSBU 250 10Mb 65nmG 576FCBGA (27mm) R8A20422BG 15-11490-01 GSBU 250 5Mb 65nmG 576FCBGA (27mm) 1.0V 1.0V 1.2V CSSPL 1.2V CSSPL 1.2V CSSPL Power (W) Core Voltage I/O Voltage 18 © 2010 Renesas Electronics America Inc. All rights reserved. Renesas TCAM Portfolio Quad Search TCAM Dual Search TCAM Dual Search TCAM R8A20410BG TBD TBD 20M 4.5M 18M Parallel Search Engines 4 banks 2 banks 2 banks Clock Frequency 360MHz 250MHz 250MHz 40b/80/160/320/480/640 72/ 144/ 288 72/ 144/ 288 Search Rate 360Msps @ Single 720Msps @ Quad 125Msps @ Single 250Msps @ Dual 125Msps @ single 250Msps @ dual Core Voltage 1.0V+/- 5% 1.0V+/- 5% 1.0V+/- 5% I/O Voltage 1.5V +/- 5% (HSTL) 2.5V +/- 5% (SSTL2) 2.5V +/- 5% (SSTL2) Data Bus 80bit (DDR) 72bit (SDR) 72bit (SDR) Package 576pins FCBGA 360pins PBGA 360pins FCBGA Datasheet Now August August Models Now November November Sample Now December December August Q1 2011 Q1 2011 Part number Density Search Mode (bit width) Production 19 © 2010 Renesas Electronics America Inc. All rights reserved. Quad Search Overview (20Mb TCAM) Description Comments Capacity 20M Full Ternary CAM 32Blks (80bit x 8K each, 80bit x 256K entries total) Search 4 searches in parallel out of 28 configurable tables. 8 search profiles switchable on-the-fly Search Key 40b L / 40b H / 80b / 160b / 320b / 480b / 640b 40b search uses 80b entry w/special high & low masks Data I/F 80-bit DDR Input only, read data comes from result IND bus Result I/F Single 20-bit Index bus IND Output only Frequency 360MHz Single table 160b = 360 Msps max, quad search 720Msps Context Registers 128 x 320-bit context registers Write Mask 7 write masks Data Block Mask 8 DBM per data block Search Key Config Search Key can be compacted in 80b resolution Valid Bit A Valid bit for each 80b entry WDS Source Synchronous Clock for DDR input signals x3 2 for 80b bus & 1 for controls Clock Signals All complementary clocks Similar to QDR Data Alignment Data Bus center-aligned. Result IND Bus programmable to center or edge-aligned Cascade 2 devices maximum 40Mb total Impedance Control Output Impedance Control ZC similar to QDR ODT On-Die-Termination Can be turned off Parity Interface parity support. 2-bit for D and 1-bit for IND Array parity support plus Array Integrity Scanner to scan for SER 4-bit per 80b segment Latency 26 cycles For cascade mode = 26 + 8 = 34 cycles Power 1.0V Core 1.5V HSTL I/O & PLL © 2010 Renesas Electronics America Inc. All rights reserved. 20 Package 576 FCBGA Quad Search Block Diagram WDS[0]/WDS#[0] P_THRU F_SEL PLL CAM_CLK TMS JTAG Search Key Configuration PARITY CONTROLLER Block31 Block30 OP/TERS[3:0] Context Register (80bits X 4) WDS[2:0]/ WDS#[2:0] D[79:0] DP[1:0] Priority Encoder For table A Block2 Block1 Block0 PARITY_ERR RDS/RDS# IND[19:0] MAT Search Mask Priority Encoder For table B CAM Array Priority Encoder For table C Search Key Device Register TCK TDI TDO TRST O_VD Priority Encoder For table D C_SEL OP_ENA Write Mask Write Data Cascade RSTL 21 © 2010 Renesas Electronics America Inc. All rights reserved. CI_RDS/RDS# CI_IND[19:0] CI_MAT CI_O_VD Quad Search Key Configuration Original Search Key [319:240] [239:160] TableA SKCR SKCR 1 Internal Search Key 1 1 1 1 0 [239:160] [79:0] TableB SKCR 319 [319:240] [159:80] [159:80] [79:0] 320bit Search Key 1 TableC SKCR 0 0 0 159 [319:240] 0 [239:160] 160bit Search Key 0 TableD SKCR 0 79 1 0 [79:0] 80bit Search Key 1 0 0 159 [319:240] 0 [79:0] 160bit Search Key Based on SKCR selection, 4 individual search keys can be generated, one for each table. 22 © 2010 Renesas Electronics America Inc. All rights reserved. 1 Quad Search Context Register Context Registers are effective in reducing I/O bandwidth requirement for long search keys Renesas TCAM has three methods of search key input. 1) From external D-bus 2) From internal Context Register ( consists of 80bit x 4segments ) 3) Combination of external D-bus & internal context Register. From Context Registers From D bus D[79:0] [319:240] [239:160] [159:80] [79:0] [319:240] 127 CR_SEL[6:0] [319:240] [239:160] [159:80] [79:0] KS_ENA KS_ENA KS_ENA KS_ENA KS_ENA KS[2:0] KS[2:0] KS[2:0] KS[2:0] KS[2:0] [319:240] LAST_KS If KS_ENA is “1”, Context register is overwritten by external D-bus. Overwrite OP[3:0] (WM_SEL) (SP_SEL) OP_ENA [319:240] 23 [239:160] © 2010 Renesas Electronics America Inc. All rights reserved. [239:160] [159:80] [79:0] [239:160] [159:80] [79:0] 0 [159:80] [79:0] Quad Search Cascaded System Input Side WDS/WDS#, OP_ENA, OP, D, DP, CR_SEL, KS, KS_ENA, LAST_KS CI_RDS/ CI_RDS# RDS/ RDS# IND CI_IND ASIC/NPU or FPGA CI_RDS/ CI_RDS# RDS/ RDS# IND CI_IND CI_O_VD O_VD CI_O_VD O_VD CI_MAT MAT CI_MAT MAT 0 ID 1 ID 1 OALIGN 0 OALIGN CAM-0 Higher priority CAM CAM-1 Lower priority CAM Output Side 24 © 2010 Renesas Electronics America Inc. All rights reserved. Renesas Value & Differentiation 25 © 2010 Renesas Electronics America Inc. All rights reserved. Custom TCAM Cell Memory cell is the most cost sensitive component in CAM LSI, Renesas’ design is based on customized cell instead of generic rules In any process technology, Renesas CAM array will have a significant die size advantage 1bit cell 1bit cell 130nm TCAM 26 90nm TCAM © 2010 Renesas Electronics America Inc. All rights reserved. 1bit cell 65nm TCAM Proprietary Repair Technology Although TCAM cell is SRAM based, defect density of TCAM cell is about 2x of SRAM Replacing defective cells with redundant cells is not as trivial as in regular memory due to Priority consideration in search Renesas Repair technology is able to bring TCAM yield up to SRAM level 27 © 2010 Renesas Electronics America Inc. All rights reserved. Sub-Core Pre-charge Technology Constant pre-charge and discharge of Match-Line Sense Amplifiers during search consumes a lot of power By reducing the sense amp pre-charge voltage to ½ of core voltage, can effectively reduce overall power consumption by 25%. 90nm 65nm 25% 65nm & New MA 0.000 0.500 1.000 Current ( A ) 28 © 2010 Renesas Electronics America Inc. All rights reserved. 1.500 2.000 MLA MLB GML SL GSL DB Others TCAM Market & Applications 29 © 2010 Renesas Electronics America Inc. All rights reserved. Markets & Customers Core Metro Access/Enterprise Access: - Active Ethernet Access Switches - IPDSLAM - GPON OLT, 10GPON OLT - Core Routers - Multiservice Provisioning Platforms - Carrier Ethernet Switch/Routers - Metro Aggregation Switches TCAM Alcatel-Lucent Avaya Brocade Calix Ciena Cisco Cloudshield Enterasys 30 Ericsson Extreme Force10 F5 Networks GEIP HP Huawei Enterprise: - Advanced Stackable Switches - Enterprise Chassis Switches SRAM & DRAM Juniper Kontron Nokia/Siemens Palo Alto Tellabs © 2010 Renesas Electronics America Inc. All rights reserved. Cisco: 40% ASSP: 60% TCAM TAM Cisco: 72% ASSP: 28% $250 $M/year $200 $150 $100 $50 $2008 2009 TCAM2 31 2010 TCAM3 © 2010 Renesas Electronics America Inc. All rights reserved. 2011 TCAM4 / TCAM5 2012 ASSP 2013 Netcam 2014 TCAM Competition 32 © 2010 Renesas Electronics America Inc. All rights reserved. Netlogic Product Portfolio 2000-2004 2005 2006 2007 2008 2009 NSE3128 NL3100 NETL7 NL8000 NL9000 NL7512 NSEX256 NL6000 NL6000XS NLS1005 NLS205 NL33100 CFP3256 NL71024 NL8256 NL71024XT NL8256 NSEx512 NL3140LV TCAM3 NL56615 NLP10142 NL5000GLQ Netcam Cypress NL3380 NLP1220 Cypress TCAM2 NL91024XT IDT Ayama 10000 Aeluros NLS2000 TCAM2 Ayama 20000 Puma SerDes NL91024XT TCAM4 NSE70000 PCI Express PHY NLS2000 route accelerator Sahasra 50000 SATA-II PHY TCAM4 75S10000A XAUI PHY NLP10000 75S10000B NLP2040 RMI NLP3040 XLP uP XLR Thread uP XLS uP Alchemy uP 33 © 2010 Renesas Electronics America Inc. All rights reserved. TCAM Cross reference 34 Netlogic Density I/F Renesas NL6128 4.5M 72 bit Dual Search 4.5M NL7512 20M 72 bit Dual Search 18M NL9512 20M 80 bit Quad Search 20M R8A20410BG IDT Density I/F Renesas 75P52100 4M 72 bit Dual Search 4.5M 75K72100 18M 72 bit Dual Search 18M 75S10020B 20M 80 bit Quad Search 20M R8A20410BG © 2010 Renesas Electronics America Inc. All rights reserved. TCAM Ecosystem Partnerships 35 © 2010 Renesas Electronics America Inc. All rights reserved. Gig E Switch Architecture Clock Distribution Clock Distribution Backplane Fabric / FPGA Backplane Fabric / ASIC © 2010 Renesas Electronics America Inc. All rights reserved. Packet Processor Network Chipset Processor (NPU) TCAM TCAM Associative Data SRAM Buffer SRAM Packets Out 36 CPU Packets In ASIC FPGA 3rd party NPU •Broadcom •Cavium •EZChip •Marvell •Wintegra •Xelerated CPU Associated Data Xelerated HX300 Family 37 © 2010 Renesas Electronics America Inc. All rights reserved. Cavium Networks OCTEON Roadmap OCTEON OCTEON Plus OCTEON II CN68XX Up to 1500 MHz 16-32 cnMIPS II cores 4MB L2 Cache, 4xDDR3 16 - 32 Cores 8 - 16 Cores 2-8 Cores 1-2 Cores 38 CN7xxx Family cnMIPS III cores CN58xx CN38xx Up to 600 MHz 4-16 cnMIPS64 cores 1MB L2 Cache Up to 800 MHz 4-16 cnMIPS64 cores 2MB L2 Cache CN56xx Up to 800 MHz 6-12 cnMIPS64 cores 2MB L2 Cache CN36xx Up to 600 MHz 6 cnMIPS64 cores 512KB L2 Cache Full SW Compatibility CN66XX Up to 1500 MHz 8-16 cnMIPS II cores 4MB L2 Cache, 2xDDR3 CN54xx CN63XX Up to 700 MHz 4-6 cnMIPS64 cores 1MB L2 Cache Up to 1500 MHz 2-6 cnMIPS II cores 2MB L2 Cache, 1xDDR3 CN31xx CN52xx CN62XX Up to 500 MHz 1-2 cnMIPS64 cores 256KB L2 Cache Up to 800 MHz 2-4 cnMIPS64 cores 512KB L2 Cache Up to 1500 MHz 2-4 cnMIPS II cores 1MB L2 Cache, 1xDDR3 CN30xx CN50xx CN60XX Up to 500 MHz 1-2 cnMIPS64 cores 64-128KB L2 Cache Up to 700 MHz 1-2 cnMIPS64 cores 128KB L2 Cache Up to 1000 MHz 2 cnMIPS II cores 256KB L2 Cache, 1xDDR3 2007-2008 2009-2010 2005-2006 Production OCTEON III Sampling In Design Planned © 2010 Renesas Electronics America Inc. All rights reserved. 2X+ Performance Application Acceleration V4 50%+ reduction in Power Consumption 2011-2012 Xelerated & Cavium Xelerated HX NPU Cavium Octeon NPU L2-4 processing L2 - L7 processing Packet Header QoS, ACL, VPN, Billing, Flow Monitoring Data Voice Layer 22-4 5K+ bits SRAM Table • 10 Gbps DRAM DRAM Memories • Packet PAYLOAD Inspection TCAM Gbps • Packet HEADER Inspection Buffers • Layer 2-4 (Network Buffers DRAM Buffers (HX330) DRAM Fabric I/F Fabric VOQ Fabric I/F Fabric VOQ Fabric I/F Fabric VOQ 4x SGMII or XAUI Cavium CN58XX CN68xx L2-L4 Security •Router ACL •VLAN ACL •IPSec •ICMP Redirect 39 L2-4 QoS •Policing •Shaping •Packetized Voice © 2010 Renesas Electronics America Inc. All rights reserved. Stack i/f HX320 HX330 Stack i/f 48x SGMII Octal PHYv RJ45 HX320 HX320 HX330 HX320 HX330 HX330 Buffer Memories (HX330) • Layer 7 (Content Awareness) Awareness) DRAM Malware & Intrusions Layer 7 L4-L7 Pizzabox L7 Security •IPS/IDS •Anti-Virus •Anti-Spam 6 RJ45 SRAM DRAM SRAM DRAM TCAM DRAM TCAM TCAM 250250-500 bits RJ45 Line Card Tables, counters, meters Tables,SRAM counters, meters• 10-40 Video Octal PHY 48 CPU RJ45 Source & Destination Addresses Packet Payload L7 QoS •Application Acceleration •Protocol Identification •. Datacenter Load Balancing TCAM Sales Strategy 40 © 2010 Renesas Electronics America Inc. All rights reserved. Questions for Customers What is their application? What density is required? (e.g. 20Mbit table size) What performance is required? (MSPS – million searches per second) What is the search key width? What is the I/O frequency / Type (e.g. 360MHz, 1.5V HSTL) What is the design power budget? Are they willing to cascade devices for increased density? Are they currently using a TCAM. If so what are its characteristics (performance, density, pinout, power, interface) What type of Network Processor (NPU) is used (ASIC, FPGA, or commercial NPU from Cavium, Broadcom, Xelerated, etc) 41 © 2010 Renesas Electronics America Inc. All rights reserved. Renesas TCAM Value Proposition Let them know that Renesas has deep experience in TCAM design & production We are a leading supplier of proprietary TCAMs to the world’s largest network equipment vendor We have patented technology that significantly reduces cost and power Explain that Renesas has leveraged this experience to introduce the 20M Quad Search TCAM to the general market Explain that Renesas has a rich roadmap that will cover multiple densities and performance levels Explain that Renesas is partnering with leading NPU vendors Cavium and Xelerated for interoperability Explain that only Renesas offers both TCAM and other high speed memory like QDR SRAM and LLDRAM 42 © 2010 Renesas Electronics America Inc. All rights reserved. Call to action Focus on networking equipment vendors (similar to Alcatel, Juniper, Brocade, Extreme, etc) Find Cavium & Xelerated NPU based designs Target high end Enterprise, Metro, Core Switches & Routers All TCAM datasheet / model / pricing requests should be sent to [email protected] , 408-588-6306 Make sure to get an NDA signed Find out if they use QDR/DDR SRAM or LLDRAM for packet buffering and packet lookup 43 © 2010 Renesas Electronics America Inc. All rights reserved. Renesas Electronics America Inc. © 2010 Renesas Electronics America Inc. All rights reserved. SPI - Forwarding Table Dynamics In an Internet router, we find the next hop address for a packet by performing a Longest Prefix match (LPM) on the forwarding table Assume (IPv4) forwarding table has 4 entries as follows: 0010 1100 0011 0/13 next-hop 10.20.30.45 0001 1101 /8 next-hop 20.30.40.54 0001 1101 0101 1110 1101/20 next-hop 30.40.50.62 */0 next-hop 50.50.50.100 Ingress packet has (IPv4) destination address: 0001 1101 0101 1110 1101 1100 1000 0110 LPM gives us the correct next hop : 30.40.50.62. 45 © 2010 Renesas Electronics America Inc. All rights reserved. SPI - Statistical vs Hardware Search Several statistical data structures can be used in the implementation of longest prefix match. For example : PATRICIA Level and/or Path Compressed Tries Skip Lists Hash Tables As number of prefixes in forwarding table increases, the trie becomes larger and lookups take longer ASICs that use tries—digital trees for storing strings (in this case, the prefixes)—require four to six memory accesses for a single route lookup and thus have higher latencies TCAMs are able to accomplish deterministic, single-cycle search 46 © 2010 Renesas Electronics America Inc. All rights reserved. SPI – ACL / QoS Access Control List (ACL) Network security systems operate by allowing selective use of services An ACL is a common means by which access to and denial of services is controlled On network devices such as Routers and firewalls, they act as filters for network traffic Quality of Service (QoS) QoS provides preferential delivery service for the applications that need it by ensuring sufficient bandwidth QoS allows the use of existing resources efficiently and ensure the required level of service without reactively expanding or over-provisioning their networks 47 © 2010 Renesas Electronics America Inc. All rights reserved. DPI (L4-L7) DPI can be evoked to look through Layer 2-7 This includes headers and data protocol structures as well as the actual payload of the message DPI can identify and classify traffic based on a signature database that includes information extracted from the data part of a packet, allowing finer control than classification based only on header information Lawful intercept -Obtaining communications network data pursuant to lawful authority Policy definition and enforcement - Service providers obligated by the service level agreement (SLA) with their customers to provide a certain level of service, and at the same time enforce an acceptable use policy Targeted advertising - monitor web-browsing habits in a very detailed way allowing them to gain information about their customers' interests Quality of service (QoS) - ensure equitable bandwidth to all users by preventing network congestion. Higher priority can be allocated to a VoIP or video conferencing call which requires low latency versus web browsing which does not Tiered services - implement tiered service plans, to differentiate "walled garden" services from "value added" DPI can be effective against buffer overflow attacks, Denial of Service (DoS) attacks, sophisticated intrusions 48 © 2010 Renesas Electronics America Inc. All rights reserved. DPI Market Demand DPI is key for ISPs and carriers for the deployment of triple play and new services Analyze their current network situations and their readiness to receive rich, demanding, consuming and real time traffic Analyze their subscribers' behavior, such as traffic patterns generated per hour/day/week and measure the over-the-top services being used by subscribers To set up global application control policies - such as the total quantity of P2P or VoIP/Skype traffic To set up per subscriber SLAs/policies, in order to enforce smarter services, volume/duration-based billing, be more competitive, provide better Quality of Experience (QoE), and increase ARPU. 49 © 2010 Renesas Electronics America Inc. All rights reserved. The Growing Need for Application/Protocol Identification Network bandwidth consumption by protocol HTTP 17% P2P 65% Other L4 8% E-Mail 4% News 3% Other 3% Source: Sandvine, 2006 50 © 2010 Renesas Electronics America Inc. All rights reserved. Revenue $350 77% $300 YoY Growth $200 $150 IPO July 2004 $M $250 19% 28% $100 $50 $Market Cap 51 2004 2005 2006 2007 2008 2009 $0.32B $0.75B $1.17B $0.98B $1.03B $1.28B © 2010 Renesas Electronics America Inc. All rights reserved. 2010 TCAM4 for Cisco Platforms Device Type ERBU Edge Routing CRBU Core Routing 5M FP-5G Mara/MaraCR Spiderwoman Juhani 10M FP-10G Luke/Barry/Flash Callista 20M FP-20G FP-40G Taiko 80M 52 GSBU Gigabit Systems © 2010 Renesas Electronics America Inc. All rights reserved. Callista Obelisk/Getafix DSBU Desktop Switching Whales Whales How OSI Works The main idea in OSI is that the process of communication between two end points in a telecommunication network can be divided into layers Each layer adding its own set of special, related functions. Each communicating user or program is at a computer equipped with these seven layers of function. So, in a given message between users, there will be a flow of data through each layer at one end down through the layers in that computer At the other end, when the message arrives, another flow of data up through the layers in the receiving computer and ultimately to the end user or program. 53 © 2010 Renesas Electronics America Inc. All rights reserved. Cavium Networks Overview Founded 2001 NASDAQ (CAVM) IPO 2007 500 Employees 2009: $101M revenues, 16% YoY growth Strong Balance Sheet and Financials: $66+M Cash, No Debt – strong cash flow Pioneer and leader in Embedded Multi-core processors Addressing Multi-billion dollar Networking, Communications, Broadband and Consumer markets. MIPS and ARM based Processor SOCs 10 / 10 Top Networking and Security Vendors use Cavium Intelligent Processors for Networking, Wireless, Storage and Video 54 54 © 2010 Renesas Electronics America Inc. All rights reserved. OCTEON™ Plus CN58XX Product Family Core: cnMIPS64 @ 600-800MHz • 4 , 8, 12, or 16 cores • 32K-I, 16K-D L1 Cache, 2K Write Buffer w/ Auto Single Bit Error Correction SPI 4.2 • 2MB L2 Cache w/ ECC or Memory Controllers: 4x RGMII • 72/144b DDR2-800, 16GB Max, ECC • 2x 18bit RLDRAM2 , 1GB Max. (Opt) Flexible High-Speed Interfaces: • 2x [4x RGMII or SPI 4.2] Boot/ • 133MHz 64b PCI-X Flash, On-chip Coprocessors: CF, GPIO, • Crypto Security, RNG, TCP/IP & DUART, I2C Timer Offload, RegEx (DPI), De/Compression (ZIP), 64-bit DMA, Secure Key Storage 133MHz Data Plane Acceleration: • Schedule/Synchronize/Order (SSO), Packet Input Processor (PIP/IPD), Packet Output Processor (PKO), Free Pool Allocator (FPA) Max Power: 17-40W Process Technology: 90nm TSMC Samples: Now Production: Now Package: 1521 FCBGA SPI 4.2 or 4x RGMII Optional 2x18-bit RLDRAM2 32x RegEx Engines Packet Interface Secure Vault Scheduler/ Sync. Order Hyper Access Low Latency Memory Controller Crypto Security Misc I/O PCI-X Packet Input TCP Unit I/O Bridge Compress /Decomp Packet Output Packet Interface CN58XX Packet MIPS64 32K Icache r2 16K Dcache Integer 2K Write Buffer Core 4 to 16 cnMIPS64 cores Crypto Security MIPS64 32K Icache r2 16K Dcache Integer 2K Write Buffer Core Coherent, Low Latency Interconnect 2MB Shared L2 Cache Hyper Access Memory Controller I/O Bus Device CN5830 CN5840 CN5850 CN5860 55 cnMIPS Cores 4 8 12 16 LP: Low Power version available for 600MHz I: Industrial temp versions available © 2010 Renesas Electronics America Inc. All rights reserved. Packet DDR2 up to 800MHz 72 or 144-bit wide w/ECC OCTEON II CN68XX Product Family Key Features 16 to 32 cnMIPSII cores MIPS64 R2 + 80 enhanced instructions Up to 37 way L1 associativity Hyperconnect Crossbar & I/O interconnect with up to 8Tbps Low latency deterministic performance Most Advanced HW acceleration including: 40Gbps+ security, TCP, packet processing, QoS 15Gbps 3rd gen DPI 20Gbps+ Compression 80Gbps+ RAID/XOR/DeDup Schedule/Synch ordering engine for unlimited flows Fully SW compatible with OCTEON Plus Power Optimizer Embedded Virtualization DMA x20 Gen2 SERDES x4 If x8 FPA Application Acceleration Manager Timers Compression /Decomp v3 RAID/ XOR TCP XAUI/DXAUI Or 4x SGMII Power Optimizer Interlaken x4 If x4 (ILK-LA Pass 2) Crypto Packet Security PCIe v2 x4 2x RXAUI or 1x XAUI x4 XAUI/DXAUI or 4x SGMII If x8 x4 CN68XX Crypto Packet Security MIPS64 r2 16-32 cnMIPS II Integer Core cores 37K Icache 37K Icache MIPS64 r2 Integer Core XAUI or 4x SGMII 32K Dcache 32K Dcache PCIe v2 Write Back Buffer Write Back Buffer If x4 Secure Vault Misc I/0 HFA (Pattern Matching) Packet Input v2 I/O Network Packet Output v2 2x Hyper Access Memory Controller v2 2x 72b Coproc Network 4MB Shared L2 Cache 2x Hyper Access Memory Controller v2 2x 72b SCP = Secure Communications Processor: Includes encryption, networking, TCP acceleration and QoS AAP = Application Acceleration Processor: Includes SCP features plus HFA RegEx acceleration and compression/decompression 56 © 2010 Renesas Electronics America Inc. All rights reserved. Boot/Flash (NOR & NAND), CF, 16 GPIO, DUART, 2x I2C, 1x USB 2.0 w/PHY, 1xRG/MII HX330 Family HX320 Family HX310 Family 57 © 2010 Renesas Electronics America Inc. All rights reserved. Current Products 40G Network Processors – X10q (20G full-duplex; SPI-4.2) – X11 (10/20G full duplex; SPI-4.2, GE, 10GE) Metro Ethernet Switch – Xelerated/Dune Metro Ethernet Switch (24xGE + 2x10GE uplink) Reference Design Kits – X10q RDK – X11 RDK Metro Ethernet Reference Application – Forwarding plane for PB, PBB, VPLS, MPLS, IPv4 and IPv6 Software Development Kit – Integrated Development Environment (editor, compiler, linker, debugger, ...) – Clock-cycle Accurate Simulator Services – Training, Application coding, Integration services 58 © 2010 Renesas Electronics America Inc. All rights reserved. Enterprise Chassis System Line Card Line Card Tables, counters, meters Line Card Tables, counters, meters Line Card Tables,SRAM counters, meters Line Card Tables,SRAM counters, meters DRAM Buffers Tables,SRAM counters, meters DRAM Buffers DRAM TCAM SRAM DRAM Buffers DRAM TCAM SRAM DRAM Buffers DRAM TCAM DRAM Buffers (HX330) DRAM TCAM DRAM TCAM HX320 HX320 HX330 HX320 HX330 HX320 HX330 HX320 HX330 HX330 Fabric Card A Fabric I/F Fabric VOQ Fabric I/F Fabric VOQ Fabric I/F Fabric VOQ Fabric I/F Fabric VOQ Fabric Card B XAUI+, HiGig 48x SGMII 48x Base-X Serdes 5xXAUI 40G Interlaken XFP/SFP+ RJ45 RJ45 RJ45 Octal Octal Octal PHY PHY PHY Octal Octal Octal PHY PHY PHY Copper Ethernet • 48x GE • 48x FE • 16x 2.5GE 59 SFP optics SFP optics SFP optics XFP/SFP+ XAUIXFI XFP/SFP+ XFP/SFP+ 40G opto XAUIXFI 40G MAC or Framer XFP/SFP+ Optical Ethernet: • 48x GE • 48x FE • 16x 2.5GE © 2010 Renesas Electronics America Inc. All rights reserved. 10GE optical: • 5x 10GE 40GE or OC768