Download A/D Converted Value Addition Mode - Renesas e

RX 12 Bit Analog-to-Digital Converter
Renesas Electronics Corporation
11/1/10
Rev. 1.0
© 2010 Renesas Electronics America Inc. All rights reserved.
00000-A
Agenda
This course contains a description of specific features of the RX 12 Bit
ADC which is identified as S12AD in the HW manual.
For basic ADC technology and terms refer to ADC Technology and ADC
Operating Mode courses.
For overview of ADC features for a specific group refer to RX Technical
Marketing Overview course. This course the describes number of
channels, conversion times and other specific items
Contained in this course:
 Block Diagram
 Operating Modes
 Channel Select Register
 Converted Value Addition Mode
 Internal Reference Voltage (Not in RX62N )
 Temperature Sensor (Not in RX62N )
 Usage Notes
2
© 2010 Renesas Electronics America Inc. All rights reserved.
Block Diagram
3
© 2010 Renesas Electronics America Inc. All rights reserved.
Operating Modes
 Single-Cycle Scan Mode
 Performs single scan over range of enabled channels
 Example: Start -> AN00 -> AN01 -> Done
 Continuous Scan Mode
 Continually performs conversion of selected analog input(s)
 Example: Start -> AN00 -> AN01 -> AN00 -> AN01 …
4
© 2010 Renesas Electronics America Inc. All rights reserved.
ADC Channel Select Registers
 Register controls which inputs are converted




Allows enabling or disabling individual channels
“1” in bit position enables conversion
ADANS1 register >16 channels
Scan occurs in ascending order
ADANS0 Register
New Development
5
© 2010 Renesas Electronics America Inc. All rights reserved.
ADC Data Registers
 16 bit registers one for each channel
 Can be left or right aligned in 12 bit mode
 14 bits left aligned when using A/D converted value addition
 Padded bits are always read as zero – no need to mask
Right Aligned
12 bit result
Left Aligned
12 bit result
b15 b14 b13 b12 b11 b10 b9
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
0
0
0
0
b3
b2
b1
b0
0
0
AD[11:0]
b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
AD[11:0]
b15 b14 b13 b12 b11 b10 b9
Left Aligned
b8
AD[13:0]
b8
b7
b6
b5
b4
14 bit result
New Development
6
© 2010 Renesas Electronics America Inc. All rights reserved.
Automatic Clearing Enable Bit (ACE)
 Located in AD Control Extended Register
 When enabled allow automatic clearing of data register after
they are read
 Allows detection of update failure
New Development
7
© 2010 Renesas Electronics America Inc. All rights reserved.
ADC Conversion
New Development
8
© 2010 Renesas Electronics America Inc. All rights reserved.
ADC Conversion Time Summary
 Conversion time based on A/D Clock = PCLK
 tSCAN = tD + (tCONV * N) + tED
 N is number of channels to convert
New Development
9
© 2010 Renesas Electronics America Inc. All rights reserved.
A/D Converted Value Addition Mode
 Performs 2-4 samples on channel and sums results
 Converted Value Addition Mode Select Register (ADADS0 ,
ADADS1) selects channels to be summed
 Converted Value Addition Count Select Register (ADADC)
selects number of times to sample (1,2,3 or 4)
Example
 Conversion sequence for:
# of
Conversions
4
AN00
AN02
AN00
AN00
AN02
AN00
AN00
AN02
AN00
3
2
1
AN00
AN01
AN02
AN03
AN00




Ch. Select 0,1,2 and 3
Continuous Scan
Ch 0 and 2 set for Value Addition Mode
Value Addition Count Select set for 4
 Ch 1 and 3 can be left or right
aligned, 12 bit result
 Ch 0 and 2 is left aligned
regardless of setting, 14 bit result
New Development
10
© 2010 Renesas Electronics America Inc. All rights reserved.
Temperature and Internal Reference
 Internal connection allows reading
 Internal Reference Voltage
 Internal Temperature Sensor
 Separate Results registers for temp and voltage
 Can be right aligned, left aligned
 Can also use value addition mode, always left aligned
 Temp Sensor and Reference Voltage should not be converted
while converting Analog Inputs
 All ANSi bits should be set to 0
11
© 2010 Renesas Electronics America Inc. All rights reserved.
ADC Usage Notes
 AD conversion complete interrupt (ADI)
 Can be used as interrupt
 Can be used to trigger DTC or DMACA
 Disable ADC (ADST = 0, SW Trigger) before entering power
down states
New Development
12
© 2010 Renesas Electronics America Inc. All rights reserved.
Summary

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13
Block Diagram
Operating Modes – Single Scan, Continuous Scan
Channel Select Register
Converted Value Addition Mode
Internal Reference Voltage (Not in RX62N)
Temperature Sensor (Not in RX62N)
Interrupt and Low Power Usage Notes
© 2010 Renesas Electronics America Inc. All rights reserved.
Thank You
Renesas Electronics America Inc.
© 2010 Renesas Electronics America Inc. All rights reserved.