Download Packet Switching, ATM, switch Fabric

Introduction
to
Computer Networks
Lecture 9: Packet Switching
University of Tehran
Dept. of EE and Computer Engineering
By:
Dr. Nasser Yazdani
Univ. of Tehran
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outline




Store-and-Forward Switches
Bridges and Extended LANs
Packet switching
Cell Switching

Segmentation and Reassembly
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Scalable Networks

Limitation of directly connected networks.



Limit on the number of hosts; For example,
Ethernet is 1024 hosts.
Limit on the geographical area of LANs. 2500
m in Ethernet.
Solution: This is like telephone network.
Then, use Switches.
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Switches

forwards packets from input port to output port
T3
T3
STS-1
Input
ports


port selected based on address in packet header
If two packets are destined to the same output,
one must be buffered (queued). This is called
contention.


Switch
T3
T3
STS-1
Output
ports
Needs some kinds of scheduling for packet delivery.
If the buffer overflow, it will be a congestion.
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An Ethernet Network
Router
Problem:
Outside
world
Shared
network limits throughput.
Lots of collisions reduces efficiency.
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Interconnecting LANs



Bridges (aka Ethernet switches) were
introduced to allow the interconnection of
several local area networks (LANs) without a
router.
By partitioning a large LAN into multiple smaller
networks, there are fewer collisions, and more
parallel communications.
It is now common for the port of an Ethernet
switch to connect to just one (or a small
number of) hosts.
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Ethernet Switching
Ethernet
Switch
Ethernet
Switch/Bridge
Benefits:
Number of collisions is reduced.
 Capacity is increased:

Router Outside
world
Problem? How to determine the output port?
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One Ethernet Switch in
“Packard”
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Output ports? Learning Bridges


Maintain a forwarding table for hosts.
Port
Host
1
A
1
B
1
C
2
X
2
Y
2
X
A
B
C
Port 1
Bridge
Port 2
X
Y
Z
How to populate table.


Manually by system admin. (not good)
Learn table entries based on source address (flexible).
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Learning Bridges, (Forwarding)
1.
2.
3.



If the frame destination address is in the
routing table, forward the frame to the
corresponding port.
Otherwise, broadcast the frame.
Update the table if the source address is not in
the table.
The table is learned by examining the
Ethernet SA of arriving packets.
Table is an optimization; need not be
complete
Always forward broadcast frames
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Ethernet Switching
Learning addresses
B
A
C
2 3
1
Ethernet
Switch
6
I
J
Ethernet
Switch
Univ. of Tehran
4
5
K
D
J F
E
F
G
Ethernet
Switch
Switch learns that ‘F’ is
reachable through port 5
N
L
M
O
H
Outside
Q Router
world
P
Ethernet
Switch
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Ethernet Switching
Ethernet address
Port
A
1
Learning addresses
B
A
C
2 3
1
Ethernet
Switch
6
I
J
B
2
C
3
D
4
E, F, G, H, Q
5
I, J, K, L, M, N, O, P
6
D
E
F
4
5
K
G
Ethernet
Switch
L
M
N
H
Outside
Q Router world
O
P
Ethernet
Switch
Ethernet
Switch
Q: How do we prevent loops?
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Preventing loops
Spanning Tree Protocol


The network of bridges is a graph.
The Spanning Tree Protocol finds a
subgraph that spans all the vertices without
loops.



Spanning => all bridges are included.
Tree => the topology has no loops.
The distributed protocol runs:


To determine which bridge is the root of the
tree, and
Each bridge turns off ports that are not part of
the tree.
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Spanning Tree Algorithm

A
Spanning tree
B
B3
C
B5
D
B2
B7
E
K
F
B1
G
H
B6
B4
I

A distributed spanning tree algorithm
select which bridges actively forward
 developed by Radia Perlman
 Univ.
now
IEEE 802.1 specification
of Tehran
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
14
Example Spanning Tree
B8
B3
Protocol operation:
B5
B7
B2
3.
B1
B6
Univ. of Tehran
1.
2.
B4
Introduction to Computer Network
Picks a root
For each LAN,
picks a designated
bridge that is closest
to the root.
All bridges on a LAN
send packets towards
the root via the
designated bridge.
15
Example Spanning Tree
B8
Spanning Tree:
B3
B5
B1
B7
B2
B2
B4
B5
B7
B1
Root
B6
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B8
B4
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Algorithm Details

Bridges exchange configuration messages





id for bridge sending the message
id for what the sending bridge believes to be root
bridge
distance (hops) from sending bridge to root bridge
Each bridge records current best
configuration message for each port
Initially, each bridge believes it is the root
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Algorithm Detail (cont)

When learn not root, stop generating config
messages



in steady state, only root generates configuration
messages
Root continues to periodically send config
messages
If any bridge does not receive config message
after a period of time, it starts generating
config messages claiming to be the root
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Spanning Tree Protocol
1. Each bridge periodically sends a configuration message out of every
port. A message contains: (ID of sender, ID of root, distance from
sender to root).
2. Initially, every bridge claims to be root and sends a distance field of 0.
3. A bridge keeps sending the same message (periodically) until it hears a
“better” message. “Better” means:
•
•
•
A root with a smaller ID
A root with equal ID, but with shorter distance
The root ID and distance are the same as we already have, but the
sending bridge has a smaller ID.
4. Once a bridge hears a better configuration message, it stops
generating its own messages, and just forwards ones that it receives
(adding 1 to the distance).
5. If the bridge realizes that it is not the designated bridge for a LAN, it
stops sending configuration messages to that LAN.
Eventually:
•
•
Only the root bridge generates configuration messages,
Other bridges send configuration messages to LANs for which they are the
designated bridge.
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Broadcast and Multicast

Forward all broadcast/multicast frames



current practice
Learn when no group members
downstream
Accomplished by having each member of
group G send a frame to bridge multicast
address with G in source field
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Limitations of Bridges

Do not scale


spanning tree algorithm does not scale
broadcast does not scale

Do not accommodate heterogeneity

Caution: beware of transparency
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Packet Switching Schemes


Learning bridges are a special case. We
need a general form for packet switching or
specifying the output in the packet.
They are three format for specifying the
output in the a packet



Source routing: List entire path in the packet
Virtual circuits: like telephone circuit, identify
packets with ids.
Datagram: Put only destination address in
packets’ headers.
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Source Routing

List entire path in packet


Router processing, one option




Driving directions (north 3 hops, east, etc..)
Examine first step in directions
Strip first step from packet
Forward to step just stripped off
Or the address can be implemented by a
linked list in the packet header.
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Source Routing Example
Packet
4,3
3,4,3
2
Sender
1
2
R1
4
3
1
R1
3
4
3
2
1
R2
4
3
Receiver
All routing information is provided by the source.
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Source Routing

Advantages


Disadvantages



Switches can be very simple and fast
Variable (unbounded) header size
Sources must know or discover topology (e.g.,
failures)
Typical use

Debugging and management
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Virtual Circuits/Tag Switching



Use the telephone model virtual circuits
Each flow is identified by a Virtual Circuits Identifier (VCI).
Connection setup phase, Signaling




Each packet carries connection ID


Use other means to route setup request
Each router allocates flow ID on local link
Creates mapping of inbound flow ID/port to outbound flow ID/port
Sent from source with 1st hop connection ID
Router processing




Lookup flow ID – simple table lookup
Replace flow ID with outgoing flow ID
Forward to output port
Swap labels
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Virtual Circuit
Connection setup establishes a path through switches



A virtual circuit ID (VCI) identifies path
Uses packet switching, with packets containing VCI
VCIs are often indices into per-switch connection tables;
change at each hop
VC1
VC2
1
2
VC1
In, VC Out, VC
1, 1
4, 1
1, 2
4, 3
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of 1
Tehran 4, 2
4
VC1
VC2
3
4
1
VC3
2
VC1
3
VC2
VC1
….
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Virtual Circuits Examples
In-port
Lookup table for
Switch R1
Packet
Sender
In-VCI
Out-port
Out-VCI
1
5
3
7
4
11
0
8
5
7
1
2
2
R1
R2
4
3
1
4
1,7  4,2
3
2
1,5  3,7
2
1
R3
4
3
Receiver
6
2,2  3,6

Subsequence packets follow the same circuit
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Virtual Circuits

Advantages






Disadvantages



More efficient lookup (simple table lookup)
More flexible (different path for each flow)
Can reserve bandwidth at connection setup
Easier for hardware implementations
Small per-packet header overhead.
Still need to route connection setup request
More complex failure recovery – must recreate
connection state
Typical uses


ATM – combined with fix sized cells
MPLS – tag switching for IP networks
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Virtual Circuit Model




Typically wait full RTT for connection setup
before sending first data packet.
While the connection request contains the full
address for destination, each data packet
contains only a small identifier, making the
per-packet header overhead small.
If a switch or a link in a connection fails, the
connection is broken and a new one needs to
be established.
Connection setup provides an opportunity to
reserve
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Datagram Switching





No connection setup phase since it is costly.
Each packet is forwarded independently
Sometimes called connectionless model
Analogy:
postal
system Packet
Each switch
maintains a
forwarding
(routing)
table
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Sender
R
R
1
2
R1
4
3
1
2
R1
4
R4
3
R3
R
2
1 R2
3
4
Receiver
R
R3
Introduction to Computer Network
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Datagram Model




There is no round trip time delay waiting for
connection setup; a host can send data as soon as it
is ready.
Source host has no way of knowing if the network is
capable of delivering a packet or if the destination
host is even up.
Since packets are treated independently, it is
possible to route around link and node failures.
Since every packet must carry the full address of the
destination, the overhead per packet is higher.
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Techniques: Comparison
Datagram
Forwarding
cost
Bandwidth
utilization
Resource
reservations
Robustness*
Circuit
switching
high
Virtual
circuit
switching
low
high
flexible
low
none
flexible
yes
high
low
low
none
*The idea is that in case of failure, circuit and VC are lost;
datagram routing can adapt after routing update ….
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Cell Switching (ATM)





Connection-oriented packet-switched network
Used in both WAN and LAN settings
Signaling (connection setup) Protocol: Q.2931
Specified by ATM forum
Packets are called cells


5-byte header + 48-byte payload
Commonly transmitted over SONET

other physical layers possible
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Variable vs Fixed-Length
Packets

No Optimal Length



if small: high header-to-data overhead
if large: low utilization for small messages
Fixed-Length Easier to Switch in
Hardware


simpler
enables parallelism
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Big vs Small Packets

Small Improves Queue behavior

finer-grained pre-emption point for scheduling link






maximum packet = 4KB
link speed = 100Mbps
transmission time = 4096 x 8/100 = 327.68us
high priority packet may sit in the queue 327.68us
in contrast, 53 x 8/100 = 4.24us for ATM
near cut-through behavior





two 4KB packets arrive at same time
link idle for 327.68us while both arrive
at end of 327.68us, still have 8KB to transmit
in contrast, can transmit first cell after 4.24us
at end of 327.68us, just over 4KB left in queue
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Big vs Small (cont)

Small Improves Latency (for voice)





voice digitally encoded at 64Kbps (8-bit samples at
8KHz)
need full cell’s worth of samples before sending cell
example: 1000-byte cells implies 125ms per cell (too
long)
smaller latency implies no need for echo cancellors
ATM Compromise: 48 bytes = (32+64)/2
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Cell Format

User-Network Interface (UNI)
4
8
16
3
1
8
384 (48 bytes)
GFC
VPI
VCI
Type
CLP
HEC (CRC-8)
Payload








host-to-switch format
GFC: Generic Flow Control (still being defined)
VCI: Virtual Circuit Identifier
VPI: Virtual Path Identifier
Type: management, congestion control, AAL5
(later)
CLP: Cell Loss Priority
HEC: Header Error Check (CRC-8)
Network-Network Interface (NNI)
switch-to-switch format
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to Computer
 ofGFC
of VPI
fieldNetwork

39
Segmentation and Reassembly

ATM Adaptation Layer (AAL)



AAL 1 and 2 designed for applications that need
guaranteed rate (e.g., voice, video)
AAL 3/4 designed for packet data
AAL 5 is an alternative standard for packet data
AAL
AAL
…
…
ATM
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ATM
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AAL 3/4

Convergence Sublayer Protocol Data Unit (CSPDU)




8
8
16
< 64 KB
CPI
Btag
BASize
User data
0– 24
8
8
16
Pad
0
Etag
Len
CPI: common part indicator (version field)
Btag/Etag:beginning and ending tag
BAsize: hint on amount of buffer space to allocate
Length: size of whole PDU
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Cell Format
40
ATM header






4
10
Type
SEQ
MID
352 (44 bytes)
Payload
6
10
Length
CRC-10
Type


2
BOM: beginning of message
COM: continuation of message
EOM end of message
SEQ: sequence of number
MID: message id
Length: number of bytes of PDU in this cell
It uses 4 extra bytes for SAR, not good!
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AAL5

CS-PDU Format




< 64 KB
0– 47 bytes
16
16
32
Data
Pad
Reserved
Len
CRC-32
pad so trailer always falls at end of ATM cell
Length: size of PDU (data only)
CRC-32 (detects missing or misordered cells)
Cell Format

end-of-PDU bit in Type field of ATM header
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ATM Layers
Aplication
PHY in ATM is usually
SONET.
TCP
Higher
Layers
IP
AAL
DLL
ATM
PHY
PHY
TCP/IP
ATM
• Sending IP over ATM is done by address translation.
• ATM is also used in LAN. Then, It tries to emulate LAN.
• The Technology is called LANE.
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Switches



A means to create connectivity
Why switching? Efficient utilization of resources
Store and forward scheme
incoming links
Node
outgoing links
Memory
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Switched Network


A network consisting of switching elements.
Hosts can connect to the network directly or
through LANs.
n links
Switches
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Switched
Network
46
Basic concepts

An ideal switch: route all incoming packet to their
requested outputs with the following conditions:





No loss
Minimum delay
Preserving order
Output contention: At least two input goes to one
output. we need buffer and queuing (how much?)
Congestion: no buffer space left. Drop packet
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Design Factors

Throughput





Max throughput- N x line speed where N is the # of
input line
Ave throughput – At random is %60.
Packet per second (PPS)- # of packets switched per
second
Throughput depends on the traffic.
Quality of service:



Ave delay of cells
Jitter
Reliability in switching cells.
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Design Factors

Scalability: how the architecture scale,
linear? Square?



Regarding the speed of input line
Regarding the # of input port.
Cost:



# of logic gates
Memory
Bandwidth or # of pines
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Performance Factors

Traffic pattern:



Addressing and operation:


Packet arrival rate.
Destination distribution
Unicast or multicast operation
Priority- Differentiation among packets
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Functional requirement

User plane:


Data is carried transparently
Header are processed and VPI/VCI is used for
routing.
LC
IPP
0
0
LC
…
…
SFC
OPP
Central unit
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Functional requirement
IPP+ SFC+ OPP

Store and forward system.
Cntrl plane: Signaling


Identified by VPI/VCI, 5/0 is for call admission.
May use SFC for transporting ctrl packets.
CAC
LC
IPP
OPP
…
…
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SFC
LC
CAC- Call
Admission Control
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Functional requirement

Management plane: System Management
(SM) must handle management cell.


Should support Network wide operations.
May use SFC for transporting management cells.
SM
LC
IPP
OPP
…
…
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SFC
LC
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Workstation-Based switch

Aggregate bandwidth




1/2 of the I/O bus bandwidth
capacity shared among all hosts connected to switch
example: 800Mbps bus can support 8 T3 ports
Packets-per-second



must be able to
switch small packets
100,000 packets-persecond is achievable
e.g., 64-byte packets
implies 51.2Mbps
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I/O bus
CPU
Interface 1
Interface 2
Interface 3
Main memory
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Architectures: First Generation
Shared Backplane
CPU
Route
Table
Buffer
Memory
Line
Interface
Line
Interface
Line
Interface
MAC
MAC
MAC
Typically < 0.5Gbps aggregate capacity
Limited by rate of shared memory
Slide by Nick McKeown
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Architectures: Second Generation
CPU
Typically
< 5Gb/s aggregate capacity
Limited by shared bus
Buffer
Memory
Route
Table
Line
Card
Line
Card
Line
Card
Buffer
Memory
Buffer
Memory
Buffer
Memory
Fwding
Cache
Fwding
Cache
Fwding
Cache
MAC
MAC
MAC
Slide by Nick McKeown
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Architectures: Third Generation
Switched Backplane
Line
Card
Local
Buffer
Memory
CPU
Card
Line
Card
Routing
Table
Local
Buffer
Memory
Fwding
Table
Fwding
Table
MAC
MAC
Typically
< 50Gbps aggregate capacity
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Slide by Nick McKeown
57
Switch fabric design

Shared Media



Space division



Bus Architecture
Shared buffer
Cross bar architecture
Combination of above
Note: Self-routing is to direct packet inside
the fabric.
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Bus Architecture



IPP puts cells on bus
OPP buffer cells
Control Processor (CP)



exchanges control messages
configures connections
Bus interconnects various
components.
» In nonblocking systems
bandwidth is equal to sum of
external link bandwidths;
» bus width must increase with
number of links
» capacitive loading reduces clock
rate as number of links grows
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Divided Bus with Knockout
Concentrators w/n


Split bus into n “minibuses”
with w/n wires each
Each minibus driven by just
one IPP.






cuts capacitive loading in half
adding fanout components
allows higher clock frequencies
IPP
IPP
IPP
IPP
w
OPPs
OPPs concentrate n minibuses
onto L<n outputs (optional)
OPPs must each be able to
buffer up to L cells in parallel
Parallel reception complicates control somewhat
Concentration reduces required OPP memory bandwidth
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Knockout Switch
Inputs
D
D
D
D

Concentrator
select l of
n packets


Complexity: n2
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D
D
D
D
D
D
D
1
D
2
D
D
Outputs
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4
61
Shared Buffer Switches
n
n

IPP
OPP
. . .
n
Queues are rarely full, then, memory
for queues is unused mostly
With shared memory, we can achieve
same performance level with less
memory.
Requires a central memory with
bandwidth equal to twice the external
link bandwidth.
Per output or per flow queues typically
implemented as linked lists.
. . .
n
CP
...
For switches with 10 or more links, can reduce required
memory by up to an order of magnitude.
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crossbar Architecture

crossbar allows multiple cells
to pass in parallel to distinct
outputs
IPP
OPP
» use of point-to-point
transmission eliminates
capacitive loading at circuit
board level
» parallelism reduces data path
width at IPPs, OPPs


control circuit arbitrates
access to outputs
retains quadratic complexity,
but concentrates it within
chip, reducing system cost
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Introduction to Computer Network
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UT switch Design
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UT Internal Design
Data Path
Shared Memory (SM)
Input
Processor
Output
Processor
Memory Management
(Pointer Path)
User
Interface
Control Path
Central Unit
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UT Capacity mode
40 Gb/s
Shared Memory
IPP0
OPP0
Dual chip mode
40 Gb/s
Shared Memory
IPP15
CM
# of chips
# of cells
stored
0
1
5500
1
2
11000
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OPP15
66
Examples: Cisco GSR - 12416




WAN Router – Large throughput; SONET links
Up to 16 line cards at 10 Gbps each
Crossbar Fabric
Cisco GSR 12416
19”
Line Cards:
1-port OC-192c
4-port OC48c
Many others
(ATM, Ethernet, …)
6ft
2ft
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