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Transcript
ESD Device testing: The test determines the result The ESD test you choose—HBM, MM, or CDM—has a profound effect on the amount of current that will pass through a device. Robert Ashton, Sr. Protection and Compliance Specialist, ON Semiconductor Whenever an electrically charged object discharges, it produces an ESD (electrostatic discharge) event. An ESD event can subject an electronic device to thousands of volts and several amperes. High voltage can cause breakdown in a device structure and the current can cause heat that damages the device. The current discharged into a device depends on the ESD voltage and on the characteristics of the device’s current path. But, the amount of current that passes through a device can be drastically different for a given discharge voltage. For example, a 1000-V discharge can produce a wide range of current, from the fantastic to the dismal. Unfortunately the differences in current for a given voltage are not always well understood. ESD tests for electrical components such as integrated circuits include Human Body Model (HBM)1,2, Machine Model (MM)3,4, and Charged Device Model (CDM)5,6. ESD tests for electrical systems such as cell phones, computers and televisions include IEC 61000-4-27 and the automotive standard ISO 106058. Each of these tests attempts to simulate real world ESD events in a reproducible manor. The nature of these ESD tests and real world ESD events depend on two properties, a capacitor that becomes charged and a discharge path. Often the discharge path, rather than the size of the capacitor or its charge voltage, that dominates the severity of an ESD event. Device Level Test Methods The ESD test methods for integrated circuits, HBM, MM, and CDM, are intended to insure that the circuits can be safely handled in an ESD controlled environment during manufacture. HBM is the oldest ESD test method and is intended to simulate a charged person touching an integrated circuit. A person has approximately 100 pF of capacitance and skin and body resistance limit the current during a discharge. A basic circuit diagram for HBM is shown in Figure 1. A 100-pF capacitor is charged to a voltage and then discharged through a 1500- resistor and the device under test (DUT). A current waveform for a 2000 V HBM event is shown in Figure 2. The current rises rapidly to about 1.4 A within 10 ns and then decays with a 150 ns time constant. For many years 2000 V HBM has been the generally accepted value for passing ESD qualification, although there has been recent movement to lower that to 1000V.9 In all ESD test specifications it is a current waveform that is actually specified with a representative circuit diagram shown or implied by the waveform. HBM 1500W MM 0.8mH HBM 100pF MM 200pF C DUT Current (A) Figure 1 Basic circuit diagram for HBM and MM is a capacitor digcharging through a resistor. 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -200 0 200 Time (ns) 400 600 Figure 2. 2000 V HBM Current waveform into a short. MM is intended to simulate a charged machine with low resistance discharging through an integrated circuit. Only inductance and a small amount of resistance limit the current. The circuit diagram is very similar to HBM. The capacitor value is 200 pF and the resistor is replaced by an inductor as shown in Figure 1. The oscillatory current waveform characteristic of MM for a 200 V MM pulse is shown in Figure 3. 200V has been the most commonly specified values for MM qualification for many years although there is sentiment to eliminate MM testing or lower its qualification level.9 4 Current (A) 3 2 1 0 -1 -2 -3 -200 0 200 400 Time (ns) 600 Figure 3. A 200V MM waveform into a short 800 1000 CDM emulates an integrated circuit which becomes charged and discharges when it touches a grounded metal surface. CDM has a very different nature than HBM and MM. There is no fixed value of a capacitor to discharge; the capacitance to be charged is the capacitance of the integrated circuit to its surroundings. The discharge path, consisting only of the circuit’s pin and the arc formed between pin and the metal surface, has very little impedance to limit current. Field Induced CDM, the most popular implementation of CDM, is illustrated in Figure 4. The integrated circuit is placed pins up, “Dead Bug Position”, on top of a field plate, with only a thin insulator between the circuit and the field plate. The thin space between the circuit and the field plate creates a capacitance whose value depends on the size of the integrated circuit and the package geometry. A ground plane with a “Pogo Pin” is positioned over the field plate. A 1- circular resistor and coax cable allow current through the pogo pin to be measured. If the capacitance between the integrated circuit and the field plate is much larger than the capacitance between the circuit and the ground plane, the potential of the integrated circuit will track the potential of the field plate. To perform the CDM test an uncharged circuit is placed on the field plate. The field plate is charged to a high voltage and the circuit’s potential tracks the field plate. The ground plane is then moved so that the pogo pin touches the integrated circuit, grounding it. The result is a very fast redistribution of charge between the field plate to ground plate capacitance and the integrated circuit to field plate capacitances. A sample 500 V CDM discharge for the small JEDEC test module is shown in Figure 5. 50 Coax Ground Plate 1 Circular Resistor Pogo Pin Insulator Field Plate Figure 4. Diagram of a Field Induced CDM ESD Tester. HV Supply >100M 6 5 Current (A) 4 3 2 1 0 -1 -2 -1 0 1 2 Tim e (ns) 3 4 5 Figure 5. Field-induced CDM waveform of a small JEDEC Module at 500 V. Figure 6 and Figure 7 overlay current waveforms for HBM at 2000 V, MM at 200 V and CDM for 500 V. These voltage levels are the most commonly required levels for qualification for each of these tests. Review of these figures demonstrates how voltage means very different things when applied to different ESD test methods. 2000 V HBM results in substantially smaller stress current than 200 V MM. It is true that the MM capacitance is twice the HBM capacitance but a factor of 10 lower voltage still results in higher current which lasts longer. CDM produces a much shorter current pulse than either HBM or MM but it produces a substantially larger peak current. HBM and MM can deliver more energy to the device under test, but high peak currents are often the best predictor of damage. Current (A) HBM 2000V 6 5 4 3 2 1 0 -1 -2 -3 -200 0 200 MM 200V 400 CDM 500V 600 800 1000 Time (ns) Figure 6 Comparison of HBM, MM and CDM waveforms at 2000V, 200V and 500V respectively at long times Current (A) HBM 2000V MM 200V CDM 500V 6 5 4 3 2 1 0 -1 -2 -3 -2 0 2 4 6 8 10 12 Time (ns) Figure 7. Comparison of HBM, MM and CDM waveforms at 2000 V, 200 V and 500 V respectively at short times. In the above discussion the CDM waveform was for the JEDEC standard. There are two other CDM standards in use, the ESDA standard and the JEITA10 standard from Japan. The JEDEC and ESDA specifications both use the field induced method while the JEITA standard uses a direct charging method. All produce somewhat different stresses for the same voltage. The differences in stress can be illustrated by the differences in peak current at 500V for each standard’s small calibration module as shown in Table 1. The ESDA and JEITA specifications both use a 4 pF calibration module yet produce over a factor of two difference in nominal peak current. The JEDEC module has a larger capacitance than the ESDA module yet has a smaller current. This does not imply that any of the standards is better than the other, only that 500 V means different things for the different standards. Table 1. Specified peak currents for the small calibration modules at 500V Standard JEDEC ESDA JEITA Module Capacitance 6.8pF 4pF 4pF Peak Current 5.75A ± 15% 7.5A ± 20% 2A ± 1A System Level Test Methods The variability in the stress between standards becomes greater when system level testing is considered. Figure 8 shows the schematic diagram often used to describe ESD guns in the IEC 61000-4-2 and ISO 10605 system level ESD standards. The two standards use different values for the C1 and R1 components. IEC 61000-4-2 uses a 330- resistor and a 150-pF capacitor. ISO 10605 uses a 2000- resistor but different capacitances depending on application. A 150-pF capacitor is used to simulate reaching into an automobile or for unpowered bench testing of electronic modules. A 330-pF capacitor is used to simulate ESD events while sitting in a vehicle. With the widely different values of the resistors and capacitors one would expect the current waveforms for the three different resistor capacitor combinations to be quite different. Figure 9 shows measurements from the same ESD gun fitted with each of the three resistor-capacitor combinations. The results show essentially the same initial peak current between the three resistor capacitor combinations, and only after about 10 ns do the 2000- resistor waveforms begin to diverge from the 330- resistor waveform. High Value Resistor HV Supply R1 Discharge Tip C C1 Ground Return IEC 61000-4-2: R1= 330W, C1=150pF ISO 10605: R1=2000W, C1=150pF or 330pF Figure 8. IEC 61000-4-2 and ISO 10605 schematic as shown in specification. IEC ISO 150pF ISO 330pF 18 16 Current (A) 14 12 10 8 6 4 2 0 -20 0 20 40 60 80 100 Time (ns) Figure 9. Comparison of ISO 61000-4-2 waveform with ISO 10605 waveforms with both 150pF and 330 pF capacitances at 4000 V Further consideration reveals that the schematic diagram in Figure 8 can not yield the waveform required by the standards. Figure 10 and Table 2 are the waveform requirements for the two standards. Both standards specify the same peak current value, although the ISO standard specifies a +30% and -0% tolerance while the IEC standard specifies ±10% tolerance. Since the initial peak is essentially unchanged between the two standards the initial peak must be due to features not included in the schematic of Figure 10. A conceptual schematic is shown in Figure 11 to explain the initial current spike. The source of the initial current pulse is the capacitor C2. The capacitor C2 is actually a fringing capacitance between the ESD gun and the ground plane required in the waveform measurement setup7. While the capacitor C2 is not discussed in either standard, it is required to be present to produce the specified waveform. A more detailed schematic has been developed by Caniggia and Maradei.11 Ip 0.9 Ip 0.1 Ip 0 30ns tr 60ns Time Figure 10. Schematic diagram of the IEC 61000-4-2 and ISO 10605 waveforms and the parameters used to characterize the waveform. Table 2. Waveform parameters for IEC 61000-4-2 and ISO 10605. Parameter Rise Time Peak Current Current at 30ns Current at 60ns High Value Resistor HV Supply IEC Value 0.7 to 1.0 ns 3.75 A/kV ±10 % 2 A/kV ± 30 % 1 A/kV ± 30% R1 C1 ISO Value 0.7 to 1.0 ns 3.75 A/kV +30% -0% Not Specified Not Specified Discharge Tip C2 Ground Return Figure 11. More realistic IEC 61000-4-2 and ISO 10605 schematic. The different capacitances and resistances in IEC 61000-4-2 and ISO 10605 only become important after the initial current spike caused by C2. The lower resistance in the IEC specification predicts a higher current level than the ISO specification. This is clearly seen in Figure 9. The R1 and C1 values predict 3 different decay times; 49.5 ns for the IEC standard and 300 ns and 660 ns for the 150 pF and 330 pF C1 capacitances in the ISO standard. This trend is clearly shown in Figure 12 where the comparison between the different waveforms is extended to longer times. Current (A) 150pF 2000 Ohms 35 30 25 20 15 10 5 0 -200 0 330pF 2000 Ohms 200 400 600 150pF 2000 Ohms 800 1000 Time (ns) Figure 12. Comparison of ISO 61000-4-2 waveform with ISO 10605 waveforms with both 150 pF and 330pF capacitances at 8000 V. Failure levels for the three resistor/capacitor combinations could be very similar or very different, depending on the failure mode. If failure is caused by peak current, all three stresses will produce very similar results. For thermal failure, in which a balance between resistive heating and thermal diffusion is important, the results could be very different. Relation of Device and System Level Testing The relative severity of system level and device level stress can be seen in Figure 13 and Figure 14 where 2000V IEC 61000-4-2, 2000V HBM and 500-V CDM (JEDEC) waveforms are plotted together. Even though the IEC and HBM waveforms are taken at the same charging voltage the level of stress is considerably more for the IEC waveform. The contrast between HBM and IEC becomes more impressive when it is realized that 2000 V is considered a good number for HBM while 8000V is often required for IEC 61000-4-2 testing. The CDM waveform, although taken at 500 V, produces a peak current approximately 70% of the peak current of the 2000V IEC waveform. Figure 13 and Figure 14 reveal that the IEC waveform combines the fast rising current spike of CDM with the more sustained current of HBM. IEC 2000V HBM 2000V CDM 500 10 Current (A) 8 6 4 2 0 -2 -50 0 50 100 150 200 250 300 Time (ns) Figure 13. Comparison of IEC, HBM and CDM waveforms. Current (A) IEC 2000V HBM 2000V CDM 500 9 8 7 6 5 4 3 2 1 0 -1 -2 -5 0 5 10 15 20 Time (ns) Figure 14. Comparison of IEC, HBM and CDM at an expanded time scale. Conclusion When evaluating ESD test results it is very important to know to what standard the product is tested to. A quote of an ESD level without a reference to a specific standard needs to be questioned. Confusion can be especially bad because the IEC 61000-4-2 system level standard is occasionally referred to as Human Body Model and has much more severe stress than the Human Body Model specified for devices by JEDEC and ESDA. For CDM it is very important to know which standard is being used, JEDEC, ESDA or JEITA since the stress levels differ for the same voltage. “Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)”, JESD22-A114D, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, March 2006. 1 “Standard Test Method For Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) Component Level”, ANSI/ESD STM5.1-2001, Electrostatic Discharge Association, March 2003. 3 “Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)”, JESD22-A115A, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, October, 1997. 4 “Standard Test Method for the Electrostatic Discharge Sensitivity Testing Machine Model – Component Level”, ESD STM5.2-1999, Electrostatic Discharge Association, May 2001. 5 “Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components”, JESD22-C101C, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, December 2004. 6 “Standard Test Method for Electrostatic Discharge Sensitivity Testing – Charged Device Model (CDM) Component Level, Electrostatic Discharge Association, May 2001. 7 “Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test”, IEC 61000-4-2, INTERNATIONAL ELECTROTECHNICAL COMMISSION, April 2001. 8 “Road vehicles - Test methods for electrical disturbances from electrostatic discharge”, ISO 10605, December 2001. 9 “White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements “ Industry Council on ESD Target Levels, August 2007. 10 “Environmental and endurance test methods for semiconductor devices”, Japan Electronics and Information Technology Industries Association, August 2001. 11 S. Caniggia and F. Maradei, “Circuit and Numerical Modeling of Electrostatic Discharge Generators”, IEEE Trans. On Industry Applications, Vol 42, No. 6, 2006. 2