Download Evolution and History of Programming Languages Software

Evolution and History of
Programming Languages
Software/Hardware/System
Software Programming
Language
History Timeline
The Evolution of Programming Languages
To build programs, people use languages that are similar
to human language. The results are translated into
machine code, which computers understand.
Programming languages fall into three broad categories:
•
Machine languages
•
Assembly languages
•
Higher-level languages
The Evolution of Programming Languages Machine Languages
• Machine languages (first-generation languages) are the
most basic type of computer languages, consisting of
strings of numbers the computer's hardware can use.
• Different types of hardware use different machine
code. For example, IBM computers use different
machine language than Apple computers.
The Evolution of Programming Languages Assembly Languages
• Assembly languages (second-generation languages)
are only somewhat easier to work with than machine
languages.
• To create programs in assembly language, developers
use cryptic English-like phrases to represent strings
of numbers.
• The code is then translated into object code, using a
translator called an assembler.
Assembly
code
Assembler
Object code
The Evolution of Programming Languages Higher-Level Languages
Higher-level languages are more powerful than assembly
language and allow the programmer to work in a more
English-like environment.
Higher-level programming languages are divided into
three "generations," each more powerful than the last:
•
Third-generation languages
•
Fourth-generation languages
•
Fifth-generation languages
Higher-Level Languages Third-Generation Languages
• Third-generation languages (3GLs) are the first to
use true English-like phrasing, making them easier
to use than previous languages.
• 3GLs are portable, meaning the object code created
for one type of system can be translated for use on a
different type of system.
• The following languages are 3GLs:
FORTAN
COBOL
BASIC
Pascal
C
C++
Java
ActiveX
A Typical C Program Development Environment
• Phases of C Programs:
Editor
Disk
Preprocessor
Disk
Compiler
Disk
Linker
Disk
1. Program is created in the
editor and stored on disk
2. Preprocessor program
processes the code
3. Compiler creates object
code and stores it on disk.
4. Linker links the object
code with the libraries
2. Preprocess
3. Compile
4. Link
5. Load
Primary Memory
Loader
5. Loader puts program
in memory.
Disk
Primary Memory
CPU
1. Edit
6. CPU takes each instruction
and executes it, possibly
storing new data values as
the program executes
6. Execute
Higher-Level Languages Fourth-Generation Languages
• Fourth-generation languages (4GLs) are even easier
to use than 3GLs.
• 4GLs may use a text-based environment (like a 3GL)
or may allow the programmer to work in a visual
environment, using graphical tools.
• The following languages are 4GLs:
Visual Basic (VB)
VisualAge
Authoring environments
Higher-Level Languages Fifth-Generation Languages
• Fifth-generation languages (5GLs) are an issue of
debate in the programming community – some
programmers cannot agree that they even exist.
• These high-level languages would use artificial
intelligence to create software, making 5GLs
extremely difficult to develop.
• Solve problems using constraints rather than
algorithms, used in Artificial Intelligence
•Prolog
Summary
Hardware Description
Language
HDL
HDL

What and why HDL??
Hardware Description Language
(HDL)
Basic idea is a programming language to
describe hardware
 Initial purpose was to allow abstract
design and simulation



Design could be verified then implemented in
hardware
Now Synthesis tools allow direct
implementation from HDL code.

Large improvement in designer productivity
HDL

HDL allows write-run-debug cycle for
hardware development.



Similar to programming software
Much, much faster than design-implementdebug
Combined with modern Field
Programmable Gate Array chips large
complex circuits (>100000s of gates) can
be implemented.
HDLs

There are many different HDLs




VHDL is the most common




Verilog HDL
ABEL
VHDL
Large standard developed by US DoD
VHDL = VHSIC HDL
VHSIC = Very High Speed Integrated Circuit
Verilog HDL is second most common


Easier to use in many ways = better for teaching
C - like syntax
Verilog HDL

Verilog constructs are use defined
keywords


Examples: and, or, wire, input output
One important construct is the module


Modules have inputs and outputs
Modules can be built up of Verilog primatives
or of user defined submodules.
Example: Simple Circuit HDL
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or
g3(x,e,y);
endmodule
HDL Summary
Hardware Description Languages allow
fast design and verification of digital
circuits.
 Accurate simulation and testing requires
delays and inputs to be specified.
 There are three different levels of
abstraction for modelling circuits.

System Design Language
Hardware and Software
Co-design
Traditional Design Flow
26
HW/SW Codesign Flow
Concurrent design
between hardware
and software using
 Co-simulation
 Co-synthesis
27
Codesign Language

Software Description
Language (SDL)

People know C, so
how about languages
built on C/C++?



SystemC
SpecC
Handel-C

Hardware Description
Language (HDL)
Has no tool support. Only useful for influencing other languages.
Lacks CAD tool support
Proprietary: Not universally available
SystemC History
VSIA SLD Data
Types Spec (draft)
Synopsys
Synopsys
ATG
“Scenic”
UC
Irvine
SystemC
v0.90
Sep. 99
Synopsys
“Fridge”
1996
Frontier Design
A/RT Library
Fixed Point
Types
SystemC
v1.0
Apr. 00
1991
imec
1992
CoWare
“N2C”
1997
Abstract
Protocols
SystemC
v1.1
Jun. 00
SystemC Highlights







Features as a codesign language
Modules
Processes
Ports
Signals
Rich set of port and signal
types
Rich set of data types






Clocks
Cycle-based simulation
Multiple abstraction levels
Communication protocols
Debugging support
Waveform tracing
Current System Design Methodology
C/C++
System Level Model
Refine
Manual Conversion
Analysis
Results

Problems



Errors in manual conversion from C
to HDL
Disconnect between system model
and HDL model
Multiple system tests
VHDL/Verilog
Simulation
Synthesis
Rest of Process