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Arithmetic Building Blocks Today: • First Hour: Signed Arithmetic – Section 5.1 of Katz’s Textbook – In-class Activity #1 • Second Hour: Adder Circuits. • Section 5.1 of Katz’s Textbook – In-class Activity #2 1 Recap: • Building Blocks we’ve learned about thus far: – Programmable Logic Arrays – Multiplexors & De-multiplexors – Read-only Memory Today: Representation of Negative Numbers Building Blocks: Adders and Subtractors 2 Sign & Magnitude Representation 4 bit example -7 -6 1111 1110 -5 +0 + sign +1 0000 0001 1101 0010 +2 -4 1100 0011 +3 0 100 = + 4 -3 1011 0100 +4 1 100 = - 4 -2 1010 0101 1001 -1 +5 0110 1000 -0 0111 +6 - sign +7 • Sign equals the High order bit: 0 = positive or zero (non-negative) 1 = negative • Magnitude equals the three low order bits: 0 = 000 thru 7 = 111 • The number range = 7 for 4 bit numbers; for n bits, 2n-1 -1 • Two Representations for 0 (redundant & problematic) 3 Sign & Magnitude Addition Operands have the same sign Sign of the result: the same as the operands' sign 4 0100 -4 1100 +3 0011 + (-3) 1011 7 0111 -7 1111 (Don’t add sign bits) Operands have different signs Sign of the result: 4 the sign of operand with the larger magnitude + (-3) 0100 -4 1100 1011 +3 0011 Magnitude of the result: subtraction operation 0001 -1 1001 1 4 Sign & Magnitude Subtraction Operands have the same sign Sign of the result: the same as the operands' sign 4 0100 -4 1100 -3 0011 - (-3) 1011 1 0001 -1 1001 (Don’t subtract sign bits) Operands have different signs Sign of the result: the sign of operand with the larger magnitude Magnitude of the result: addition operation 4 0100 -4 1100 - (-3) 1011 -3 0011 7 0111 -7 1111 5 Sign & Magnitude • Addition – Addition when signs of operand the same – Subtraction when signs of operands differ – Must compare magnitudes to determine sign of result • Subtraction – Subtraction when signs of operand the same – Addition when signs of operands differ – Must compare magnitudes to determine sign of result • Complicated implementation – Adder unit – Subtractor unit – Comparator unit 6 Signed Representations Sign Magnitude One's Complement 000 = +0 000 = +0 001 = +1 001 = +1 010 = +2 010 = +2 011 = +3 011 = +3 100 = - 0 100 = - 3 101 = - 1 101 = - 2 110 = - 2 110 = - 1 111 = - 3 111 = - 0 Two's Complement 000 = +0 001 = +1 010 = +2 011 = +3 100 = - 4 101 = - 3 110 = - 2 111 = - 1 Issues: balance, number of zeros, ease of operations Two’s complement is ideal because hardware is simpler Same circuit for addition and subtraction 7 Pizza Pie Diagram 2 010 3 -4 1 001 0 011 000 100 111 101 -3 Only one zero -1 110 -2 8 MSB = The Sign Bit 2 010 3 -4 1 001 0 011 000 100 111 101 -3 110 -2 -1 MSB=0 For zero and positive numbers Positive numbers are the same as in Sign-Magnitude 9 MSB = The Sign Bit 2 010 3 -4 1 001 0 011 000 100 111 101 -3 110 -1 MSB=1 For negative numbers -2 10 More Negative Numbers than Positives 2 010 3 One more negative number. No +4 -4 1 001 0 011 000 100 111 101 -3 -1 110 -2 11 Recognizing Overflow 2 010 3 3+1 = -4 Wrong sign Indicates overflow -4 1 001 0 011 000 100 111 101 -3 -1 110 -2 12 Twos-Complement Calculations Carries 5 3 -8 0111 0101 0011 1000 Carries -7 -2 7 1000 1001 1110 0111 overflow overflow Carries 5 2 7 0000 0101 0010 0111 no overflow Carries -3 -5 -8 1111 1101 1011 1000 no overflow Overflow occurs when the carry in to the sign position does not equal the carry out of the sign position Also, wrong sign Overflow 13 Twos-Complement • Addition – Addition not dependent on the signs of operand – No need to compare magnitudes to determine sign of result • Subtraction – Subtraction is treated as an addition – Add the negative of the subtrahend to the minuend • Simple implementation – Adder unit – Negation circuit unit Simpler addition/subtraction scheme makes twos-complement the most common choice for integer number systems within digital systems 14 Do Activity #1 Now Get to know two’s complement arithmetic 15 Half Adder Adder With twos-complement, adders are sufficient Ai Bi Ai Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Sum Bi Half-adder Carry 16 Full Adder A 0 0 0 0 1 1 1 1 B CI 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 S 0 1 1 0 1 0 0 1 CO 0 0 0 1 0 1 1 1 AB CI 00 01 11 10 0 0 1 0 1 1 1 0 1 0 S AB CI 00 01 11 10 0 0 0 1 0 1 0 1 1 1 CO S = A B CI CO = B CI + A CI + A B = (A + B) CI + A B 17 Multi-Bit Adder using Full Adder Units A3 B3 A2 B2 A1 B1 FA FA FA C4 S3 C3 S2 C2 S1 A0 B0 C0 FA C1 S0 18 Full Adder Full Adder from Half Adders Standard Approach: 6 Gates A B S CI A B CI CO A B Alternative Implementation: 5 Gates - 2 XOR, 2 AND, & 1 OR A B S AB Half AdderCO A B Half S AdderCO S = A B CI S (A B) CI CI + CO CO = A B + (A B) CI = A B + B CI + A CI 19 Adder/Subtractor A3 B3 B3 A2 B2 B2 0 1 Sel A B CO + CI A1 B1 B1 0 1 Sel 0 1 Sel A B CO + CI A0 B0 B0 A B CO + CI 0 1 Sel A B CO + S S S S S3 S2 S1 S0 CI Add/Subtract 2s complement negative Overflow A - B = A + (-B) = A + (B + 1) 20 How Fast is it? Inputs Ai & Bi are available immediately, @ time 0 The CI from lower bit additions take time. Suppose CI is available @ time N @0 A @1 one gate delay from N to compute S @0 B S @N CI @0 A @0 B @N CI @0 @0 A B @N+ 1 @1 two gate delays from N to compute CO @N+ 1 CO @N+ 2 @1 21 The Carry bit Ripples Slowly Critical delay: the propagation of carry from low to high order stages 4 stage adder C0 A0 B0 S0 @2 0 C1 @3 A1 B1 S1 @4 1 C2 @5 A2 B2 2 S2 @6 C3 @7 A3 B3 3 S3 @8 C4 @9 Notation: @n means signal is available after n gate delays 22 Timing Diagram The propagation of carry from low to high order stages S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid 1111 + 0001 worst case addition T0 T2 T4 T6 T8 T0: Inputs to the adder are valid T2: Stage 0 carry out (C1) T4: Stage 1 carry out (C2) N + 2 delays to compute sum But last carry is not ready until 6 delays later, N = 6 T6: Stage 2 carry out (C3) T8: Stage 3 carry out (C4) 23 A Faster Adder To make our adder faster, we must compute the carry faster Just how fast can it be? Ultimately, the adder is just a large combinational circuit. We should be able to realize it using 2-state logic. Price to pay: more gates. Plan: Express each carry directly in terms of the Ai , Bi, and C0 24 Observe: A B CI S CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 CO = 0 CO = CI if A B, Carry out =Carry in CO = CI CO = 1 CARRY PROPAGATED (if AB=1, Carry out =1 regardless of carry in) CARRY GENERATED 25 Carry Lookahead Logic Let CI = Ci , then CO = Ci+1 Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai Bi carry in will equal carry out here Si = Ai Bi Ci = Pi Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai Bi) show logical equivalence = Gi + Ci Pi 26 Expand it out C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0! 27 Implementation Ai Bi Pi @ 1 gate delay Ci Si @ 2 gate delays Adder with Sum, Propagate and Generate Outputs Increasingly complex logic Gi @ 1 gate delay C0 P0 C1 G0 C0 P0 P1 G0 P1 C2 C0 P0 P1 P2 G0 P1 P2 G1 P2 G2 G1 C0 P0 P1 P2 P3 C3 G0 P1 P2 P3 G1 P2 P3 G2 P3 G3 C4 28 Carry Lookahead Delays First Level Carry Lookahead C0 Carry lookahead logic generates individual carries @3 A0 S0 @2 B0 C1 @3 A1 S1 @4 B1 Reduced slowest output from 8 to 4 gate delays! C2 @3 A2 S2 @4 B2 C3 @3 A3 S3 @4 Result: sums computed faster B3 C4 @3 29 Building Larger Adders Second Level Carry Look-ahead 4 4 4 C16 A[15-12]B[15-12] C12 4-bit Adder P G 4 @8 S[15-12] @2 @3 C16 @5 P3 C4 G3 4 4 A [11-8] B[11-8] C 8 4-bit Adder P G 4 @8 S[11-8] @5 C3 @2 @3 P2 G2 4 A[7-4] B[7-4] 4-bit Adder P G 4 @7 S[7-4] @5 C2 @2 @3 P1 G1 4 4 A[3-0] B[3-0] 4-bit Adder P G C4 4 C0 @0 @4 S[3-0] @4 C1 @2 @3 P0 G0 C0 Lookahead Carry Unit P3-0 @3 G3-0 C0 @0 @5 4 bit adders with internal carry look-ahead Second level carry lookahead unit, extends look-ahead to 16 bits 30 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: • Bring Randy Katz Textbook, & TTL Data Book • Required Reading: – Sec 3.4 & 5.3 of Katz • This reading is necessary for getting points in the Studio Activity! 31