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Lectures 16
Transfer Characteristics
(Delay and Power)
Feb. 10, 2003
Modern VLSI Design 3e: Chapters 3 & 8
week6-1
Partly from 2002 Prentice Hall PTR
Topics

Electrical properties of static combinational
gates:
– Noise margin and transfer curve;
– delay;
– power.
Modern VLSI Design 3e: Chapters 3 & 8
week6-2
Partly from 2002 Prentice Hall PTR
Delay

Assume ideal input (step), RC load.
Modern VLSI Design 3e: Chapters 3 & 8
week6-3
Partly from 2002 Prentice Hall PTR
Delay assumptions

Assume that only one transistor is on at a
time. This gives two cases:
– rise time, pullup on;
– fall time, pullup off.

Assume resistor model for transistor.
Ignores saturation region and
mischaracterizes linear region, but results
are acceptable.
Modern VLSI Design 3e: Chapters 3 & 8
week6-4
Partly from 2002 Prentice Hall PTR
Current through transistor

Transistor starts in saturation region, then
moves to linear region.
Modern VLSI Design 3e: Chapters 3 & 8
week6-5
Partly from 2002 Prentice Hall PTR
Resistive model for transistor

Average V/I at two voltages:
– maximum output voltage
– middle of linear region

Voltage is Vds, current is given Id at that
drain voltage. Step input means that Vgs =
VDD always.
Modern VLSI Design 3e: Chapters 3 & 8
week6-6
Partly from 2002 Prentice Hall PTR
Resistive approximation
Modern VLSI Design 3e: Chapters 3 & 8
week6-7
Partly from 2002 Prentice Hall PTR
Ways of measuring gate delay
Delay: time required for gate’s output to
reach 50% of final value.
 Transition time: time required for gate’s
output to reach 10% (logic 0) or 90% (logic
1) of final value.

Modern VLSI Design 3e: Chapters 3 & 8
week6-8
Partly from 2002 Prentice Hall PTR
Inverter delay circuit

Load is resistor + capacitor, driver is
resistor.
Modern VLSI Design 3e: Chapters 3 & 8
week6-9
Partly from 2002 Prentice Hall PTR
Inverter delay with t model
t model: gate delay based on RC time
constant t.
 Vout(t) = VDD exp{-t/(Rn+RL)/ CL}
 tf = 2.2 R CL
 For pullup time, use pullup resistance.

Modern VLSI Design 3e: Chapters 3 & 8
week6-10
Partly from 2002 Prentice Hall PTR
t model inverter delay

0.5 micron process:
– Rn = 3.9 kW
– Cl = 0.68 fF

So
– td = 0.69 x 3.9 x .68E-15 = 1.8 ps.
– tf = 2.2 x 3.9 x .68E-15 = 5.8 ps.
Modern VLSI Design 3e: Chapters 3 & 8
week6-11
Partly from 2002 Prentice Hall PTR
Example 2

Delay
Modern VLSI Design 3e: Chapters 3 & 8
week6-12
Partly from 2002 Prentice Hall PTR
Power consumption analysis
Almost all power consumption comes from
switching behavior.
 Static power dissipation comes from
leakage currents.
 Surprising result: power consumption is
independent of the sizes of the pullups and
pulldowns.

Modern VLSI Design 3e: Chapters 3 & 8
week6-13
Partly from 2002 Prentice Hall PTR
Other models

Current source model (used in power/delay
studies):
– tf = CL (VDD-VSS)/Id
– = CL (VDD-VSS)/0.5 k’ (W/L) (VDD-VSS -Vt)2

Fitted model: fit curve to measured circuit
characteristics.
Modern VLSI Design 3e: Chapters 3 & 8
week6-14
Partly from 2002 Prentice Hall PTR
Power consumption
A single cycle requires one charge and one
discharge of capacitor: E = CL(VDD - VSS)2 .
 Clock frequency f = 1/t.
 Energy E = CL(VDD - VSS)2.
 Power = E x f = f CL(VDD - VSS)2.

Modern VLSI Design 3e: Chapters 3 & 8
week6-15
Partly from 2002 Prentice Hall PTR
Observations on power
consumption
Resistance of pullup/pulldown drops out of
energy calculation.
 Power consumption depends on operating
frequency.

– Slower-running circuits use less power (but not
less energy to perform the same computation).
Modern VLSI Design 3e: Chapters 3 & 8
week6-16
Partly from 2002 Prentice Hall PTR
Example 3

Power
Modern VLSI Design 3e: Chapters 3 & 8
week6-17
Partly from 2002 Prentice Hall PTR
Lectures 17
VHDL
Feb. 12, 2003
Modern VLSI Design 3e: Chapters 3 & 8
week6-18
Partly from 2002 Prentice Hall PTR
Basic VHDL
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Modern VLSI Design 3e: Chapters 3 & 8
week6-19
Partly from 2002 Prentice Hall PTR
Topics
 Introduction
 VHDL Design

Example
Synthesis and VHDL
Modern VLSI Design 3e: Chapters 3 & 8
week6-20
Partly from 2002 Prentice Hall PTR
Reasons for Using VHDL

VHDL is an international IEEE standard
specification language (IEEE 1076-1993) for
describing digital hardware used by industry
worldwide
– VHDL is an acronym for VHSIC (Very High Speed
Integrated Circuit) Hardware Description Language

VHDL enables hardware modeling from the gate
to system level
VHDL provides a mechanism for digital design
and reusable design documentation
week6-21
Modern VLSI Design 3e: Chapters 3 & 8
Partly from 2002 Prentice Hall PTR

Gajski and Kuhn’s Y Chart
Architectural
Behavioral
Structural
Algorithmic
Systems
Functional Block
Processor
Hardware Modules
Algorithms
Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transistors
Transfer Functions
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Modern VLSI Design 3e: Chapters 3 & 8
Physical/Geometry
week6-22
Partly from 2002 Prentice Hall PTR
Putting It All Together
Package
Generics
Architectur
e
Entity
Ports
Architectur
e
Concurren
Concurren
t
t
Statement
Modern
VLSI Design 3e: Chapters 3 & 8
Statement
s
Architectur
e
Process
week6-23
Sequential
Partly from 2002 Prentice Hall PTR
Statements
VHDL Design Example

Problem: Design a single bit half adder with carry
and enable

Specifications
–
–
–
–
Inputs and outputs are each one bit
When enable is high, result gets x plus y
When enable is high, carry gets any carry of x plus y
Outputs are zero when enable input is low
x
carry
y
Half Adder
result
enable
Modern VLSI Design 3e: Chapters 3 & 8
week6-24
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Entity Declaration
 As
a first step, the entity declaration
describes the interface of the component
– input and output ports are declared
ENTITY half_adder IS
PORT( x, y, enable: IN BIT;
carry, result: OUT BIT);
END half_adder;
x
y
enable
Modern VLSI Design 3e: Chapters 3 & 8
week6-25
Half
Adder
carry
result
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Behavioral Specification

A high level description can be used to describe
the function of the adder
ARCHITECTURE half_adder_a OF half_adder IS
BEGIN
PROCESS (x, y, enable)
BEGIN
IF enable = ‘1’ THEN
result <= x XOR y;
carry <= x AND y;
ELSE
carry <= ‘0’;
result <= ‘0’;
END IF;
END PROCESS;
END half_adder_a;

The model can then be simulated to verify correct
functionality of the component
Modern VLSI Design 3e: Chapters 3 & 8
week6-26
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Data Flow Specification

A second method is to use logic equations to
develop a data flow description
ARCHITECTURE half_adder_b OF half_adder IS
BEGIN
carry <= enable AND (x AND y);
result <= enable AND (x XOR y);
END half_adder_b;

Again, the model can be simulated at this level to
confirm the logic equations
Modern VLSI Design 3e: Chapters 3 & 8
week6-27
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Structural Specification

As a third method, a structural description can be
created from predescribed components
x
y
enable
carry
result

These gates can be pulled from a library of parts
Modern VLSI Design 3e: Chapters 3 & 8
week6-28
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Structural Specification (Cont.)
ARCHITECTURE half_adder_c OF half_adder IS
COMPONENT and2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT and3
PORT (in0, in1, in2 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT xor2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);
FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
-- description is continued on next slide
Modern VLSI Design 3e: Chapters 3 & 8
week6-29
Partly from 2002 Prentice Hall PTR
VHDL Design Example
Structural Specification (cont.)
-- continuing half_adder_c description
SIGNAL xor_res : BIT; -- internal signal
-- Note that other signals are already declared in entity
BEGIN
A0 : and2 PORT MAP (enable, xor_res, result);
A1 : and3 PORT MAP (x, y, enable, carry);
X0 : xor2 PORT MAP (x, y, xor_res);
END half_adder_c;
Modern VLSI Design 3e: Chapters 3 & 8
week6-30
Partly from 2002 Prentice Hall PTR
Synthesis and VHDL
 Logic
synthesis
 Rewrite the half-adder to synthesized VHDL
– Library
– Std_logic and std_logic_vector
Modern VLSI Design 3e: Chapters 3 & 8
week6-31
Partly from 2002 Prentice Hall PTR
Full Adder Example
Modern VLSI Design 3e: Chapters 3 & 8
week6-32
Partly from 2002 Prentice Hall PTR
Lectures 18
Synopsys Tutorial
Feb. 14, 2003
Modern VLSI Design 3e: Chapters 3 & 8
week6-33
Partly from 2002 Prentice Hall PTR
Synopsys and VHDL

Lab 2
Modern VLSI Design 3e: Chapters 3 & 8
week6-34
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapters 3 & 8
week6-35
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapters 3 & 8
week6-36
Partly from 2002 Prentice Hall PTR