Download VLSI DEsign Methodology

The Devices:
MOS Transistor
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
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The MOS Transistor
Gate Oxyde
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
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Field-Oxyde
(SiO2)
p+ stopper
MOS transistors Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
G
S
PMOS Enhancement
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D
B
S
NMOS with
Bulk Contact
Channel
MOSFET Static Behavior
VGS =0
Mobile electrons
Depletion Region
With drain and source grounded, and VGS = 0, both back-to-back (subsource, sub-drain) junctions have 0V bias and are OFF
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MOSFET Static Behavior
Positive voltage applied to the gate (VGS > 0)
•The gate and substrate form the plates of a capacitor.
•Negative charges accumulate on the substrate side (repels mobile holes)
•A depletion region is formed under the gate (like pn junction diode)
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
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B
Inversion
As the VGS increases, the surface under the gate undergoes inversion to ntype material. This is the beginning of a phenomenon called strong
inversion.
Further increases in VGS do not change the width of the depletion layer,
but result in more electrons in the thin inversion layer, producing a
continuous channel from source to drain
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The Threshold Voltage
The value of VGS where strong inversion occurs is called the Threshold
Voltage, VT , and has several components:
•The flat-band voltage, VFB , is the built-in voltage offset across the MOS
structure and depends on fixed charge and implanted impurities charge
on the oxide-silicon interface
•VB represents the voltage drop across the depletion layer at inversion and
equals to minus twice the Fermi potential ~(0.6V)
•Vox represents the potential drop
across the gate oxide
VT  VFB  VB  Vox
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The Threshold Voltage
Where:
F is the Fermi potential ( ~ -0.3V for ptype substrates
Cox is the gate oxide capacitance
VSB is the substrate bias voltage
VT0 is VT at VSB = 0
Note:
VT is positive for NMOS transistors and
negative for PMOS
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The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1
-1.5
V
BS
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(V)
-0.5
0
Current-Voltage Relations
Assume VGS > VT
•A voltage difference VDS will cause ID to flow from drain to source
•At a point x along the channel, the voltage is V(x), and the gate-tochannel voltage is VGS - V(x)
•For channel to be present from drain to source, VGS - V(x) > VT,
i.e. VGS - VDS > VT for channel to exist from drain to source
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
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MOS transistor and its bias conditions
Linear (triode) Region
•When VGS - VDS > VT , the channel exists from drain to source
•Transistor behaves like voltage controlled resistor
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Saturation Region
•When VGS - VDS  VT , the channel is pinched off
•Electrons are injected into depletion region and accelerated
towards drain by electric field
•Transistor behaves like voltage-controlled current source
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Pinch-off
Current-Voltage Relations
Long-Channel Device
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Current-Voltage Relations
Long Channel transistor
6
x 10
-4
VGS= 2.5 V
5
VDS = VGS - VT
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
Quadratic
Relationship
VDS = VGS - VT
2
VGS= 1.5 V
cut-off
1
0
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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A model for manual analysis
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