Download ppt

CSCE 612: VLSI System Design
Instructor: Jason D. Bakos
MOSFET Theory
p-type body:
majority carriers
are holes
accumulation
mode
Vt depends on
doping and tox
VLSI System Design 2
Regions of Operation
Gate to channel:
Vgs near source
Vgd near drain
Switching delay is
determined by:
• time required to
charge/discharge gate
drain
• time for current to
travel across channel
VLSI System Design 3
Ideal I-V Characteristics
I ds 
Qchannel
carrier time
Q  CV
Linear region
Vgc  Vgs 
C g   ox
WL
tox
Qchannel  C g Vgc  Vt 
V


Qchannel  C g Vgs  sd  Vt 
2



Cox  ox
C g  CoxWL
(charge)
Vsd
2
 ox  3.9   0
 0  8.85 10 14 F / cm
tox
V


Qchannel  CoxWLVgs  sd  Vt 
2


v  E
V
E  ds
L
(carrier velocity,  is mobility)
(electric
field)
L
v
L2
carrier time 
Vds
carrier time 
V
v   ds
L
I ds 
Qchannel
carrier time
V 
W
Vgs  Vt  ds Vds
L
2 
V 

I ds   Vgs  Vt  ds Vds
2 

V 
W
I ds  k ' Vgs  Vt  ds Vds
L
2 
I ds  Cox
VLSI System Design 4
Ideal I-V Characteristics
Saturation region:
Vds  Vgs  Vt
  Cox
into equation…


0, Vgs  Vt

V 

I ds   Vgs  Vt  ds Vds , Vds  Vdsat
2 
 

2



V

V
, Vds  Vdsat
gs
t

2
Holes have less mobility
than electrons, so pmos’s
provide less current (and
are slower) than nmos’s of
the same size
W
L
nmos
cutoff
linear
saturation
n
2
3
p
pmos
Which parameters do we change
to make MOSFETs faster?
VLSI System Design 5
Nonideal I-V Effects
• Velocity saturation and mobility degradation
– Lower Ids than expected
• At high lateral field strength (Vds/L), carrier velocity stops increasing linearly with field
strength
• At high vertical field strength (Vgs / tox) the carriers scatter more often
• Channel length modulation
– Saturation current increases with higher Vds
• Subthreshold conduction
– Current drops exponentially when Vgs drops below Vt (not zero)
• Body effect
– Vt affected by source voltage relative to body voltage
• Junction leakage
– S/D leaks current into substrate/well
• Tunneling
– Gate current due to thin gate oxides
• Temperature dependence
– Mobility and threshold voltage decrease with rising temperature
VLSI System Design 6
C-V Characteristics
• Capacitors are bad
– Slow down circuit (need to use more power), creates
crosstalk (noise)
• Gate is a good capacitor
– Gate is one plate, channel is the other
– Needed for operation: attracts charge to invert channel
• Source/drain are also capacitors to body (p-n junction)
– Parasitic capacitance
– “Diffusion capacitance”
– Depends on diffusion area, perimeter, depth, doping levels,
and voltage
• Make as small as possible (also reduces resistance)
VLSI System Design 7
Gate Capacitance
• Gate’s capacitance
–
–
–
–
–
–
Relative to source terminal
Cgs=COXWL
Assuming minimum length…
Cgs=CperW
Cper = COXL = (OX/tOX)L
Fab processes reduce length and oxide thickness
simultaneously
• Keeps Cper relatively constant
• 1.5 – 2 fF / um of width
VLSI System Design 8
Gate Capacitance
Five components:
Intrinsic:
Cgb, Cgs, Cgd
Overlap:
Cgs(overlap), Cgd(overlap)
C0 = WLCox
Parameter
Cutoff
Linear
Saturation
Cgb
C0
0
0
Cgs
0
C0/2
2/3 C0
Cgd
0
C0/2
0
Sum
C0
C0
2/3 C0
Cgsol=Cgdol=0.20.4 fF / um of
width
VLSI System Design 9
Parasitic Capacitance
• Source and drain capacitance
– From reverse-biased PN junction (diffusion to
body)
– Csb, Cdb
– Depends of area and perimeter of diffusion,
depth, doping level, voltage
– Diffusion has high capacitance and resistance
• Made small as possible in layout
– Approximately same as gate capacitance (1.5 –
2 fF / um of gate width)
Isolated, shared, and merged
diffusion regions for transistors in
series
VLSI System Design 10
Switch-Level RC Delay Models
Delay can be
estimated as
R * 6C
FET passing weak
value has twice
the resistance
VLSI System Design 11