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Metal-Oxide-Semicondutor FET
(MOSFET)
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Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to
100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
Copyright  2004 by Oxford University Press, Inc.
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Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate.
Copyright  2004 by Oxford University Press, Inc.
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Device structure of MOSFET (n-type)
Source(S)
Gate(G)
(SiO2)
n+
Drain(D)
Oxide
Metal
Channel area
n+
p-type Semiconductor
Substrate (Body)
Body(B)

For normal operation, it is needed to create a
conducting channel between Source and Drain
2017/5/23
SJTU
J. Chen
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Creating a channel for current flow
An n channel can be induced at
the top of the substrate beneath
the gate by applying a positive
voltage to the gate
The channel is an inversion
layer
The value of VGS at which a
sufficient number of mobile
electrons accumulate to form a
conducting channel is called the
threshold voltage (Vt)
2017/5/23
SJTU
J. Chen
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Device structure of MOSFET (n-type)
L = 0.1 to 3 mm
W = 0.2 to 100 mm
Tox= 2 to 50 nm
Cross-section view
2017/5/23
SJTU
J. Chen
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Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is
determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS.
Note that the depletion region is not shown (for simplicity).
Copyright  2004 by Oxford University Press, Inc.
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Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered
shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
Copyright  2004 by Oxford University Press, Inc.
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Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS,
is kept small. The device operates as a linear resistor whose value is controlled by vGS.
Copyright  2004 by Oxford University Press, Inc.
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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated
with vGS > Vt.
Copyright  2004 by Oxford University Press, Inc.
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Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is
formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.
Copyright  2004 by Oxford University Press, Inc.
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Complementary MOS or CMOS
 The PMOS transistor is formed in n well.
 Another arrangement is also possible in which an n-type body is used and
the n device is formed in a p well.
 CMOS is the most widely used of all the analog and digital IC circuits.
2017/5/23
Copyright  2004 by Oxford University Press, Inc.
SJTU
J. Chen
The Junction Field Effect Transistor (JFET)
Figure: n-Channel JFET.
Copyright  2004 by Oxford University Press, Inc.
Biasing the JFET
Figure: n-Channel JFET and Biasing Circuit.
Copyright  2004 by Oxford University Press, Inc.
Operation of JFET at Various Gate Bias
Potentials
Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)
Copyright  2004 by Oxford University Press, Inc.
Operation of a JFET
Drain
N
Gate
+
P
P
-
+
-
N
Source
Copyright  2004 by Oxford University Press, Inc.
+
Characteristics of n-JFET
Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.
Copyright  2004 by Oxford University Press, Inc.
n-Channel JFET
Figure: n-Channel FET for vGS = 0.
Copyright  2004 by Oxford University Press, Inc.
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Junction FET
D
Depletion
layer
P+
N-channel
G
n-type
Semiconductor
S
D
P+
G
S
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Physical operation under vDS=0
D
D
D
P+
P+
G
S
UGS = 0
P+
P+
G
P+
P+
G
S
UGS < 0
S
UGS = UGS(off)
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The effect of UDS on ID for UGS(off) <UGS < 0