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POLITECNICO DI BARI
Front-end for Silicon Photomultiplier (SiPM)
SiPM: Silicon photomultiplier
MATRICE DI FOTODIODI
A VALANGA
POLARIZZATI IN GEIGER
MODE
MOLTIPLICAZIONE DEI
PORTATORI TRAMITE IL
PROCESSO A VALANGA
AMPIEZZA
DELl’IMPULSO DI USCITA
PROPORZIONALE AL
NUMERO DI FOTONI
ASSORBITI
24x24 pixels
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Electrical model of a SiPM
Rq: quenching resistor
(hundreds of kW)
Cd: photodiode capacitance
(few tens of fF)
Cq: parasitic capacitance in parallel to Rq (smaller
than Cd)
IAV: current source modelling the total charge
delivered by a microcell during the avalanche

Cg : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with a metal grid.
Example: metal-substrate unit area capacitance 0.03 fF/mm2
metal grid = 35% of the total detector area = 1mm2
Cg  10pF, without considering the fringe
parasitics
 Avalanche time constants much faster than those introduced by the circuit:
IAV can be approximated as a short pulse containing the total amount of charge delivered by the
firing microcell Q=DV(Cd+Cq), with DV=VBIAS-VBR
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Experimental validation of the model
Two different amplifiers have been used to read-out the FBK-irst SiPM
a)
Transimpedance amplifier
BW=80MHz Rs=110W Gain=2.7kW
b)
Voltage amplifier
BW=360MHz Rs=50W Gain=140
• The model extracted according to the procedure described above has been used in the SPICE simulations
• The fitting between simulations and measurements is quite good
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Front-end electronics: different approaches
Vbias
Vbias
CF
Vbias
SiPM
SiPM
+
VOUT
Charge sensitive amplifier
RS
SiPM
+
-
VOUT
Voltage amplifier
RS
IS
kIS=IOUT
Current amplifier
The charge Q delivered by the
detector is collected on CF
A I-V conversion is realized by
means of RS
RS is the (small) input impedance of
the current buffer
If the maximum DVOUT is 3V and Q
is 50pC (about 300 SiPM
microcells), CF must be 16.7pF
The value of RS affects the gain
and the signal waveform
The output current can be easily
replicated (by means of current
mirrors) and further processed (e.g.
integrated)
VOUT must be integrated to extract
the charge information: thus a
further V-I conversion is needed
Perspective limitations in dynamic
range, die area, power
consumption
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The circuit is inherently fast
Less problems of dynamic range
The CMOS current buffer

0.35mm standard CMOS technology

Common gate configuration (M1)

Feedback applied to increase
bandwidth and decrease input
resistance (M3, M2)

SiPM bias (and gain) fine tuning
possible by varying Vrif
Main simulated specs




Small signal bandwidth: 250MHz
Total current consumption: 800uA
Rise time of the output waveform: 400ps
Vrif variable in the range 1V÷2V
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 Input resistance: 17W
 Linearity dynamic range: about 50pC
 3.3V power supply
Experimental setup: blue LED light source
Vrif
Current
Buffer
Voltage
Amplifier
BNC
Pulse
Generator
Blue
Led
SiPM
50Ω
RIV
Iout
Vbias
The circuit has been coupled to a SiPM realized by FBK-Irst
7V
Picture of the setup
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Single dark pulse measurement (Vbr=-30.5V; Vbias=-32.5V)
Dark pulse measurements
Charge measurements at Vbias = -32.5V
Comparison with a very fast discrete voltage
amplifier front-end, used as a reference:
Average dark pulse charge
•
Integrated current buffer: 143fC
•
Discrete voltage amplifier: 142fC
The standard deviation is worse:
sint2sdisc
Blue LED measurements
Comparison with the ref. amplifier :
Average no. of fired microcells
• Current buffer: 39
• Ref. amplifier: 38.4
Standard deviation
• Current buffer: 7.5
• Ref. Amplifier: 7.2
Average number of fired microcells as
a function of the input pulse width
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Charge distribution for a 8.25ns input pulse
width (in terms of no. of fired microcells)
Architecture of the analog channel
 Variable gain integrator: Gain: 1V/pC  0.33V/pC (2 bits);
f = 200ns;
Output voltage range: 0.3V ÷ 2.7V;
Current mirror scaling factor 10:1
 Current discriminator:
Current mirror scaling factor 1:1;
Threshold variable from 0 to 40µA (about 50 microcells @ VBIAS=-31.5V);
 Baseline holder :
Baseline value Vbl = 300mV
Very slow time constant;
Non-linearities added to prevent baseline shifts at increasing event rates
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Experimental setup: LED light source
Voltage Buffer
50Ω
Ch_out
Ch_in
Pulse
Generator
Blue
Led
Lemo
Chip
Disc
SiPM
Logic Buffer
Lemo
Vbias
 SiPM A51 ( FBK – IRST )
 Blue Led HSMB-C150
Typical output waveforms
(Vbias=31.5V)
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Charge measurements (blue LED light source)
Ouput voltage vs pulse width for different gain settings
From the previous characterization measurements we have:
For pulse width = 9ns, n=115 fired microcells

If Vbias = 31.5 V, the total injected charge is QT= Q µcell(31.5V)*n = 6.9pC
If Vbias = 32.5 V, the total injected charge is QT= Q µcell(32.5V)*n = 17.3pC
Vbias
31.5V
32.5V
QT/(M*Cf)
690mV
1.73V
Vpeak-Vbl
670mV
1.76V
Measurement are in good agreement with the expected results
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Design of the 8 channel ASIC: the Peak Detector (PD)
VDD
M1
Integrator output
M2
_
OTA
+
out
IBIAS
VDISC
MR
Chold=2pF
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reset
•
It is based on a P-MOS current mirror as
a rectifying element
•
IBIAS added to improve the speed of
operation, especially for small signals
Design of the 8 channel ASIC: the fast-OR
•
Fast-OR circuit operating in current mode, to improve the speed of operation
•
Current buffer to reduce the input impedence
•
Current discriminator with fixed treshold
Vdd
Ibias
trig_0
M0
Vdd
Vdd
Vbias
Ibias
trig_1
M1
I0
Vbias
MNBUF MPBUF
Cur_disc
Cbus
Ithresh
Vdd
Ibias
trig_7
I2
Ithresh= I2-(I0-I1)
M7
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I1
F_or
Architecture of the test chip
Curbuf
Ext.
bias
Curdisc
ch_0
Vrif
PD
CSA
I_th
a_out_0
trig_0
gain
ADC_ck
Curbuf
PD
CSA
a_out_1
reset_pad
Ext.
bias
Curdisc
ch_1
trig_1
data
ADC
MUX
ck_pad
Read_out
logic
EOC
Vrif
I_th
gain
data_pad
Vrif
Curbuf
Ext.
bias
PD
CSA
I_th
DAC
Vrif
a_out_7
MUX_sel
config_reg
MUX_reg
Vrif
I_th
srq_pad
gain
Trig.
reg.
trig_7
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DAC
I_th
gain
Curdisc
ch_7
rw_pad
F_or
Design of the 8 channel ASIC: Layout
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Read-out procedure for the test chip
CHIP
DATA
CLOCK
SRQ
RESET
DATA_0
CLOCK
SRQ
RESET
FPGA
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Package SMD
A)
An event activates the SRQ bus (by default at Hi-Z)
B)
FPGA gives a time-stamp to the event and takes control of
the SRQ bus during the read-out procedure
C)
SRQ, in its active state, is used to “freeze” the content of
the trigger registers (no more trigger are accepted)
D)
FPGA waits the time needed by the PDs to reach the peak
and sends the CLOCK signal to the ASICs
F)
The read-out logic starts the A/D conversions and sends
the results to FPGA on the DATA_i pad
G)
When all the conversions have been completed, FPGA
releases the SRQ bus and sends a RESET signal
Jitter measurements on fast-OR signal
Misure di jitter in presenza di un solo canale soprasoglia
Canale colpito
Valore medio del
Deviazione
ritardo
standard
1
1.77 ns
50 ps
2
1.66 ns
53 ps
3
1.68 ns
49 ps
4
1.69 ns
49 ps
5
1.74 ns
48 ps
6
1.57 ns
49 ps
7
1.66 ns
49 ps
8
1.67 ns
48 ps
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Misure di jitter in presenza di due canali soprasoglia
Coppia canali
Valore medio del
Deviazione
ritardo
standard
1-5
1.618 ns
47.26 ps
2-4
1.55 ns
50.5 ps
2-3
1.55 ns
48.6 ps
3-4
1.57 ns
49.7 ps
1-4
1.62 ns
49 ps
4-8
1.53 ns
50.3 ps
3-7
1.53 ns
50 ps
6-8
1.415 ns
50.5 ps
7-8
1.55 ns
50 ps
Design of the 32 channel ASIC: Logic Readout
pd_out_0
Vrif
I_th
gain
ex_ADC
DAC
Vrif
pd_out_1
MUX
DEMUX
ADC_2
DAC
I_th
data
MUX
config_reg
ADC_1
pd_out_31
reset_pad
DEMUX_reg
MUX_reg
MUX_reg
ADC/Clock Manager
Logic Readout
EOC
cK_ADC
rw_pad
coincidence_pad
ck_pad
trig_0
trig_1
Trig.
reg.
trig_31
SDI_pad
F_or
srq_pad
SDO_pad
SS
SPI interface
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