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Combinational Logic Circuits
Overview
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Integrated Circuits
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CMOS Circuits
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Integration Levels
Digital Logic Families
Positive/Negative Logic
Transmission Gates
Transistors and switch models
CMOS Networks
Fully Complementary CMOS
CMOS Transmission Gates
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Integrated Circuits (ICs)
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An IC is a silicon semiconductor crystal
(chip) that contains the electronic
components of digital gates.
Chip is mounted in a ceramic or plastic
container.
Connections are welded from the chip to
external pins.
# of pins varies (depending on the chip’s
functionality)
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Levels of Integration

Small-scale Integration (SSI)
Several independent gates (>10) per package (like the ones in
your H/W lab kit)
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Medium-scale Integration (MSI)
Between 10-100 gates per chip. Perform basic digital functions,
e.g. 4-bit addition.
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Large-scale Integration (LSI)
Between 100 and a few thousands of gates per chip. Implement
digital systems, e.g. small processors and memories.
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Very Large-scale Integration (VLSI)
Several thousands to over 100 million gates per chip, e.g.
complex microprocessors.
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Digital Logic Families
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ICs are also classified based on their specific
circuit technology, known as digital logic
family.
Each family has its own basic electronic
components (NAND, NOR, and NOT gates),
used to build complex digital circuits.
Various digital logic families have been
introduced and used over the years.
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Digital Logic Families
(in chronological order)
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RTL: Resistor-Transistor Logic
earliest,
now obsolete
DTL: Diode-Transistor Logic
TTL: Transistor-Transistor Logic
widely used
ECL: Emitter-coupled Logic
high-speed operation
MOS: Metal-Oxide Semiconductor
compact
CMOS: Complementary MOS
 Low power dissipation, currently the MOST DOMINANT
BiCMOS: Bipolar CMOS
 CMOS and TTL for additional current/speed
GaAs: Gallium-Arsenide
very high-speed operation
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Defining Characteristics of
Digital Logic Families
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Fan-in: # of gate inputs.
Fan-out: # of standard loads a gate’s output can
drive.
Noise margin: max external noise tolerated.
Power dissipation: power consumed by the gate
(dissipated as heat).
Propagation delay: time required for an input
signal change to be observed at an output line.
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Propagation Delay
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One of the most important design parameters (if
not THE most important!)
The maximum propagation delay (tpd)
determines the circuit’s speed.
tPHL: high-to-low propagation time
tPLH: low-to-high propagation time
tpd = max(tPHL, tPLH)
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Propagation Delay (cont.)
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Transport and Inertial Delays
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Two different models are used to simulate gates:
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Transport delay: change in output occurs after the
propagation delay.
Inertial delay: output change also occurs after the
propagation delay; in addition, if output changes twice in an
interval less than a predefined rejection time, then the 1st
change does not occur  filtering of spikes (gate output is
only sensitive to changes of duration at least as large as
the rejection time).
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Transport and Inertial Delay (cont.)
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Positive and Negative Logic
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Two different assignments of signal levels to logic
values:
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Positive logic:
 H 1
 L 0
Negative logic:
 H0
 L 1
IC data sheets define digital gates in terms of
signal values; user decides on positive or
negative logic.
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Demonstration of Positive/Negative Logic
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Positive and Negative Logic
(cont.)
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Conversion between positive and negative
logic:
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Interchange 0’s and 1’s at gate’s inputs and
outputs.
This is the same as taking the dual!
Remember to include/remove the polarity
indicators.
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CMOS Circuits
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Implementation of logic gates and other structures
using CMOS technology.
Basic element: transistor
2 types of transistors:
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n-channel (nMOS) and p-channel (pMOS)
Type depends on the semiconductor materials used to
implement the transistor (beyond our scope…).
We want to model transistor behavior at the logic level in order
to study the behavior of CMOS circuits  view pMOS and
nMOS transistors as swithes.
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CMOS transistors as Switches
3 terminals in CMOS transistors:
 G: Gate
 D: Drain
 S: Source
nMOS transistor/switch
X=1 switch closes (ON)
X=0 switch opens (OFF)
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pMOS transistor/switch
X=1 switch opens (OFF)
X=0 switch closes (ON)
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Networks of Switches
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Use switches to create networks that
represent CMOS logic circuits.
To implement a function F, create a network
s.t. there is a path through the network
whenever F=1 and no path when F=0.
Two basic structures:
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Transistors in Series
Transistors in Parallel
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Transistors in Series/Parallel
nMOS in Series
X
a
Y
a
X:X
Y:Y
b
nMOS in Parallel
Path between
points a and b
exists if both
X and Y are 1
 X•Y
a
X
X
Y
X:X’
Y:Y’
b
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a
X:X
b
b
Y:Y
b
Path between
points a and b
exists if either
X or Y are 1
 X+Y
pMOS in Parallel
pMOS in Series
a
Y
a
Path between
points a and b
exists if both
X and Y are 0
 X’•Y’
a
X
Y
b
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a
X:X
b
Y:Y
Path between
points a and b
exists if either
X or Y are 0
 X’+Y’
b
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Networks of Switches (cont.)
In general:
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1.
2.
3.
4.
nMOS in series is used to implement AND logic
pMOS in series is used to implement NOR logic
nMOS in parallel is used to implement OR logic
pMOS in parallel is used to implement NAND logic
Observe that:
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1 is the dual of 3, and vice-versa
2 is the dual of 4, and vice-versa
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CMOS Inverter
+V
X
F = X’
X
F = X’
Logic symbol
GRD
Transistor-level schematic
Operation:
 X=1  nMOS switch conducts (pMOS is open)
and draws from GRD  F=0
 X=0  pMOS switch conducts (nMOST is open)
and draws from +V  F=1
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Fully Complementary CMOS
Networks
Basic Gates
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Symbol to transistor
A
Y
B
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“NAND” Gate
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Fully Complementary CMOS
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Why is the pMOS network connected to +V
and the nMOS network to GRD?
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pMOS devices are “nearly” ideal when passing
HIGH voltage.
nMOS devices are “nearly” ideal when passing
LOW voltage.
Thus, the CMOS structure ensures that signal
values remain at appropriate HIGH and LOW
logic levels.
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Fully Complementary CMOS
Complex Gates
Given a function F:
1.
Find and simplify F’. Make sure complements are
down to the literal level.
2.
Implement F’ as a nMOS net and connect it to
GRD (pull-down net) and F.
3.
Find dual of F’, implement it as a pMOS net and
connect it to +V (pull-up net) and F.
4.
Connect switch inputs.
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Fully Complementary CMOS
Networks
Complex Gates - Example
F = AB’+AC+BC’
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CMOS Transmission Gate (TG)
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2-input MUX and XOR
using CMOS TGs
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CMOS Electrical
Characteristics
 Digital
analysis works only if circuits are
operated in spec:
 Power
supply voltage
 Temperature
 Input-signal quality
 Output loading
 Must
do some “analog” analysis to prove that
circuits are operated in spec.
 Fanout
specs
 Timing analysis (setup and hold times)
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DC Loading
 An
output must sink
current from a load
when the output is in
the LOW state.
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 An
output must source
current to a load when
the output is in the HIGH
state.
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Output-voltage drops
 Resistance
of “off” transistor is > 1 Megohm,
but resistance of “on” transistor is nonzero,
 Voltage
drops across “on” transistor, V = IR
 For
“CMOS” loads, current and voltage drop
are negligible.
 For TTL inputs, LEDs, terminations, or other
resistive loads, current and voltage drop are
significant and must be calculated.
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Example loading calculation
 Need
to know “on” and “off” resistances of
output transistors, and know the
characteristics of the load.
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Calculate for LOW and HIGH
state
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Limitation on DC load
 If
too much load, output voltage will go outside
of valid logic-voltage range.
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 VOHmin,
VIHmin
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Output-drive specs
 VOLmax
and VOHmin are specified for certain outputcurrent values, IOLmax and IOHmax.
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No need to know details about the output circuit, only the
load.
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Input-loading specs
Each gate input requires a certain amount of current to drive it in
the LOW state and in the HIGH state.
 IIL and IIH
 These amounts are specified by the manufacturer.
 Fanout calculation
 (LOW state) The sum of the IIL values of the driven inputs may
not exceed IOLmax of the driving output.
 (HIGH state) The sum of the IIH values of the driven inputs may
not exceed IOHmax of the driving output.
 Need to do Thevenin-equivalent calculation for non-gate loads
(LEDs, termination resistors, etc.)
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Manufacturer’s data sheet
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TTL Logic Levels and Noise
Margins
 Asymmetric,
 CMOS
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unlike CMOS
can be made compatible with TTL
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CMOS vs. TTL Levels
TTL levels
CMOS levels
CMOS with TTL Levels
-- HCT, FCT, VHCT, etc.
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TTL
differences
from
CMOS
 Asymmetric input and output characteristics.
 Inputs
source significant current in the LOW state,
leakage current in the HIGH state.
 Output can handle much more current in the LOW
state (saturated transistor).
 Output can source only limited current in the HIGH
state (resistor plus partially-on transistor).
 TTL has difficulty driving “pure” CMOS inputs
because VOH = 2.4 V (except “T” CMOS).
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AC Loading
 AC
loading has become a critical design
factor as industry has moved to pure CMOS
systems.
 CMOS
inputs have very high impedance, DC
loading is negligible.
 CMOS inputs and related packaging and wiring
have significant capacitance.
 Time to charge and discharge capacitance is a
major component of delay.
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Transition times
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Circuit for transition-time
analysis
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HIGH-to-LOW transition
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Exponential rise time
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LOW-to-HIGH transition
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Exponential fall time
t = RC time constant
exponential formulas, e-t/RC
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Transition-time considerations
 Higher
capacitance ==> more delay
 Higher on-resistance ==> more delay
 Lower on-resistance requires bigger transistors
 Slower transition times ==> more power dissipation
(output stage partially shorted)
 Faster transition times ==> worse transmission-line
effects (Chapter 11)
 Higher capacitance ==> more power dissipation
(CV2f power), regardless of rise and fall time
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Open-drain outputs
 No
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PMOS transistor, use resistor pull-up
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What good is it?
 Open-drain
 Problem
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bus
-- really bad rise time
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Open-drain transition times
resistance is larger than a PMOS transistor’s
“on” resistance.
 Pull-up
 Can
reduce rise time by reducing pull-up resistor
value
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But not too much
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