Download Digital Systems Topic 2: Logic Gates and Families: Definitions and Characteristics

Digital Systems
Topic 2: Logic Gates and Families:
Definitions and Characteristics
Objectives
• To review several basic logic gates
• To review positive and negative logic
• To become familiar with several static and
dynamic characteristics of several logic
families
– Understand fanout
– Noise margins
– Open collector/drain resistance calculations
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Logic Gate Forms
Negative Logic
Positive Logic
A
B
AB
A
B
A+B
A
B
A+B
A
B
AB
A
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A
A
A
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Application of Positive Logic
• Active Level:
TRUE = 1
• Quiescent Level:
FALSE= 0
Easier for us to analyze and interpret.
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X
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Application of Positive Logic
• Active Level:
TRUE = 1
• Quiescent Level:
FALSE = 0
Easier for us to analyze and interpret.
X
Application of Negative Logic
• Active Level:
TRUE = 0
• Quiescent Level:
FALSE = 1
Circuitry takes less space and draws less power.
X
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Application of Positive Logic
• Active Level:
TRUE = 1
• Quiescent Level:
FALSE = 0
Easier for us to analyze and interpret.
X
Application of Negative Logic
• Active Level:
TRUE = 0
• Quiescent Level:
FALSE = 1
Circuitry takes less space and draws less power.
X
Negative logic is more commonly used.
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Negative Logic Circuitry
• Consider for a moment, the schematic diagram of
an inverting buffer:
A
A
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Negative Logic Circuitry
• Consider for a moment, the schematic diagram of
an inverting buffer:
If A = VCC, the transistor
saturates, causing the
output to go low.
0
1
A
A
Closed
Switch
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Negative Logic Circuitry
• Consider for a moment, the schematic diagram of
an inverting buffer:
If A = VCC, the transistor
saturates, causing the
output to go low.
1
0
A
A
If A = 0, the transistor
cuts off, causing the
output to go high.
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Open
Switch
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Negative Logic Circuitry
• Inverting Buffer
A
A
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Negative Logic Circuitry
• The inverting buffer becomes a 2-input NOR gate
by allowing two inputs to saturate
the transistor.
A
A+B
B
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Negative Logic Circuitry
Adding an inverting buffer creates an OR gate.
Note: One transistor is
always turned on!
A+B
A
B
This circuit is larger and draws more current
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Negative Logic Circuitry
Advantages of using negative logic:
• Smaller footprint allows more dense circuits.
• Lower power consumption.
• Can be used to generate any logic.
• Better noise immunity in quiescent (inactive)
high state.
• Faster switching speed.
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Example
Convert positive logic to negative logic:
y = AB + CD
A
B
AB
AB+CD
C
D
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CD
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Example
Convert positive logic to negative logic:
y = AB + CD
A
B
AB
AB+CD
C
D
CD
Replace the summing junction (OR gate) with its
negative logic equivalent.
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Example
Convert positive logic to negative logic:
y = AB + CD = AB * CD
A
B
AB
AB*CD = AB + CD
C
D
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CD
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Example
Convert positive logic to negative logic:
y = AB + CD = AB * CD
A
B
AB
AB*CD = AB + CD
C
D
CD
Move “bubbles” back to product junctions
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Example
The negative logic is more efficient because the
circuit is faster & uses all the same logic gates
(all on one IC).
A
B
AB
AB+CD
C
D
A
B
Positive Logic
CD
AB
AB*CD
C
D
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CD
Negative Logic
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Family Characteristics
TTL Voltage and Current Characteristics1
1: These are “Ballpark” values, Actual Specification Sheet should be consulted
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Family Characteristics
CMOS Voltage and Current Characteristics1
1: These are “Ballpark” values, Actual Specification Sheet should be consulted
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Family Characteristics
CMOS Power and Timing Characteristics1
TTL Power and Timing Characteristics1
1: These are “Ballpark” values, Actual Specification Sheet should be consulted
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Operation: TTL Inverter
A
A
• If input A goes high:
– Transistor turns on (saturated), output goes low
• If input A goes low:
– Transistor turns off, output gets pulled high
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Operation: TTL NOR
A+B
A
B
• If either A OR B goes high:
– Transistor turns on (saturated), output goes low
• If both A and B are low:
– Transistor turns off, output gets pulled high
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Operation: TTL OR
A
B
A+B
• If either A OR B goes high:
– Transistor on stage 1 turns on (saturated), turns off
stage 2 transistor, and output goes high
• If both A and B are low:
– Transistor on stage 1 turns off, turns on stage 2
transistor, and output goes low
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Operation: TTL OR
A
B
A+B
NOTE: Stage 1 or stage 2 transistor
is ALWAYS On.
TTL uses a lot of power
• If either A OR B goes high:
– Transistor on stage 1 turns on (saturated), turns off
stage 2 transistor, and output goes high
• If both A and B are low:
– Transistor on stage 1 turns off, turns on stage 2
transistor, and output goes low
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CMOS Primer (NMOS)
Gate
Source
VD
Drain
VD = 0 V
VD
Substrate (Body)
VG
NMOS transistor
VS = 0 V
Closed switch
whenVG = VDD
VG
VS
Open switch
whenVG = 0 V
NMOS transistor
VD
Simplified symbol for an NMOS transistor
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CMOS Primer (PMOS)
Gate
Drain
Source
Substrate (Body)
VDD
VS = VDD
VDD
VDD
VD
VD
VD = VDD
VG
PMOS transistor
Open switch
whenVG = VDD
VG
Closed switch
whenVG = 0 V
PMOS transistor
VS
VD
Simplified symbol for a PMOS transistor
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CMOS Primer
VD
VD = 0 V
VD
VG
NMOS transistor
VS = 0 V
Closed switch
whenVG = VDD
VS = VDD
VDD
Open switch
whenVG = 0 V
VDD
VG
PMOS transistor
VD
VD
Open switch
whenVG = VDD
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VD = VDD
Closed switch
whenVG = 0 V
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Operation: CMOS Inverter
Q1 is an N-type MOS FET (this is a simplified circuit)
and is turned on when a high gate voltage is applied.
Q2 is a P-type MOS FET (this is a simplified circuit)
and is turned on when a low gate voltage is applied.
• If the input goes high:
– Q1 turns on, Q2 turns off, output goes low
• If the input goes low:
– Q1 turns off, Q2 turns on, output goes high
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Operation: CMOS NAND
Q1 & Q3 are N-type MOS FETs and are turned on
when a high gate voltage is applied.
Q2 & Q4 are P-type MOS FETs and are turned on
when a low gate voltage is applied.
• If both inputs go high:
– Q1 & Q3 turn on, Q2 & Q4 turn off, output goes low
• If A goes low:
– Q1 turns off, Q2 turns on, output goes high
• If B goes low:
– Q3 turns off, Q4 turns on, output goes high
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Operation: CMOS NOR
Q1 & Q3 are N-type MOS FETs and are turned on
when a high gate voltage is applied.
Q2 & Q4 are P-type MOS FETs and are turned on
when a low gate voltage is applied.
• If both inputs go low:
– Q2 & Q4 turn on, Q1 & Q3 turn off, output goes high
• If A goes high:
– Q2 turns off, Q3 turns on, output goes low
• If B goes high:
– Q4 turns off, Q1 turns on, output goes low
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Comparison
• In TTL circuits, one or more transistors are
always on, which requires current, and
causes higher power dissipation
• In CMOS circuits, at least one of the
transistors in a pair is off, preventing current
flow, and reduces power significantly (as
compared to TTL)
– Current flows in CMOS circuits only as the
inputs/outputs are changing
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Definitions
VOH-MIN: Minimum Output High Voltage
VOL-MAX: Maximum Output Low Voltage
VDD
VOH-MIN
VOL-MAX
Gnd
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Definitions
VIH-MIN: Minimum Input Low Voltage
VIL-MAX: Maximum Input Low Voltage
VDD
VOH-MIN
VIHMIN
VOL-MAX
VILMAX
Gnd
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Definitions
NMHIGH High-Level Noise Margin
NMLOW Low-Level Noise Margin
VDD
VOH-MIN
VIH-
NMHIGH=VOH-MIN-VIH-MIN
MIN
VILVOL-MAX
MAX
NMLOW=VIL-MAX-VOL-MAX
Gnd
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Definitions
For devices to be compatible VOL-MAX <= VIL-MAX
AND VOH-MIN >= VIH-MIN
VDD
VOH-MIN
VIHMIN
VILVOL-MAX
MAX
Gnd
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Definitions
IIL-MAX Maximum Low-Logic Input Current
IIH-MAX Maximum High-Logic Input Current
IOL-MIN Minimum Low-Logic Output Current
IOH-MIN Minimum High-Logic Output Current
For devices to be compatible IOL-MIN >= IIL-MAX
AND IOH-MIN >= IIH-MAX
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Definitions
FAN-OUT The maximum number of device
inputs that can be driven by a
single device output.
Minimum of:
|I
|
or:
|I
|
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OL-MIN/IIL-MAX
OH-MIN/IIH-MAX
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Why be worried about fanout?
Example: Two TTL Inverters: One driving the other
A
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B
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Why be worried about fanout?
Example: Two TTL Inverters: Gate A driving Gate B
A
B
IOH
+
V ≈ 1.6v
-
Vo = 3.4v
IIH
When Gate A is producing a logic “1” output: VO = 3.4v (typical)
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Why be worried about fanout?
Example: Two TTL Inverters: Gate A driving Gate B
A
IOH
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
IIH
+
V≈ ?v
IIH
-
Vo
IIH
IIH
When Gate A is producing a logic “1” output, and is driving too many “Gate
Bs,” IOH increases, causing the output voltage to drop (because the voltage
across R is increasing). This will cause Vo to drop, possibly below an
identifiable Logic “1” (2v).
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Why be worried about fanout?
Example: Two TTL Inverters: Gate A driving Gate B
A
B
IIL
Vo = 0.4v
+
V ≈ 0.4v
-
IOL
When Gate A is producing a logic “0” output: VO = 0.4v (typical)
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Why be worried about fanout?
Example: Two TTL Inverters: Gate A driving Gate B
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
IIH
IIH
Vo
+
V≈ ?v
-
IIH
IOL
IIH
When Gate A is producing a logic “0” output, and is driving too many “Gate
Bs,” IOL increases, causing the output voltage to increase (because the
voltage across D is increasing). This will cause Vo to rise, possibly above an
identifiable Logic “0” (0.8v).
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Fanout in CMOS
VDD
VDD
VA
Vx
Vf
C
The capacitive load at node A
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Fanout in CMOS
Current flow when input VX changes from 0 V to 5 V
ID
Vf
Vx
VDD
Vx
ID
Vf
Current flow when input VX changes from 5 V to 0 V
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The effect of fan-out on propagation delay
N1
f
x
Vf
To inputs of
x
n other inverters
To inputs of
n other inverters
Cn
Inverter that drives n other inverters
Equivalent circuit for timing purposes
V f for n =1
VDD
V f for n = 4
Gnd
0
Time
Propagation times for different values of n
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Example: Similar Family
How many 7400 series TTL inputs can be driven
by a single 7400 series TTL output?
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Example: Similar Family
How many 7400 series TTL inputs can be driven
by a single 7400 series TTL output?
IIL-MAX = -1.6ma
IOL-MIN = 16.0ma
IIH-MAX = 0.04ma
IOH-MIN/= -0.4ma
|I
|
|I
|
OL-MIN/IIL-MAX
OH-MIN/IIH-MAX
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Example: Similar Family
How many 7400 series TTL inputs can be driven
by a single 7400 series TTL output?
IIL-MAX = -1.6ma
IOL-MIN = 16.0ma
IIH-MAX = 0.04ma
IOH-MIN/= -0.4ma
|I
| = |16.0/-1.6| = 10
|I
| = |-0.4/0.04| = 10
OL-MIN/IIL-MAX
OH-MIN/IIH-MAX
Fan Out = 10
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Example: Mixing Families
How many 74ALS00 series TTL inputs can be
driven by a single 7400 series TTL output?
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Example: Mixing Families
How many 74ALS00 series TTL inputs can be
driven by a single 7400 series TTL output?
IIL-MAX = -0.1ma
IOL-MIN = 16.0ma
IIH-MAX = 0.02ma
IOH-MIN/= -0.4ma
|I
|
|I
|
OL-MIN/IIL-MAX
OH-MIN/IIH-MAX
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Example: Mixing Families
How many 74ALS00 series TTL inputs can be
driven by a single 7400 series TTL output?
IIL-MAX = -0.1ma
IOL-MIN = 16.0ma
IIH-MAX = 0.02ma
IOH-MIN/= -0.4ma
|I
| = |16.0/-0.1| = 160
|I
| = |-0.4/0.02| = 20
OL-MIN/IIL-MAX
OH-MIN/IIH-MAX
Fan Out = 20
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Logic Families
To mix logic families:
1. Logic Levels must be compatible
VOL-MAX <= VIL-MAX
VOH-MIN >= VIH-MIN
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Logic Families
To mix logic families:
1. Logic Levels must be compatible
VOL-MAX <= VIL-MAX
VOH-MIN >= VIH-MIN
2. Current Levels must be compatible
IOL-MIN >= IIL-MAX
IOH-MIN >= IIH-MAX
3. Fanout must not be exceeded.
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Definitions
Propagation Delay: The time delay between an event on a device
input and a corresponding change on its output.
VDD
Vin
50%
50%
Gnd
Propagation delay
Propagation delay
VDD
90%
Vout
Gnd
50%
50%
10%
tr
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90%
10%
tf
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Definitions
Rise Time: TR The time required
for a signal to rise from 10% of its
amplitude to 90% of its amplitude.
VDD
90%
90%
Vout
Gnd
10%
tr
10%
tf
Fall Time, TF The time required
for a signal to fall from 90% of its
amplitude to 10% of its amplitude.
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Common Logic Families
TTL: Transistor-Transistor Logic
Bipolar transistors in common-emitter
configuration.
• Over 30 years old.
• Switches currents.
• Slow: 10ns/dev. typical (100 MHz).
• High power dissipation, typically 10mW/dev.
• Very reliable, commonly used.
• Power supply voltages = +5V, 0V.
• Subfamilies with different current characteristics.
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Common Logic Families
ECL:Emitter Coupled Logic
Bipolar high-speed multi-emitter transistors
eliminate several buffer stages.
• Switches currents.
• Fast: 1ns/dev. typical (1 GHz).
• High power dissipation, typically 40mW/dev.
• Typical power supply voltages = -8V, 0V.
• Approx 1V swing in signal from High to Low.
• Low noise margin = 0.15v
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Common Logic Families
GaAs:Galium-Arsenide Logic
Bipolar high-speed transistors use a GaliumArsenide substrate that is significantly faster
than silicon.
• Switches currents.
• Very Fast: 0.1ns/dev. typical (10 GHz).
• High power dissipation, typically 200mW/dev.
• Power supply voltages = -3.5V, -5.5v, 0V.
• Approx 1V swing in signal from High to Low.
• Literally no noise margin. Requires cooling.
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Common Logic Families
MOS:Metal-Oxide Semiconductor Logic
Uses a metal-oxide gate in a field-effect
transistor as the switch.
• Switches voltages.
• Slow: 100ns/dev. typical (10 MHz).
• Low power dissipation, typically 1mW/dev.
• Power supply voltages = +5, -9v. Varies.
• Approx 2.5V swing in signal from High to Low.
• Large gate-to-drain capacitances limit speed.
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Common Logic Families
CMOS:Complementary MOS Logic.
Uses MOS-FET transistors in a complementary biased totem pole so that one
transistor is always turned off.
• Switches voltages.
• Slow: 50ns/dev. typical (20 MHz).
• Very Low power dissipation < .01mW.
• Excellent for battery-driven applications.
• Complex power supplies
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Common Logic Families
Advances in CMOS Technology
HC/HCT: High Speed/HS TTL Compatible
• Faster than the 4000 level CMOS
• 10ns Propagation Delay (100 MHz)
AHC/AHCT: Advanced HS/AHC TTL Compatible
• Faster than the HC/HCT CMOS
• 3.7 to 5ns Propagation Delay (200 MHz)
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Open Collector / Drain Outputs
First, let’s take a look at a typical TTL Totem-Pole
output:
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Open Collector / Drain Outputs
If the output is a LOW logic level, the Lower
transistor must be saturated
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Open Collector / Drain Outputs
If the output is a HIGH logic level, the upper
transistor must be saturated and the lower transistor
must be off
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Open Collector / Drain Outputs
What happens if these two TTL outputs are tied
together?
Logic LOW on the
left circuit pulls the
entire output low
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Open Collector / Drain Outputs
What happens if these two TTL outputs are tied
together?
What is the current
through the lower
transistor in the first
stage?
16 mA
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Open Collector / Drain Outputs
What happens if we tie a third TTL output to the
other two?
What is the current
through the lower
transistor in the
first stage?
32 mA
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Open Collector / Drain Outputs
If we add another, the first transistor will have to
sink 48 mA
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Open Collector / Drain Outputs
A LOW on any single gate
output pulls the entire
circuit output LOW.
(Wire - NOR)
Excessive currents can
permanently damage the
circuits
What can we do?
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Solutions:
1. Use an AND gate to combine the outputs:
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Solutions:
2. Use Open-Collector
circuits.
Such circuits are specially
designed to drive a single line
with several device outputs.
Provides capability to switch
currents up to 16mA (74XX)
with flexible Voltage supply
values.
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Solutions:
2. Use Open-Collector circuits.
Useful for switching
• Relays
• Lamps
• DC Motors
• Stepping Motors
• Etc.
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Open Collector / Drain Outputs
• Any gate can pull the output line low.
• Quiescent HIGH, Active LOW
• Negative Logic!
• RP limits current allowing any +V.
VMAX = VceBREAKDOWN
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Open Collector / Drain Outputs
To determine RP:
If RP is too small, currents through the opencollector circuits will be too large, and the
circuit will be damaged.
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Open Collector / Drain Outputs
To determine RP:
If RP is too large, insufficient current will be
available to switch the junction to a low level.
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Open Collector / Drain Outputs
To determine RP:
The minimum RP current state exists when all
O.C. circuits are in the high state.
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Open Collector / Drain Outputs
To determine RP:
The minimum RP current state exists when all
O.C. circuits are in the high state.
N1 = No. of O.C. Circuits
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Open Collector / Drain Outputs
To determine RP:
The minimum RP current state exists when all
O.C. circuits are in the high state.
N1 = No. of O.C. Circuits
N2 = No. of driven circuits.
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Open Collector / Drain Outputs
To determine RP:
The minimum RP current state exists when all
O.C. circuits are in the high state.
IRP=N1IOH+N2IIH
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Open Collector / Drain Outputs
RPMAX
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VCC − VIHMIN
=
N 1 IOH + N 2 IIH
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Open Collector / Drain Outputs
RPMAX
VCC − VIHMIN
=
N 1 IOH + N 2 IIH
RPMAX
5.0V − 2.7V
=
4(250 µA) + 2(50 µA)
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Open Collector / Drain Outputs
RPMAX
RPMAX
RPMAX
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VCC − VIHMIN
=
N 1 IOH + N 2 IIH
5.0V − 2.7V
=
4(250 µA) + 2(50 µA)
2.3V
=
= 2.09 KΩ
1100 µA
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Open Collector / Drain Outputs
The maximum RP current state is IOL in any
single O.C. output. The O.C. output must sink
both IRP and N2IIL.
IOL = IRP + N2IIL
I OL
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Open Collector / Drain Outputs
So, the current through RP is shown by the
formula below
IRP=IOL - N2IIL
I OL
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Open Collector / Drain Outputs
RPMIN
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VCC − VILMAX
=
IOL +- N 2 IIL
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Open Collector / Drain Outputs
RPMIN
VCC − VILMAX
=
IOL +- N 2 IIL
RPMIN
5.0V − 0.5V
=
20 mA +- 22((2.0mA)
− 2.0mA )
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Open Collector / Drain Outputs
RPMIN
VCC − VILMAX
=
IOL +- N 2 IIL
RPMIN
5.0V − 0.5V
=
20 mA +- 22((2.0mA)
− 2.0mA )
4.5V
RPMIN =
= 281.25Ω
16mA
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Open Collector / Drain Outputs
RPMAX + RPMIN 2090 + 281.25
RP =
=
≈ 1200Ω
2
2
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Open Collector / Drain Outputs
VCC − VIHMIN
RPMAX =
N 1 IOH + N 2 IIH
VCC − VILMAX
RPMIN =
IOL +- N 2 IIL
RPMAX + RPMIN
RP =
2
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Open Collector / Drain Outputs
Determine RP for the following circuit:
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Open Collector / Drain Outputs
RPMAX
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VCC − VIHMIN
=
N 1 IOH + N 2 IIH
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Open Collector / Drain Outputs
RPMAX
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5.0V − 2.7V
=
2( 250 µA) + 3(50 µA)
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Open Collector / Drain Outputs
RPMAX
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2.3V
=
= 3.538 KΩ
650 µA
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Open Collector / Drain Outputs
RPMIN
VCC − VILMAX
=
IOL -+ N 2 IIL
RPMAX = 3538
.
KΩ
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Open Collector / Drain Outputs
RPMIN
5.0V − 0.5V
=
(−2.0mA)
20mA + 33(
2.0mA)
RPMAX = 3538
.
KΩ
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Open Collector / Drain Outputs
RPMIN
4.5V
=
= 321.4Ω
14mA
RPMAX = 3538
.
KΩ
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Open Collector / Drain Outputs
RPMAX + RPMIN
RP =
2
RPMIN = 321.4Ω
.
KΩ
RPMAX = 3538
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Open Collector / Drain Outputs
3538 + 321
RP =
≈ 2000Ω
2
RPMIN = 321.4Ω
.
RPMAX = 3538
KΩ
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Summary
• In this topic we,
– Reviewed several basic logic gates
– Reviewed positive and negative logic
– Became familiar with several static and dynamic
characteristics of several logic families
including:
• Fanout
• Noise margins
• Open collector/drain resistance calculations
8/18/2010
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