Download A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-µm CMOS

A 26 GHz Phase-Locked Loop Frequency
Multiplier in 0.18-µm CMOS
by
John Patten Carr
A thesis submitted to the
Department of Electrical and Computer Engineering
in conformity with the requirements for
the degree of Doctor of Philosophy
Queen’s University
Kingston, Ontario, Canada
April 2009
c John Patten Carr, 2009
Copyright Abstract
This thesis presents the analysis, design and characterization of an integrated highfrequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is
novel in its use of a low multiplication factor of 4 and a fully differential topology for
rejection of common mode interference signals. The PLL is composed of a voltage
controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first
divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second
divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has
been fabricated using a standard CMOS 0.18-µm process based on its relatively low
cost and ready availability. The PLL frequency multiplier generates an output signal
at 26 GHz and is the highest operational frequency PLL in the technology node
reported to date.
Time domain phase plane analysis is used for prediction of PLL locking range
based on initial conditions of phase and frequency offsets. Tracking range of the PLL
is limited by the inherent narrow locking range of the ILFD, and is confirmed via
experimental results.
The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the
VCO control lines. A comparison of the common- and differential-mode modulation
i
indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB
is possible for carrier offset frequencies of less than 1 MHz.
Closed-loop frequency domain transfer functions are used for prediction of the
PLL phase noise response, with the PLL being dominated by the reference and VCO
phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental
verifications display good agreement and confirm the usefulness of the techniques for
PLL performance prediction.
The PLL clock multiplier has an operational output frequency of 26.204 to 26.796
GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1
MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit
(VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and
4.3 V DC rails.
ii
Acknowledgments
The author would like to acknowledge and thank the many people and organizations
who have made this research possible.
Funding at the national and provincial levels has been provided by the National
Science and Engineering Research Council (NSERC) Post Graduate Scholarship (Doctoral) (PGS-D) and the Ontario Graduate Scholarship in Science and Technology
(OGSST). Additional funding was awarded by the Sumner Foundation for the Walter P. Sumner Memorial Fellowship and the Association of Professional Engineers
and Geoscientists of New Brunswick for the APEGNB Advanced Studies Scholarship. The financial support of both levels of government and of the private sector is
greatly appreciated and played a large part in the decision to undertake the research.
Integrated circuit fabrication support was supplied by CMC Microsystems. Testing equipment was supplied under a grant from a CFI New Opportunities Grant with
matching funds through the Ontario Innovation Trust (OIT) and Agilent and Anritsu. Additional test equipment was made available through the Advanced Photonics
Systems Lab of the National Microelectronics and Photonics Testing Collaboratory
(NMPTC) and the Lightwave Systems Research Laboratory, both under Dr. John
Cartledge, and from CMC Microsystems. A special thanks is to be extended to the
iii
Advanced RF Systems Lab of the NMPTC for the remote use of their testing facilities and to James Dietrich for ensuring a successful testing exercise. Patricia Greig
of the Advanced Photonics Systems Lab was always supportive of any particular test
equipment requests, which helped the testing greatly.
Dr. Brian Frank is to be commended for his steady guidance, encouragement
and patience over the course of the research. His technical knowledge and dedication
to quality educational instruction at all levels is exemplary. Thanks are also to be
extended to Dr. David Krause for fruitful discussions on PLL simulation techniques.
The graduate students of the Very High Speed Silicon Circuits Group have always
been willing to brainstorm a solution to circuit or analysis challenges; their inputs
are always welcome and enlightening.
To my immediate and extended family, I cannot begin to put into words my
appreciation for your unflagging support throughout the degree - thank you all. To
James and Jessica, I will always be there to support and encourage you as you have
done for me. Finally, to my loving wife Karen, who has been and is always beside me
through the good and the trying times: I love you very much, and truly appreciate
all your efforts to make the degree, our marriage, and our lives rich and meaningful.
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Table of Contents
Abstract
i
Acknowledgments
iii
Table of Contents
v
List of Tables
viii
List of Figures
ix
Nomenclature
xiv
Chapter 1:
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Literature Review
. . . . . . . . . . . . . . . . . . . . . .
5
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
2.2
Selected Review of PLL Performance . . . . . . . . . . . . . . . . . .
6
2.3
Review of PLL Subcircuits . . . . . . . . . . . . . . . . . . . . . . . .
13
Chapter 2:
v
Chapter 3:
Phase-Locked Loop Frequency Synthesis . . . . . . . . .
34
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.2
PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.3
Phase Noise Performance of the PLL . . . . . . . . . . . . . . . . . .
49
3.4
Locking Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
3.5
Tracking Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
3.6
Selection of PLL Loop Constants . . . . . . . . . . . . . . . . . . . .
54
3.7
PLL Design Considerations
61
. . . . . . . . . . . . . . . . . . . . . . .
Chapter 4:
Component Description
. . . . . . . . . . . . . . . . . . .
80
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
4.2
Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . .
80
4.3
Frequency Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
4.4
Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
Chapter 5:
Phase Lock Loop - Top Level . . . . . . . . . . . . . . . .
98
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
5.2
Top Level Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
5.3
Top Level Performance Evaluation . . . . . . . . . . . . . . . . . . . 112
Chapter 6:
Results
6.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
vi
6.2
Test Equipment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3
Component Performance Verification . . . . . . . . . . . . . . . . . . 139
6.4
Integrated PLL measurements . . . . . . . . . . . . . . . . . . . . . . 151
6.5
Analytical vs. Measured Phase Noise . . . . . . . . . . . . . . . . . . 166
Chapter 7:
Conclusion and Future Work . . . . . . . . . . . . . . . . 172
7.1
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.2
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Bibliography
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Appendix A:
Simulation of High Frequency PLLs . . . . . . . . . . . 192
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
A.2 Cadence Spectre
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
A.3 Agilent EESof Advanced Design System . . . . . . . . . . . . . . . . 195
vii
List of Tables
2.1
Summary, Reviewed PLL Systems . . . . . . . . . . . . . . . . . . . .
2.2
Phase Noise Comparison of Crystal and Dielectric Resonator Oscilla-
13
tors (DROs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
3.1
Performance Comparison, Multiplier and Sequential Phase Detectors
79
4.1
ILFD Locking Bandwidth: Tail- vs. Direct-Injection . . . . . . . . . .
87
4.2
Input-Referenced Locking Bandwidth vs. Static Phase Offset . . . . .
96
5.1
PLL Sample Ports Coupling Factor . . . . . . . . . . . . . . . . . . . 109
6.1
Major Test Equipment - PLL Performance Verification . . . . . . . . 137
6.2
Test Equipment - PLL Power-up Sequence. DC pins and referenced
power supplies are shown in Figure 6.1. . . . . . . . . . . . . . . . . . 138
6.3
PLL - Performance comparison . . . . . . . . . . . . . . . . . . . . . 153
6.4
Input-Referenced Locking Bandwidth Results . . . . . . . . . . . . . 154
6.5
Input-Referenced Tracking Bandwidth Results . . . . . . . . . . . . . 155
6.6
Common Mode Rejection Ratio (CMRR) vs. Injected Frequency . . . 162
6.7
Analytical Calculation of Phase Noise - Loop Constants . . . . . . . . 169
viii
List of Figures
2.1
Block Diagram, 2.4 GHz Frequency Synthesizer . . . . . . . . . . . .
6
2.2
2.5 GHz phase detector response and implementation . . . . . . . . .
8
2.3
Stacked 24 GHz VCO and divider . . . . . . . . . . . . . . . . . . . .
10
2.4
Circuit diagram, 75 GHz VCO and first-stage divider . . . . . . . . .
12
2.5
Circuit diagram, complementary differential LC-VCO . . . . . . . . .
14
2.6
Circuit diagram, 10 GHz differentially-tuned LC-VCO . . . . . . . . .
16
2.7
Circuit diagram, 3.8-5.7 GHz differentially-tuned LC-VCO . . . . . .
17
2.8
Schematic diagram, 27 GHz MSFF . . . . . . . . . . . . . . . . . . .
21
2.9
Schematic diagram, high speed latch . . . . . . . . . . . . . . . . . .
22
2.10 Schematic diagram, 50 GHz injection-locked frequency divider . . . .
25
2.11 D flip-flop phase/frequency detector block diagram and response . . .
26
3.1
Block Diagram, Feedback System . . . . . . . . . . . . . . . . . . . .
35
3.2
Block Diagram, Frequency-Multiplying PLL (a) Time Domain (b) Linear Frequency Domain . . . . . . . . . . . . . . . . . . . . . . . . . .
37
3.3
First Order LPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3.4
Modified Block Diagram, Frequency-Multiplying PLL . . . . . . . . .
42
3.5
PLL Linear Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
3.6
Phase Plane Trajectories: No Phase Lock and Phase Lock . . . . . .
58
ix
3.7
PLL Closed Loop Transfer Functions - Type I, 2nd Order . . . . . . .
3.8
Varactor circuits (a) Individual varactor element, (b) Singly-tuned subassembly, (c) Differentially-tuned assembly . . . . . . . . . . . . . . .
3.9
60
63
Varactor circuits with injected common mode noise (a) Individual varactor element, (b) Singly-tuned sub-assembly . . . . . . . . . . . . . .
64
3.10 Differentially-tuned varactor with injected common mode noise . . . .
65
3.11 Typical oscillator phase noise versus offset frequency . . . . . . . . .
67
3.12 Two-Bit Digital Counter (a) Schematic, (b) Timing Diagram . . . . .
72
3.13 Injection-Locked Frequency Divider: Tail Injection . . . . . . . . . . .
75
3.14 CMOS level-based D flip-flop: logic circuit diagram . . . . . . . . . .
76
3.15 Master-Slave Flip-Flop Frequency Divider Block Diagram . . . . . . .
76
3.16 Schematic diagram of the D Flip-Flop . . . . . . . . . . . . . . . . . .
77
4.1
Circuit Schematic, negative gm VCO . . . . . . . . . . . . . . . . . .
81
4.2
Layout, negative gm VCO . . . . . . . . . . . . . . . . . . . . . . . .
82
4.3
AMOS varactor sub-assemblies: (a) Gate-tuned, (b) Diffusion-tuned .
84
4.4
AMOS differential varactor assembly . . . . . . . . . . . . . . . . . .
85
4.5
Injection-Locked Frequency Divider: Direct Injection . . . . . . . . .
86
4.6
Layout, injection-locked frequency divider . . . . . . . . . . . . . . .
88
4.7
Schematic diagram of the Master-Slave Flip-Flop Divider . . . . . . .
89
4.8
Layout, master-slave flip-flop divider . . . . . . . . . . . . . . . . . .
90
4.9
Circuit schematic - Gilbert cell phase detector . . . . . . . . . . . . .
92
4.10 Layout, Gilbert cell phase detector . . . . . . . . . . . . . . . . . . .
93
4.11 Phase Detector Output versus LO-RF Phase Difference for Ideal and
Real Multiplier PDs
. . . . . . . . . . . . . . . . . . . . . . . . . . .
x
94
5.1
PLL Integrated Circuit (a) Circuit microphotograph, (b) Block diagram101
5.2
VCO to ILFD Circuit Schematic . . . . . . . . . . . . . . . . . . . . . 102
5.3
ILFD to MSFF Circuit Schematic . . . . . . . . . . . . . . . . . . . . 104
5.4
Coupling Factor vs. Frequency, ILFD Buffer Output to Gate of ILFD sample
Common Drain Amplifier
. . . . . . . . . . . . . . . . . . . . . . . . 105
5.5
MSFF Divider to Phase Detector Circuit Schematic . . . . . . . . . . 106
5.6
Coupling Factor vs. Frequency, MSFF Divider Output to Gate of
MSFF sample Common Drain Amplifier . . . . . . . . . . . . . . . . 107
5.7
Test Coupler Construction . . . . . . . . . . . . . . . . . . . . . . . . 108
5.8
Lowpass Filters and their effect on open loop gain. (a) First Order
One Pole, (b) First Order One Pole/One Zero, (c) Second Order Two
Poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.9
Simulated VCO Frequency vs. Differential Control Voltage . . . . . . 114
5.10 Simulated Phase Detector Output vs. Input Phase Difference . . . . . 115
5.11 PLL Input Frequency Step Response vs. Time . . . . . . . . . . . . . 120
5.12 VCO Tank, ILFD Tank, and MSFF Divider Output Voltages vs. Time,
PLL Open Loop HB Simulation . . . . . . . . . . . . . . . . . . . . . 122
5.13 VCO Control Voltages vs. Time, PLL Open Loop HB Simulation . . 123
5.14 PLL Block Diagram with Noise Sources . . . . . . . . . . . . . . . . . 127
5.15 MOS noise model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.1
Test Setup - PLL Phase Noise, Tracking and Locking Bandwidth . . . 139
6.2
Integrated PLL - VCO Tuning Range vs. Differential Control Voltage
6.3
Test Setup, VCO Free-running Phase Noise . . . . . . . . . . . . . . . 142
xi
140
6.4
VCO Phase Noise (a) Injection-Locked VCO, (b) Injected Reference
Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.5
VCO Free-Running Phase Noise (extracted using Eq. 6.4) . . . . . . 145
6.6
ILFD Tuning Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.7
Test Setup, Gilbert Cell Phase Detector . . . . . . . . . . . . . . . . 149
6.8
Gilbert Cell PD output versus RF-LO phase difference, PD current =
2.63 mA, Freq. = 6.5 GHz . . . . . . . . . . . . . . . . . . . . . . . . 150
6.9
Static Phase Shift vs. PD Total Current: Simulated, Measured, Calculated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.10 PLL Output Signal, Frequency Domain
. . . . . . . . . . . . . . . . 152
6.11 Interfering Signal Injection Generator (a) Differential Mode, (b) Common Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.12 DM/CM Signal Injection at VCO Control Lines, Frequency = 10 kHz
(a) PLL Unmodulated O/P Spectrum (freq=26.376 GHz), (b) PLL
O/P Spectrum with Injected DM/CM signals . . . . . . . . . . . . . 159
6.13 Modulation Indices βCM and βDM for CM/DM Signal Injection at VCO
Control Lines, Frequency = 10 kHz . . . . . . . . . . . . . . . . . . . 160
6.14 Measured Phase Noise for Differential Mode/Common Mode Signal
Injection, Frequency = 10 kHz (a) PLL Output, DM-injected Signal,
(b) PLL Output, CM-injected Signal . . . . . . . . . . . . . . . . . . 163
6.15 Injected Broadband Noise (a) Generator Noise at Generator Output
and Device Injection Test Points (RBW=4.7 kHz), (b) Generator Noise
at Generator Output (RBW=30 Hz) . . . . . . . . . . . . . . . . . . 164
xii
6.16 Unmodulated Carrier versus CM/DM-Injected Broadband Noise Spectra, fosc =26.524 GHz (RBW=4.7 kHz) . . . . . . . . . . . . . . . . . 165
6.17 PLL Phase Noise for Broadband CM/DM-Injected Noise, Noise BW=100
kHz, fosc =26.524 GHz (a)Unmodulated Output Carrier, (b)Output
Carrier with CM/DM-injected Noise . . . . . . . . . . . . . . . . . . 167
6.18 Phase Detector Simulated IF Output Voltage vs. Input Phase Difference with Least Squares Best Fit Line
. . . . . . . . . . . . . . . . . 168
6.19 PLL Phase Noise: Contributions from Reference and VCO (top graph),
Analytical versus Measured Performance (bottom graph) and Identification of Dominant Contributions vs. Offset Frequency . . . . . . . . 171
7.1
Calculated PLL Phase Noise, Lead-lag Loop Filter . . . . . . . . . . . 178
A.1 Schematic-dependent S-parameter blocks for time domain (a) Successful simulation (b) Unsuccessful simulation . . . . . . . . . . . . . . . 194
A.2 DC bias feed for differential VCO . . . . . . . . . . . . . . . . . . . . 194
A.3 Differential Ground Reference for VCO . . . . . . . . . . . . . . . . . 195
xiii
Nomenclature
Latin Symbols
A
Magnitude of PLL Output Signal [V]
ACM
Operational Amplifier Common Mode Gain [V/V]
ADM
Operational Amplifier Differential Gain [V/V]
Agate
Transistor Gate Area [m2 ]
Aoverlap
Gate-Drain Overlap Area [m2 ]
A(s)
Forward Loop Gain [rad/rad]
a
Coefficient for Simultaneous Equation Solution
a0 , a1 , . . .
Coefficients of Lowpass Filter Transfer Function
B(s)
Feedback Gain [rad/rad]
BWlock
Locking Bandwidth [rad/sec or Hz]
BWtrack
Tracking Bandwidth [rad/sec or Hz]
b
Coefficient for Simultaneous Equation Solution
b 0 , b1 , . . .
Coefficients of Lowpass Filter Transfer Function
CL
Load Capacitance [F]
Cds
Drain to Source Capacitance [F]
Cgd
Gate to Drain Capacitance [F]
xiv
Cgs
Gate to Source Capacitance [F]
Cox
Gate Oxide Capacitance per Unit Area [f/m2 ]
Cpar
Parasitic Capacitance [F]
Ctot
Total Tank Capacitance [F]
Cvar
Variable Capacitance [F]
C0
Varactor Zero Bias Capacitance [F]
C0,1
Differential Varactor Zero Bias Capacitance [F]
C0,2
Differential Varactor Zero Bias Capacitance [F]
C1−
−
Differentially-Tuned Varactor Capacitance ( V+
ctrl to vo ) [F]
C1+
+
Differentially-Tuned Varactor Capacitance ( V+
ctrl to vo ) [F]
C−
2
−
Differentially-Tuned Varactor Capacitance ( V−
ctrl to vo ) [F]
C+
2
+
Differentially-Tuned Varactor Capacitance ( V−
ctrl to vo ) [F]
C−
Varactor Capacitance (Control Node to Negative Node) [F]
C+
Varactor Capacitance (Control Node to Positive Node) [F]
c
Coefficient for Simultaneous Equation Solution
c 0 , c1 , . . . , c n
Fourier Series Coefficients
d
Coefficient for Simultaneous Equation Solution
E(s)
Filtered Error Signal (Frequency Domain) [V]
Esat
Electric Field Where Carrier Velocity = 50% of Low-Field Velocity [V/m]
Estored
Energy Stored in an LC Tank [J]
e(t)
Filtered Error Signal (Time Domain) [V]
e0 (t)
Filter Zero-input Response (Time Domain) [V/V]
F
Excess Noise Number [57]
F(s)
Filter Transfer Function (Frequency Domain) [rad/rad]
xv
F(x,y)
Function (with G(x,y)) for Simultaneous Equation Solution
F1 (x,y)
Function for Simultaneous Equation Solution
f
Frequency [Hz]
fV CO
VCO Frequency [Hz]
∆f
Resolution Bandwidth for Power Measurement [Hz]
∆flock
Locking Frequency [Hz]
∆ftrack
Tracking Frequency [Hz]
fi
Current Waveform Frequency [Hz]
fi,LO
Gilbert Cell LO Switching Stage Current Waveform Frequency [Hz]
fi,RF
Gilbert Cell RF Transconductance Stage Current Waveform Frequency [Hz]
fmax
Unity Power Gain Frequency [Hz]
fref,lock
PLL Locked Reference Frequency [Hz]
fsample,out
Output Phase Sampling Frequency [Hz]
ft
Short Circuit Unity Gain Frequency [Hz]
f (t)
Filter Impulse Response [V/V]
G(s)
Open Loop Transfer Function [rad/rad]
G(x,y)
Function (with F(x,y)) for Simultaneous Equation Solution
G1 (x,y)
Function for Simultaneous Equation Solution
gm
Transconductance [A/V]
gD0
Transistor Drain-Source Conductance at VDS = 0V [A/V]
gD0,T
Tail Transistor Drain-Source Conductance at VDS = 0V [A/V]
H(s)|closed,I/P
Closed Loop Transfer Function, Input to Output [rad/rad]
H(s)|closed,V CO Closed Loop Transfer Function, VCO to Output [rad/rad]
hφ (t, τ )
Unit Impulse Response for Excess Phase [1/Coulomb]
xvi
IB
Tail Bias Current [A]
IDS
Drain-Source or Channel Current [A]
Ic
Charge pump current [A]
Im
Current of mth harmonic, ISF Fourier Series Expansion [A]
In
Current of nth harmonic, ISF Fourier Series Expansion [A]
ind
Drain Noise Current [A]
i2nd
Mean Square Drain Current Noise Spectral Density [A2 /Hz]
i2nd,tot
Total Mean Square Drain Current Noise Spectral Density [A2 /Hz]
ing
Gate Noise Current [A]
i2 n,1/f
Mean Square Current Noise Spectral Density in 1/f Region [A2 /Hz]
in (t)
Injected Noise Current [A]
Jn (β)
Bessel Function of the First Kind of Order n, Argument β
iv,ng
Current Due to Gate Noise Voltage [A]
i2v,ng
Mean Square Current Noise Spectral Density due to vng [A2 /Hz]
K
MOSFET Device-Specific Constant for 1/f Noise
Kd
Phase Detector Gain Constant [V/rad]
K0
VCO Gain Constant [rad/s/V]
k
Boltzmann’s Constant [J/K]
kv
Varactor Sensitivity [F/V]
kv1
Varactor 1 Sensitivity [F/V]
kv2
Varactor 2 Sensitivity [F/V]
L
Inductance [H]
Lg
CMOS Gate Length [m]
Loverlap
Gate-Drain Overlap Length [m]
xvii
Lpeak
Peaking Inductor [H]
LCrystal (∆ω)
Crystal Single-Sided Phase Noise PSD at ∆ω [dBc/Hz]
LV CO,f ree (∆ω) Free-Running VCO Single-Sided Phase Noise PSD at ∆ω [dBc/Hz]
LV CO,lock (∆ω)
Injection-locked VCO Single-Sided Phase Noise PSD at ∆ω [dBc/Hz]
Lref (∆ω)
Reference Single-Sided Phase Noise PSD at ∆ω [dBc/Hz]
Lout (∆ω)
Output Single-Sided Phase Noise PSD at ∆ω [dBc/Hz]
L(X)
Single-Sided Phase Noise PSD at Offset Frequency X [dBc/Hz]
L{}
Laplace Transform
N
Division Factor
PILF D,Buf
Power at ILFD Buffer Output [W]
PSBC (∆ω)
Power in Sidebands Relative to Carrier [dBc/Hz]
PV CO,tank
Power at VCO Tank [W]
Pmod,n
Angle-Modulated nth Sideband Power [W]
Ps
Average Power Dissipated in Resistive Part of LC Tank [W]
Punmod
Unmodulated Carrier Power [W]
Q
Quality Factor
Qi
Inversion Layer Charge [Coulombs]
QL
Quality Factor, Loaded LC Tank
qmax
Maximum Charge Displacement Across LC Tank Capacitor [Coulombs]
<[]
Real Part of Complex Representation
RL
Load Resistance [Ω]
Rd
Drain Resistance [Ω]
r
Polar Coordinate Magnitude
rg
Gate Series Resistor [Ω]
xviii
r1 , r2
Roots of Characteristic Equation
SV (s)
Noise Spectral Density (Voltage-Generated) [V 2 /Hz]
SV,F (s)
Loop Filter Noise Spectral Density [V 2 /Hz]
SV,P D (s)
Phase Detector Noise Spectral Density [V 2 /Hz]
Sθ (s)
Noise Spectral Density (Phase-Generated) [rad2 /Hz]
Sθ,DivN (s)
Divider Noise Spectral Density [rad2 /Hz]
Sθ,F (s)
Loop Filter Phase Noise Spectral Density [rad2 /Hz]
Sθ,V CO (s)
VCO Noise Spectral Density [rad2 /Hz]
Sθ,in (s)
Input Noise Spectral Density [rad2 /Hz]
Sθ,out (s)
Output Noise Spectral Density [rad2 /Hz]
Sφ (s)
Double-sided Phase Noise PSD (Complex) [dBc/Hz]
Sφ (ω)
Double-sided Phase Noise PSD [dBc/Hz]
s
Complex Radian Frequency (= iω) [rad]
T
Temperature [K]
TD
Data Period [s]
t
Time [s]
tox
Oxide Thickness [m]
u(t − τ )
Unit Step Applied at Time Offset τ
VDD
Voltage Supply Line [V]
VCM
VCO Input Common Mode Voltage [V]
VDM
VCO Input Differential Mode Voltage [V]
VDS
DC Drain-Source Voltage [V]
VF (s)
Loop Filter Noise Voltage [V]
VGS
DC Gate-Source Voltage [V]
xix
VIF
Intermediate Frequency Voltage [V]
VP D (s)
Phase Detector Noise Voltage [V]
VT
Transistor Threshold Voltage [V]
Vctrl
Varactor control voltage [V]
−
Vctrl
Differential Varactor Negative Control Voltage [V]
+
Vctrl
Differential Varactor Positive Control Voltage [V]
Vctrldif f
Differential Varactor Differential Control Voltage [V]
Vd
Drain Voltage [V]
Vdif f
Differential Voltage [V]
Vg
Gate Voltage [V]
Vgctrl
Control Voltage for Adjustable Gain Phase Detector [39]
Vin (t)
PLL Input Reference Signal [V]
Vout (t)
PLL Output Signal [V]
Vtail
Tail Transistor Voltage [V]
Vtank
LC Tank Voltage [V]
vICM
Operational Amplifier Input Common Mode Voltage [V]
vIDM
Operational Amplifier Input Differential Mode Voltage [V]
vncm
Common Mode Noise Voltage [V]
vng
Gate Noise Voltage [V]
2
vng
Mean Square Gate Voltage Noise Spectral Density [V 2 /Hz]
vo
Varactor Reference Voltage [V]
vo,opamp
Operational Amplifier Output Voltage [V]
vo−
Varactor Reference Voltage (Negative Node) [V]
vo+
Varactor Reference Voltage (Positive Node) [V]
xx
Wg
Gate Width [m]
X(s)
Phase Detector Output Error Signal (Frequency Domain) (V)
x(t)
Phase Detector Output Error Signal (Time Domain) (V)
Y (ω)
General Function (Frequency Domain)
y(t)
General Function (Time Domain)
Greek Symbols
α
Body Effect Coefficient Factor
β
Modulation Index [rad]
βCM
Common Mode Modulation Index [rad]
βDM
Differential Mode Modulation Index [rad]
Γ(ω0 τ )
Impulse Sensitivity Function
Γrms
Root Mean Square of Impulse Sensitivity Function
γ
Transistor Noise Coefficient
γT
MSFF Divider Tail Transistor Noise Coefficient
∆ω
Offset Angular Frequency [rad/s]
∆ωstep
Step Change in Frequency [rad/s]
∆ωLock
Maximum Locking Frequency [rad/s]
∆ωtrack
Tracking Range [rad/s]
∆ωV CO,lock
VCO Injection Locking Bandwidth [rad/s]
∆ω1/f 3
Corner Frequency, 1/f 3 and 1/f 2 Regions [rad/s]
δ
Gate Noise Coefficient, Long Channel Devices
δφ2V CO,lock (∆ω) Locked VCO Phase Noise Spectral Density [rad2 /Hz]
δφ2V CO,f ree (∆ω) Free-Running VCO Phase Noise Spectral Density [rad2 /Hz]
xxi
δφ2inj (∆ω)
Injected Locking Signal Phase Noise Spectral Density [rad2 /Hz]
0
Permeability of Free Space = 8.854 × 10−12 [F/m]
ox
Permeability of Silicon Oxide [F/m]
r,ox
ζ
Relative Permeability of Silicon Oxide
√
PLL Damping Factor [1/ s]
θ
Polar Coordinate Angle [rad]
θDivN (s)
Divider Phase Noise [rad]
θV CO (s)
VCO Phase Noise [rad]
θin (s)
Reference Input Phase (Frequency Domain) [rad]
θin (t)
Reference Input Phase (Time Domain) [rad]
θn
Phase of nth harmonic, ISF Fourier Series Expansion
θo (t)
Output Total Excess Phase (Time Domain) [rad]
θout (s)
Total Output Phase (Frequency Domain) [rad]
θout (t)
Total Output Phase (Time Domain) [rad]
θ0 (s)
Modified Total Output Phase (Frequency Domain) [rad]
θ0 (t)
Modified Total Output Phase (Time Domain) [rad]
θref (t)
Reference Total Excess Phase (Time Domain) [rad]
θref (s)
Reference Total Excess Phase (Frequency Domain) [rad]
θV CO (s)
VCO Total Excess Phase (Frequency Domain) [rad]
θ1 (t)
Reference Relative Total Phase (Time Domain) [rad]
θ2 (t)
Modified VCO Relative Total Phase (Time Domain) [rad]
λ
Wavelength [m]
µ
Effective Electron Mobility [cm2 /(V · s)]
µm
micrometer [1 × 10−6 m]
xxii
τ
Time Offset [s]
τtr
Intrinsic Channel Transit Time [s]
τtr,LO
LO Switching Stage Intrinsic Channel Transit Time [s]
τtr,RF
RF Transconductance Stage Intrinsic Channel Transit Time [s]
τ1 , τ2 , . . .
Time Constants for Closed Loop Transfer Function Poles [s]
φ
Phase Error [rad]
φ̇
Relative Frequency Error [rad/s]
φ0
Minimum Phase [rad]
φ(t)
Phase Error [rad]
Φd
PD Phase Difference Corresponding to a Dead Zone [rad]
Φdetune
Phase Difference, Free-Running VCO and Injected Locking Signal [rad]
Φe
Phase Difference in Phase Detector [rad]
ΦO
Static Phase Offset [rad]
ΦO,Cp
Static Phase Offset due to Parasitic Capacitance [rad]
ΦO,tr
Static Phase Offset due to Intrinsic Channel Transit Time [rad]
ω
Angular Frequency [rad/s]
ωL
3-dB Bandwidth of Loop Filter [rad/s]
ωN
Free-running Angular Frequency [rad/s]
ωin
ωn
Input Angular Frequency [rad/s]
√
PLL Natural Frequency [1/ s]
ωm
Interfering Signal Frequency [rad/s]
ωo
Output Angular Frequency [rad/s]
ωref
Input Reference Angular Frequency [rad/s]
ωt
Short Circuit Unity Gain Radian Frequency [rad/s]
xxiii
ω0
VCO Free-Running Angular Frequency [rad/s]
ω1/f
Device Noise 1/f Corner Frequency [rad/s]
Acronyms
AC
Alternating Current
ADS
Advanced Design System
AMOS
Accumulation-mode Metal Oxide Semiconductor
APW
Adjustable Pulse Width
BiCMOS
Bipolar Complementary Metal Oxide Semiconductor
CD
Common Drain
CDR
Clock and Data Recovery
CLK
Clock
CLK
Clock (Complementary)
CLK+, CLK-
Differential Clock Signals
CM
Common Mode
CML
Current Mode Logic
CMOS
Complimentary Metal-Oxide Semiconductor
CMRR
Common Mode Rejection Ratio
CP
Charge Pump
CPW
Co-Planar Waveguide
CS
Common Source
CW
Continuous Wave
DC
Direct Current
D+, D-
Flip-Flop Differential Input Data Signals
xxiv
D-FF
D Flip-Flop
DM
Differential Mode
DRO
Dielectric Resonator Oscillator
EM
Electro-Magnetic
EMI
Electromagnetic Interference
FD
Frequency Detector
FF
Fast-Fast CMOS Process Corner
GSG
Ground-Signal-Ground
HB
Harmonic Balance
HBAHB
Harmonic Balance Assisted Harmonic Balance
HBT
Heterojunction Bipolar Transistor
IC
Integrated Circuit
IF
Intermediate Frequency
IEEE
Institute of Electrical and Electronics Engineers
ILFD
Injection Locked Frequency Divider
ILFD sample
ILFD Test Port
ISF
Impulse Sensitivity Function
LAN
Local Area Network
LC
Inductor-Capacitor
LO
Local Oscillator
LPF
Low Pass Filter
M(name)
Transistor Identification
MIM
Metal-Insulator-Metal
MIMcap
Metal-Insulator-Metal capacitor
xxv
MCML
Metal Oxide Semiconductor Current Mode Logic
MSFF
Master-Slave Flip-Flop
MSFF OUT
MSFF Divider Output
MSFF sample
MSFF Output Test Port
MT ail,M
Tail Transistor, Master Flip-Flop
MT ail,S
Tail Transistor, Slave Flip-Flop
M1, M2, ...
Metal Layer Name
M6T
Thick Metal6 Layer
NMOS
n-type Metal Oxide Semiconductor
NSW
ILFD NMOS Switch Transistor
neg-gm
negative gm
nMOSFET
n-type Metal Oxide Semiconductor Field Effect Transistor
OC
Optical Carrier
PD
Phase Detector
PFD
Phase and Frequency Detector
PLL
Phase-Locked Loop
PMOS
p-type Metal Oxide Semiconductor
PSD
Power Spectral Density
PSS
Periodic Steady State
PSU
Power Supply Unit
PSW
ILFD PMOS Switch Transistor
Q+, Q-
Flip-Flop Differential Output Signals
RBW
Resolution Bandwidth
RC
Resistor-Capacitor
xxvi
REF pos
Reference Input Signal (positive)
REF neg
Reference Input Signal (negative)
RF
Radio Frequency
RMS
Root Mean Square
R(name)
Resistor Identification
SCL
Source Coupled Logic
SDD
Symbolically-Defined Device
SiGe
Silicon Germanium
SOI
Silicon On Insulator
SONET
Synchronous Optical Network
Spec. A.
Spectrum Analyzer
SS
Slow-Slow CMOS Process Corner
SSB
Single Side Band
STI
Shallow Trench Isolation
TAHB
Transient Assisted Harmonic Balance
TL
Transmission Line
TSMC
Taiwan Semiconductor Manufacturing Company
TT
Typical-Typical CMOS Process Corner
UMTS
Universal Mobile Telecommunications Service
VCO
Voltage Controlled Oscillator
VCO neg
VCO Output Line (negative)
VCO pos
VCO Output Line (positive)
VCOctrl neg
VCO Varactor Control Line (negative)
VCOctrl pos
VCO Varactor Control Line (positive)
xxvii
VHSC
Very High Speed Circuits
VNA
Vector Network Analyzer
WLAN
Wireless Local Area Network
XOR
Exclusive OR
xxviii
Chapter 1
Introduction
The demand for increased data rates in communication systems as well as applications such as automotive radar are driving the operational requirements of circuits
and systems to higher frequencies. At the same time there is pressure to bring the
cost of new technologies down to allow a greater uptake by end users. Increased
levels of integration are being used to reduce the cost of cost-sensitive applications.
Through continued refinement of its processes, complementary metal-oxide semiconductor (CMOS) technology now has the capability of operating in the tens of gigahertz
range. CMOS technology is used extensively for computer and memory integrated
circuit (IC) fabrication and is well-suited to high levels of integration, making it an
ideal candidate for high-volume low-cost applications.
As operational frequencies increase the challenge of signal generation also increases. High frequency signals may be generated by using low frequency oscillators
and converting them to higher frequencies using frequency multiplier circuits. CMOS
frequency doublers have been reported recently up to 75 GHz [1], [2].
Multipliers typically use device non-linearities to generate signals at the required
1
CHAPTER 1. INTRODUCTION
2
harmonics. This does present challenges, however, as very high harmonic multiples
required the devices to exhibit highly non-linear performance and have a substantial
input power to generate the required signals. Multipliers are also application specific,
in that the multiplication function is their sole use.
It is also possible to achieve a frequency multiplication of an input signal using
a phase-locked loop (PLL) which contains a divider circuit in its feedback path.
The PLL has been extensively studied in the literature, and is commonly used for
communication circuits. Because of its potential for other uses such as modulation
and demodulation, a frequency multiplying PLL was selected for the research topic.
The PLL under study is novel in its use of a completely differential architecture.
Integrated circuits may display undesirable behaviour when exposed to noise signals
that are coupled into the chip. A differential architecture can make the circuit less
susceptible to these potentially disruptive interference signals. The design also incorporates a low multiplication factor of 4, which benefits the noise performance of the
system.
Contributions of the research include the design, fabrication and test of an integrated 26 GHz frequency-multiplying PLL using a 0.18-µm CMOS process. The
26 GHz PLL output frequency is the highest reported to date using this process. A
fully-differential circuit realization resulted in common mode rejection ratio (CMRR)
values in excess of 20 dB for discrete and broadband injected signal frequencies less
than 1 MHz. An analytical model for static phase offset for a multiplying phase
detector was also presented. Finally, PLL output phase noise was determined using
analytical models of the PLL closed loop transfer functions for the Reference- and
voltage controlled oscillator (VCO)-generated phase noise and confirmed via test.
CHAPTER 1. INTRODUCTION
3
Recently reported PLLs and tools for system level performance prediction are
presented in Chapter 2. A review of recent publications on PLLs realized in CMOS
technologies is undertaken, as well as the VCO, dividers and phase detector subcircuits.
Chapter 3 examines the operation of the PLL frequency multiplier using both timeand frequency-domain analyses. The time domain performance of the PLL is derived
from the loop differential equation. Phase plane analysis is introduced as a means of
determining locking bandwidth through an analog computer simulation of the loop
differential equation, taking into account the initial conditions for phase and frequency
offsets. Frequency domain analysis is derived from the PLL closed loop transfer
functions at steady state conditions, and is presented as a tool to predict tracking
bandwidth, noise transfer characteristics and potential areas of circuit electromagnetic
interference (EMI) susceptibility. A review of design considerations for the PLL subcircuits is also presented; the VCO’s critical role in the PLL system is examined, with
design emphasis placed on rejection of common mode (CM) noise; a review of phase
noise in VCOs is also undertaken with design recommendations for reduction of VCO
phase noise presented.
The sub-circuits associated with the PLL are examined in greater detail in Chapter 4. Circuit diagrams for each sub-circuit are presented with an accompanying
description of circuit operation. Design modifications for the first- and second-stage
dividers are presented to build on the differential nature of the design and to extend
the operational frequency range. The phase detector non-ideal behaviour is analyzed
and attributed to intrinsic properties of the associated transistors.
Chapter 5 returns to the top level PLL from an implementation point of view. The
CHAPTER 1. INTRODUCTION
4
integrated layout is presented with descriptions of the interconnecting transmission
lines and the test coupler. System level performance evaluation for the PLL is then
discussed. The challenges and results of time domain simulation are identified for
the system, followed by the means of evaluating the ability of the system to reject
common mode noise. The chapter concludes with the method used to calculate the
system phase noise from the Reference and VCO sources and a consideration of the
effect of the multiplying factor N on phase noise.
Test results are presented from selected sub-circuits and the integrated system in
Chapter 6. Test circuitry and operational conditions are identified, and evaluated
sub-circuit performance results are presented. At the PLL system level, locking and
tracking bandwidths are measured and compared to the predicted/expected values.
Common mode rejection results are presented that confirm the desirable rejection
capability of the PLL differential design. Finally, measured phase noise is compared
to calculated phase noise, showing very good agreement between the two.
Chapter 7 summarizes the important results and contributions of the research
work. Based on the successful results, further research areas are proposed for the
optimization and improvement of the design.
Chapter 2
Literature Review
2.1
Introduction
The development of high frequency multiplying PLLs has followed the emergence
of applications enabled by the scaling of the CMOS process. Applications already
using these PLLs include wireless local area network (WLAN) applications such as
IEEE 802.11g and 802.11a at 2.4 and 5 GHz and 3rd generation wireless applications.
Other applications include 20 and 40 Gbit/s backplane and optical links, 60 GHz
wireless transceivers, and automotive collision avoidance systems operating between
76 and 77 GHz [3]. Emphasis has been placed on developing solutions for several key
performance limitations, including lower power requirements, phase noise/jitter and
operational frequency and bandwidth.
This chapter first reviews the performance of selected PLL systems reported since
2000, with an emphasis on CMOS-based realizations. A survey of publications associated with the critical sub-circuits is then presented.
5
CHAPTER 2. LITERATURE REVIEW
2.2
6
Selected Review of PLL Performance
A 5 GHz WLAN receiver in 0.24-µm CMOS using a PLL-based frequency synthesizer
was reported in 2000 [4]. The PLL in the paper synthesized frequencies between 4.84
and 4.994 GHz, using a reference input frequency of 11 MHz and a loop bandwidth
of 280 kHz. Out-of-band phase noise was measured at -101 dBc/Hz at 1 MHz offset.
A multiple-output frequency synthesizer with very low jitter performance using
a PLL-generated 2.4 GHz signal as the basic clock source has been developed [5].
The core PLL employed a 25 MHz crystal oscillator as the reference clock, with a
phase-frequency detector, high-swing cascode charge pump with programmable output current for UP-DOWN mismatch compensation and setting of loop bandwidth,
high speed prescalers, a 200 MHz low-jitter output and the feedback divider. Fig. 2.1
shows the frequency synthesizer block diagram.
c
Figure 2.1: Block Diagram, 2.4 GHz Frequency Synthesizer [5], 2002
IEEE
To minimize jitter in the system, the LC-VCO used a differential complementary
CHAPTER 2. LITERATURE REVIEW
7
structure (i. e. , cross-coupled PMOS and NMOS transistors) with an LC tank optimized for phase noise and power consumption (small capacitor for tuning purposes,
inductor operated close to its self-resonant frequency). The jitter-critical path from
the VCO output to the 200 MHz clock output was implemented in differential current mode logic, selected for its speed as well as power-supply rejection ratio and
lower switching noise into the PLL supplies. Three power supplies were used in the
synthesizer to isolate jitter-critical systems from noise.
At the 200 MHz clock output, phase noise was measured versus loop bandwidth.
For a loop bandwidth of 600 kHz the phase noise at 1 MHz offset was -116 dBc/Hz
with a long- term jitter RMS of 5 psec; for a PLL bandwidth of 1.5 MHz the phase
noise at 1 MHz offset was -118 dBc/Hz with a long-term jitter RMS of 3 psec. The
authors stated that while the increased PLL bandwidth gave a lower noise floor,
the option to increase the bandwidth further was restricted by stability constraints
relating to the ratio of the 25 MHz reference clock frequency and the PLL bandwidth.
A low-jitter 2.5 GHz input / 10 GHz output clock-multiplier unit was reported
[6] in a standard 0.18-µm CMOS process. The design employs a tri-state phase and
frequency detector (PFD) followed by a charge pump (CP) and the loop filter. The
PFD outputs two signals (UP and DN) that are used to drive current sources in
the CP that either add to or subtract from the charge on the loop filter capacitors.
This causes either a rise or a drop in control voltage for the VCO. The main speed
limitation of the standard tri-state PFD composed of 2 D flip-flops and an AND reset
logic gate was identified as the relatively slow reset path. A novel design for the
phase detector was proposed whereby the flip-flop structure of the PFD was replaced
by a pair of AND gates using the reference input (Ref) and in- and quadrature-phase
CHAPTER 2. LITERATURE REVIEW
8
outputs from the static divider circuit (DivI, DivQ). Figure 2.2 shows the desired
phase detector response and the circuit implementation, where icp,out is the output
current of the charge pump.
Figure 2.2: 2.5 GHz phase detector response and implementation (a) Desired PD
c
response, (b) Circuit implementation [6], 2004
IEEE
When the UP and DN signals were supplied to a charge pump the net charge
pumped in the PLL loop filter was linearly dependent for phase differences close to
zero degrees. For the case of ideal quadrature inputs the linear range is 0 ± π/2
radians, that is less than the standard tri-state PFD range of 0 ± 2π radians. The
tradeoff for reduced locking range compared to the tri-state PFD was an increase in
operational speed, allowing the use of a reference at considerably higher frequency
(2.5 GHz).
The use of a high frequency reference allowed the loop divider to have a low value
of 4. This has several advantages from a system point of view:
CHAPTER 2. LITERATURE REVIEW
9
1. A small division factor N results in less noise multiplication factor for low frequency offsets than for large N,
2. The PLL optimized loop bandwidth may be increased (The optimized loop
bandwidth is determined by the intersection of the noise spectrum of the sum
of all in-band phase noise generators in the PLL and the noise spectrum of
the VCO [6]; lower N results in lower in-band phase noise contribution and a
higher-frequency intersection for optimized loop bandwidth),
3. Larger loop bandwidth allows for smaller values of capacitor components in the
loop bandpass filter.
Use of the high frequency reference placed limitations on how narrow the UP and
DOWN pulses could be; a minimum duty cycle of 25% was required to avoid incomplete switching of the CP current sources resulting in a phase detector / charge pump
dead zone.
The optimized loop bandwidth was selected by assuming that the CP noise would
dominate the in-band noise. The CP noise was then compared to the free-running
VCO noise, and the loop bandwidth selected for where the two intersected. Phase
noise of the various components was minimized through the use of patterned ground
shields for the VCO inductor, and differential signal processing for UP and DOWN
signals as well as low-voltage PMOS mirrors in the charge pump. The reported output
jitter in the circuit was 0.22 ps rms, well below the 10-Gb/s SONET recommendation.
A 24 GHz PLL in standard 0.18-µm CMOS [7] addressed the challenges of low
supply voltage, low power and high operating frequency by stacking the VCO and the
divider circuits, as shown in Figure 2.3. The VCO used a design similar to the Colpitts
common drain oscillator but with the source-gate capacitive feedback replaced by
CHAPTER 2. LITERATURE REVIEW
10
c
Figure 2.3: Stacked 24 GHz VCO and divider [7], 2006
IEEE
inductive feedback using a transformer. The transformer allowed the voltage at the
gate to swing above its bias voltage and the signal at the source to swing below the
ground, enabling the use of a reduced supply voltage. The transformer was optimized
for phase noise in a Colpitts oscillator with a practical coupling coefficient k of 0.7
p
and a turns ratio N = Lgate /Lsource of 3.2. The divider is a modified version of
a source-coupled logic (SCL) divider, with inductive loads to extend the frequency
range. The conventional current source of the regenerative latch was removed for
low-voltage operation. The phase detector was based on the Gilbert cell architecture;
a current mismatch compensation network was used to maintain current symmetry in
the output buffer network when operating close to the supply voltage or ground. The
CHAPTER 2. LITERATURE REVIEW
11
PLL consumed 17.5 mW from a 1V supply, and showed in- and out-of-band singlesided phase noise at 100 kHz and 10 MHz frequency offsets of L(100 kHz)=-106.3
dBc/Hz and L(10 MHz)=-119.1 dBc/Hz, respectively.
Cao et al. [8] presented a 50 GHz PLL fabricated in a 130-nm CMOS process.
The VCO used a negative gm / LC tank oscillator, with tuning provided by AMOS
varactors. The VCO second harmonic was sampled from the common node at the
midpoint of the VCO inductor, and was isolated from the power supply by a microstrip
transmission line of length λ/4 at the second harmonic frequency. An injectionlocked frequency divider (ILFD) was used for the first division stage, followed by a
÷512 static divider circuit. The ILFD employed direct injection for one of the VCO
differential outputs across the LC tank, with the complementary VCO signal being
routed to the output. The ILFD also used AMOS varactors for tuning and tracking
the VCO frequency, allowing for a locking range of 45.9 to 50.5 GHz. A charge pump
phase detector (PD) and second order LPF completed the circuit. Phase noise was
measured at L(1 MHz)=-72 dBc/Hz, with a total consumed power of 57 mW from a
combination of 1.5 V / 0.8 V DC sources.
A 75 GHz PLL using 90-nm CMOS was presented recently [3]. The authors
reduced the loading effects of subsequent circuitry on the VCO by modeling three
series inductors as lossy transmission lines of three-quarter wavelength (3λ/4) at 75
GHz shorted at one end and open at the other. With the negative gm cell placed
at λ/4 from the short-circuit a maximum is created at the VCO core, with another
maximum at the 3λ/4 that is 180◦ out of phase. The λ/2 distance between the VCO
output and the neg. gm cell rotates the loading impedance by 360◦ ; the loss of the
transmission line means that the capacitive load is translated to a lossy but smaller
CHAPTER 2. LITERATURE REVIEW
12
capacitance at the VCO core. Fig. 2.4 shows the VCO and divider circuits, with the
3λ/4 transmission lines identified as inductors; inductor LR is used to resonate out
parasitic capacitance associated with nodes C and C 0 .
c
Figure 2.4: Circuit diagram, 75 GHz VCO and first-stage divider [3], 2008
IEEE
The divider topologies were carefully selected to meet bandwidth and operational
frequency requirements. The first divide-by-two stage used identical ILFDs to preserve symmetry at the VCO, with one set of differential ILFD outputs going to a test
pad and the second ILFD outputs being fed to the next divider stage. The second
divide-by-two stage was realized as a Miller divider with a bandpass load, while the
third through sixth stages were designed as static dividers.
The phase and frequency detector used a pair of single sideband (SSB) mixers to
mix two quadrature signals from the reference input and the last stage of division.
This allows a significant reduction in the reference clock feedthrough and a lessening
of reference spurs at the output.
CHAPTER 2. LITERATURE REVIEW
13
The integrated PLL showed locking from 73.4 to 73.72 GHz. Measured VCO
phase noise was L(100 kHz)=-72 dBc/Hz; an inferred value at 10 MHz was L(10
MHz)=-114 dBc/Hz. The nominal power consumption from a 1.45 V supply was 88
mW.
A summary of the PLL systems discussed in this section may be found in Table
2.1.
Parameter
CMOS Process
Ref. Freq. (GHz)
O/P Freq. (GHz)
Phase Noise, dBc/Hz
100 kHz
1 MHz
Supply Voltage, V
Power Diss., mW
[4]
[5]
[6]
[7]
0.24-µm 0.18-µm 0.18-µm 0.18-µm
0.011
0.025
2.488
12.1
4.84-4.99
2.4
9.953
24.2
N/A
-101
1.5/2
25
N/A
-118
1.6-2.0
20
N/A
N/A
1.8
81
-106.3
N/A
1
17.5
[8]
130-nm
0.050
50
[3]
90-nm
2.3
75
N/A
-72
1.5/0.8
57
-88
N/A
1.45
88
Table 2.1: Summary, Reviewed PLL Systems
2.3
Review of PLL Subcircuits
Many of the PLL systems examined in the previous section considered performance
of the subcircuits. An expanded review of the key subcircuits of the PLL (VCO,
dividers and phase detector) is continued here.
2.3.1
Voltage Controlled Oscillator (VCO)
The VCO is the element responsible for frequency generation in the PLL; as such,
extensive investigation into maximizing the performance (increasing tuning range,
decreasing phase noise) has been carried out.
CHAPTER 2. LITERATURE REVIEW
14
Hajimiri and Lee [9] reported on the effects of different noise sources in complementary (i. e. , using both PMOS and NMOS transistors), cross-coupled differential
LC oscillators. Fig. 2.5 shows the circuit diagram for the VCO, where Mtail is the
tail transistor and the tail current Itail flow is indicated when completely switched
to one side. The authors used their time variant phase noise model to analyze the
c
Figure 2.5: Circuit diagram, complementary differential LC-VCO[9], 1999
IEEE
noise contributions of noise sources in the circuit, including the PMOS and NMOS
devices and the biasing tail transistor. They found that the addition of a capacitor in
parallel with the biasing tail transistor served to improve the symmetry of the waveform, leading to better phase noise performance. The upconversion of 1/f noise was
found to be the dominant noise contributor; the use of the complementary oscillator
structure improved the rise- and fall-time symmetry, which resulted in a lower 1/f 3
noise corner frequency. With the goal of obtaining minimum phase noise for a given
CHAPTER 2. LITERATURE REVIEW
15
power dissipation, the authors reported phase noise of -121 dBc/Hz at 600 kHz offset
for a 6 mW power dissipation at 1.8 GHz.
A monolithic VCO in 0.25-µm CMOS operating at 5.35 GHz was reported by
Hung et al. [10]. The authors constructed the VCO using cross-coupled PMOS
transistors, generating a negative resistance to cancel the losses in the LC tank.
PMOS transistors were selected based on lower 1/f noise than NMOS transistors
for a given current and transconductance (contributing to VCO phase noise in the
1/f 3 region) and smaller hot carrier effect (contributing to VCO phase noise in the
1/f 2 region). Two varactor structures were implemented on different VCOs: a p+ /nwell varactor and an accumulation mode MOS (AMOS) varactor structure. Measured
single-sided phase noise for the p+ /n-well VCO at 1.5 V VDD with 4.7 mA tail current
and a centre frequency of 5.35 GHz was -117 dBc/Hz at a 1 MHz offset frequency.
Measured single-sided phase noise for the AMOS varactor VCO at 1.5 V VDD with
4.7 mA tail current and a centre frequency of 5.23 GHz was -116.5 dBc/Hz at a 1
MHz offset frequency. The authors attributed the similar phase noise performance
to the low quality (Q) factor of the inductor and postulated that at higher frequency
the Q-factor of the varactor would become dominant, favoring the AMOS varactor
implementation.
Mukherjee et al. [11] presented a 10 GHz differentially-tuned LC VCO using an
NMOS cross-coupled core with a PMOS tail current source. Fig. 2.6 shows the circuit
diagram for the VCO.
The NMOS core was selected because of a better tuning range; the PMOS tail
current source was selected because of its lower flicker noise and its tapping of the
tank common-mode point which has lower ac-variation than the common-source tap
CHAPTER 2. LITERATURE REVIEW
16
c
Figure 2.6: Circuit diagram, 10 GHz differentially-tuned LC-VCO [11], 2002
IEEE
required of an NMOS tail current source. Differential tuning was accomplished by
cascading AMOS varactors with fixed capacitors and applying differential control
voltages across the AMOS varactors. The tank inductor Q was maximized in the
0.13-µm CMOS process by stacking the upper 4 metal layers. Simulated results at a
carrier frequency of 10 GHz showed a single-sided phase noise of -99 dBc/Hz at an
offset frequency of 1 MHz, with a tuning range of 3.7 GHz.
Novel MOS varactor designs were presented by Maget et al. [12] that improved
the frequency tuning capability for a UMTS VCO. The first version of the device
used the basic structure of an AMOS varactor but used shallow trench isolations
(STIs) to separate the active area underneath the thin gate oxide and the n-well
contacts. The second version used the basic construction of the first version, but
periodically replaced short sections of the STIs and n-well contacts with grounded
p+ regions. The STIs act to reduce the parasitic overlap capacitances of the gate and
n-well contacts because of the increased thickness of the STI; the parasitic fringing
CHAPTER 2. LITERATURE REVIEW
17
capacitances between the gate and n-well contacts are also reduced because of the
increased distance between the gate and n-well contacts due to the STI. The periodic
grounded p+ regions in the second version act to extract any thermally-generated
holes when the varactor is driven into depletion, thus preventing an inversion layer
from being formed and allowing the varactor to be driven deeper into depletion with
an associated lower capacitance. When compared to a standard nMOSFET varactor
tuning range of ±7%, the first version had a tuning range of ±11%, while the second
version had a tuning range of ±13% about a normalized centre frequency in the 3.7
GHz range.
A 3.8 to 5.7 GHz VCO using differentially-tuned AMOS varactors [13] was found
to offer good common-mode noise rejection. Fig. 2.7 shows the circuit diagram for
the differentially-tuned VCO. The upconversion of low-frequency noise by variation of
c
Figure 2.7: Circuit diagram, 3.8-5.7 GHz differentially-tuned LC-VCO [13], 2003
IEEE
CHAPTER 2. LITERATURE REVIEW
18
the varactor capacitance shows up as phase noise about the carrier. A differentially
tuned varactor structure was presented that reduced the effects of common-mode
noise injected at the varactor control lines. A comparison of singly- and differentiallytuned VCOs showed a 9 dB improvement in phase noise at a 1 MHz offset for the
differentially-tuned VCO at a centre frequency of 4.4 GHz. The circuit was realized
in a 0.13-µm CMOS silicon on insulator (SOI) technology.
A VCO designed to work in excess of 40 GHz was reported in 2004 [14]. The
VCO was designed specifically for SONET OC-768 clock and data recovery (CDR),
with a required phase noise single-sided power spectral density L{∆ω = 1 M Hz}
of -87 dBc/Hz. Emphasis was placed on improving the Q factor of the capacitor
because of the small L / higher Q-factor of the inductor. Care was taken in the
EM-modeling of the inductor to account for skin effects. The circuit was fabricated
in a 0.13-µm standard CMOS process that included 8 metal and 1 polysilicon layers,
low-k interconnect dielectric, and metal-insulator-metal (MIM) capacitors between
M7 and M8.
A 24 GHz VCO for use in automotive medium-to-short range detection was proposed in a 0.18-µm CMOS process [15]. The VCO used series-stacked PMOS and
NMOS transistors in a cross-coupled configuration for current re-use; the configuration uses half the supply current compared to a conventional complementary LC
VCO. An LC noise filter was used at the NMOS source to smooth the abrupt change
in current at switching instances. By proper selection of the inductor and capacitor
values, the proposed VCO waveform can be made more symmetric as a result of rejection of the VCO second harmonic and absorption of current spikes. Simulations
showed that VCO phase noise can thus be reduced. AMOS varactors are used because
CHAPTER 2. LITERATURE REVIEW
19
of their large tuning range and potentially lower phase noise contribution. Simulated
phase noise for a 24 GHz signal at a 1 MHz offset was -108 dBc/Hz, with a tuning
range of 2.7 GHz and a DC core power consumption of 8.2 mW from a 1.8 V DC
supply.
A push-push 26 GHz VCO was reported in a 0.18-µm CMOS process [16]. The
authors used a cross-coupled PMOS LC VCO for generation of the fundamental
frequency because of the better phase noise performance. Fundamental and second
harmonic signals were amplified through the output buffers and were then combined
at the output port; the fundamental signals cancel each other because of their 180◦
phase difference, while the second harmonic signals add in phase. The output buffers
were biased in the triode region to increase the non-linearity of the devices, resulting
in greater second harmonic content. MOS varactors were used for tuning elements,
with a measured second harmonic tuning range of 24.14 to 27.76 GHz. The VCO core
consumed a total current of 15.5 mA with a drain bias of 1.2 V. Measured second
harmonic phase noise for a 26.9 GHz signal at a frequency offset of 1 MHz was -102.9
dBc/Hz, with a minimum output power of -17.9 dBm.
Alternate frequency sources commonly used as low- or medium-frequency reference sources because of their stability and tunability include crystal oscillators and
dielectric resonator oscillators (DROs). A selection of commercial crystal oscillators
examined revealed an operational frequency range in the tens of megahertz to 130
MHz, with 10 kHz frequency offset phase noise values of between -155 dBc/Hz and
-174 dBc/Hz, where dBc/Hz represents the phase level in decibels referenced to the
carrier power over a 1 Hz resolution bandwidth. A sampling of dielectric resonator
oscillators (DROs) at frequencies between 5 and 7 GHz revealed values of phase noise
CHAPTER 2. LITERATURE REVIEW
20
at a 10 kHz offset frequency of between 93 and 108 dBc/Hz. Table 2.2 lists the typical performances for several commercially available crystal and dielectric resonator
oscillators.
Realization Freq.(GHz)
Crystal[17]
Crystal[18]
Crystal[19]
DRO[20]
DRO[21]
DRO[22]
DRO[23]
0.010
0.100
0.100
5
6-7
6.259-6.579
3.5-7
Phase Noise (dBc/Hz)
10 kHz Offset 100 kHz Offset
-155
-155
-171
-172
-174
-100
-125
-108
-126
-96
-121
-93
-119
Table 2.2: Phase Noise Comparison of Crystal and Dielectric Resonator Oscillators
(DROs)
As a point of comparison, recently published work on dielectric oscillators focuses
on very low phase noise performance through the use of high quality factor resonators.
Stockwell et. al. report a DRO at 1.3 GHz with phase noise at a 10 kHz offset of
-147 dBc/Hz [24]. The DRO used a resonator with a loaded Q of 14000. A sapphiresilicon germanium (SiGe) HBT oscillator operating at 4.7 GHz was reported [25].
The ambient-temperature uncompensated device had measured phase noise of -150
dBc/Hz at a 10 kHz offset and a resonator loaded Q of 60000. Both of the reported
DROs use resonators with high Q factors to achieve the low phase noise close to the
carrier, and are intended for specific timing-critical applications.
CHAPTER 2. LITERATURE REVIEW
2.3.2
21
Frequency Dividers
Master-Slave Flip-Flop Divider
The 2:1 frequency divider is the most basic divider structure used in PLL circuits.
The D-type master-slave flip-flop (MSFF) divider has been extensively investigated
because of its large operational bandwidth and potentially high operational frequency
as fabrication technology improves. Wolhmuth et. al. reported an operational frequency of 27 GHz for a MSFF divider [26]. Fig. 2.8 shows the circuit diagram for the
MSFF; in order to achieve a divide-by-2 configuration, the outputs of the slave flip-
c
Figure 2.8: Schematic diagram, 27 GHz MSFF [26], 2003
IEEE
flop are inverted and fed to the inputs of the master flip-flop (not shown in the circuit
diagram). The high achievable speed was made possible by the circuit fabrication in
a high performance 0.13-µm CMOS process and the use of MOSFET current-mode
logic (CML). CML is based on current sources and differential amplifiers which in
combination with the use of differential signals allows a low voltage swing (in the
CHAPTER 2. LITERATURE REVIEW
22
range of 0.3 to 0.5 Vpp ). The rapid switching capability enables high operating speed
and bandwidth (2 to 27 GHz) and low power consumption (45 mW total for the buffer
and VCO at a 1.5 V DC supply voltage).
A realization of a MSFF divider in a standard 0.18-µm CMOS process [27] achieves
an operational speed of up to 17 GHz by employing a new topology for the highspeed latch. Fig. 2.9 shows the circuit schematic for the high-speed latch. The
c
Figure 2.9: Schematic diagram, high speed latch [28], 2006
IEEE
latch design has the cross-coupled pair (M3/M4) always drawing current from the
output; this implementation does not require time for the charge to build up during
the latching phase. The cross-coupled pair also reduces the rise and fall times for the
output voltages at the drain nodes (X and Y) by reducing the drain node equivalent
resistance through the presentation of a negative resistance. This design was verified
at 40 GHz [28] using a 0.18-µm silicon-germanium (SiGe) bipolar CMOS (BiCMOS)
process where only CMOS transistors were utilized. Power consumed was 9 mW from
a 1.8 V source.
CHAPTER 2. LITERATURE REVIEW
23
Continued scaling of CMOS processes allows even higher operational frequencies
for standard MSFF divider circuits. A performance analysis was carried out for a 66
GHz maximum frequency CML divider in 90 nm silicon on insulator (SOI) CMOS
[29]. The authors examined the performance variations for voltage and temperature
variations; they concluded that because of the non-scalability of some process tolerances, statistical design, measurements and analysis was the only way to quantify
deep sub-micron circuit performance. Statistical analysis was carried out on a 65 nm
MSFF divider realization to support design equations [30]. An operational frequency
greater than 90 GHz was presented, as well as a method for estimating yield of the
design based on input power and frequency. Because of the wideband operation of
the CML divider it is an attractive solution for very high speed division requirements
that must consider component yield.
Injection-Locked Frequency Divider
Another divide-by-2 circuit which is attractive for high frequency CMOS applications
is the injection-locked frequency divider (ILFD). The ILFD uses a tuned oscillator
core resonating at a free-running frequency ωN . Under proper phase and magnitude
conditions, when an input signal at frequency ωin ( ωin = 2ωN ± ∆ω) is injected into
the circuit the oscillator will oscillate at one half the input frequency (ωo = ωin /2),
where ±∆ω is the input locking bandwidth of the ILFD [31], [32]. The ILFD is
characterized by a more limited operational range (typically a few percent of ωN ), but
consumes significantly less power than MS-FF configurations (typically in the tensof-mW range). Its high operational frequency as observed in the afore-mentioned 75
GHz PLL [3] make it an excellent candidate for first-stage division in a high-frequency
CHAPTER 2. LITERATURE REVIEW
24
PLL.
An ILFD was reported as the first divider stage for a 5 GHz wireless LAN receiver
[4]. The oscillator core used a cross-coupled differential LC oscillator; the control
voltage of the ILFD varactors was tied to the VCO control voltage, allowing the resonant frequency of the output tank to track the input frequency. The VCO signal
was injected into the tail transistor; an additional transistor was used to maintain
load symmetry. The tank inductance–quality (LQ) factor required a high value for
reduction of power consumption; this was achieved through optimization of the inductance and Q value by trading off inductor value, area and line width. The circuit was
realized in 0.24-µm CMOS technology, and showed a locking range of approximately
20% of the input frequency for a 1V (+10 dBm, referenced to 50Ω) input signal level.
An ILFD using an alternate injection technique was reported in 2004 [33]. Fig.
2.10 shows the circuit schematic for a 50 GHz injection-locked frequency divider,
where IN and INX are the complementary inputs and Q and QX are the complementary divided outputs.The limited locking range of the tail-injected ILFD in CMOS
realizations as described in [4] was attributed to the inefficient injection path through
the tail transistor, due to the large input capacitance and the high width necessary
for DC bias and RF input transconductance. A direct injection scheme was presented
based on a PMOS or NMOS transistor switch across the LC tank. Because the switch
transistor had no biasing function and was not a transconductance device it could be
sized much smaller, resulting in lower input capacitance. The design was further optimized by using both PMOS and NMOS switches in a quasi-differential realization,
as well as PMOS/NMOS cross-coupled pairs to complement the differential VCO
signal in an integrated application. Frequency division at 15, 40 and 50 GHz input
CHAPTER 2. LITERATURE REVIEW
25
Figure 2.10: Schematic diagram, 50 GHz injection-locked frequency divider [33],
c
2004
IEEE
frequencies was confirmed. The circuits used 0.12-µm CMOS technology with 1.5 V
power supply, and displayed power consumption between 3 mW (for 40, 50 GHz) and
23 mW (15 GHz).
2.3.3
Phase Detector
Digital clock and data recovery (CDR) systems are a significant application for PLLs.
Considerable research has gone into the design of phase detectors for minimization of
phase noise and jitter, as well as increasing operational bandwidth and frequency for
higher data rate applications.
CHAPTER 2. LITERATURE REVIEW
26
An overview of design techniques for CMOS phase detectors was given by Soliman et. al. [34]. The authors discussed a number of different PDs, consisting of
combinational (multipliers such as the Gilbert cell [35]), XOR, and edge-triggered
detectors (R-S latch, D flip-flop phase/frequency and bang-bang) and presented pros
and cons for each design. Fig. 2.11 presents the block diagram for the D flip-flop
phase/frequency detector (PFD), also known as a tri-state PFD. The output voltage
V out (defined as the difference between the average values of QA and QB ) versus the
input phase difference ∆φ is shown, where Vm is the maximum output voltage magnitude. Digital PDs using one or more flip-flops were observed to suffer from longer lock
Figure 2.11: D flip-flop phase/frequency detector block diagram and response [34],
c
2004
IEEE
time due to latch stabilization requirements than their analog counterparts, making
analog PDs more suitable for high speed applications. A reduction of the PD output
to zero in a locked condition was noted to reduce the charge pump activity, leading
to reduced VCO control line activity and output jitter. A warning was given about
input pattern sensitivity of the PD that could potentially lead to undesired VCO
CHAPTER 2. LITERATURE REVIEW
27
jitter or frequent loss of lock. The authors concluded by observing that analog PDs
offered a high operation speed, whereas digital PDs provided a large lock range and
a better lock condition.
Digital phase detectors are often used in conjunction with a charge pump that is
used to increase or decrease the charge on a integrating capacitor to generate the VCO
control voltage. The charge pump is driven by control pulses (typically identified as
UP and DOWN) generated by the phase detector; the width of the UP and DOWN
pulses is dependent on the phase difference between the reference input and the
internal VCO-derived signal. For phase differences that are less than some minimum
amount φ0 the output pulse width of a flip-flop based detector may be insufficient
to turn on the subsequent charge pump, leading to an accumulation of phase error
or increased output jitter of the VCO [36]. This phase difference region is identified
as a dead zone. To minimize the effect of this dead zone a phase/frequency detector
(PFD) - charge pump combination which incorporates coarse- and fine-tuning loops
is often used.
An improved linear phase detector in conjunction with a complementary threestate frequency detector was introduced by Renaud and Savaria [37]. The digital
linear phase detector was composed of transmission gates and transistors that modify
the charge on the UP and DOWN integrator capacitors in one of 3 ways, based on the
phase relationships between the input reference signal and the internal VCO signal:
1. Reset, where the integrator capacitance is discharged, causing the capacitor
voltage to drop,
2. Charge, where the bias current pushes charges into the capacitance, causing
the capacitor voltage to rise, and
CHAPTER 2. LITERATURE REVIEW
28
3. Transfer, where the voltage on the capacitance is copied at the output.
The design allows a full half-cycle for discharge of the UP and DOWN integrator
capacitances, leading to a more linear response when the phase difference between
the input reference and internal signals approaches 180◦ . The logical ANDs between
the integrator capacitors and the PD outputs were not made with AND gates, which
would have introduced a dead zone into the PD; they were instead composed of two
series transmission gates.
The improved linearity PD was complemented by a three-state frequency detector
(FD) with additional filtering of the UP and DOWN outputs via secondary inputclocked flip-flops. These additions meant that the FD generates UP and DOWN
outputs only for phase differences greater than 180◦ , caused by signals that are not
frequency- aligned. For phase differences less than 180◦ the FD outputs neither UP
nor DOWN pulses, allowing the PD to take care of these cases.
In an integrated PLL, the proposed PD and FD may be combined to obtain a very
wide tracking range PLL that has low noise sensitivity, no dead zone, and produces no
UP or DOWN pulses in the locked state. The PD feeds a voltage-to-current converter
to maintain its linear behaviour, while the FD feeds a charge pump for faster locking
and parasitic/noisy signal filtering. A particular potential application identified by
the authors was high speed clock skew measurements. The circuit was simulated
using a 0.18-µm CMOS process with an achievable operating frequency of 4 GHz.
A dual slope phase/frequency detector and charge pump architecture was presented by Cheng et. al. [38]. The authors used coarse- and fine-tuning loops with
associated charge pumps to accelerate the locking time for an integrated PLL. The
CHAPTER 2. LITERATURE REVIEW
29
fine loop used a dynamic true single phase clock CMOS circuit as the PFD to reduce the dead zone to ≈10 psec. The fine CP used a current of a few microamps,
resulting in a lower PD/CP gain. The coarse-tuning loop used a conventional CMOS
PFD circuit with an associated dead zone, Φd . Increased CP current Ic in the coarse
loop was used to accelerate frequency acquisition. For phase differences Φe > Φd
the coarse PFD will output the corresponding CP current Ic . For phase differences
Φe < Φd the coarse PFD will output no current, and the fine PFD/CP will take over.
An adjustable pulse width (APW) input is incorporated in the coarse PFD circuit
to control the dead zone width. The APW input is controlled by the VCO control
voltage, which is generated based on the incoming frequency value; the dead zone
width of the coarse PFD is automatically tuned according to the input frequency,
with a narrower dead zone for higher input frequency and vice-versa. The circuit was
realized in a 0.35-µm CMOS process and displayed a lock time improvement of 82%
in comparison with a conventional PLL.
To capture the best performance characteristics of linear PDs (superior jitter
characteristics) and binary PDs (wide locking range and fast frequency acquisition)
a phase detector with an adjustable detector gain Kd was proposed [39]. The authors present a three-state phase/frequency detector that produces a response that
resembles either a binary PD or a linear PD, depending on applied voltage Vgctrl
at additional series transistors in the latch cross-coupled pairs of a D-type MSFF
configuration. The authors propose and demonstrate via simulation control voltage
Vgctrl variation with time, allowing a binary-style detector response for rapid initial
frequency acquisition, followed by a linear-style detector response for reduced jitter
and phase noise in the locked condition. Further research is proposed in implementing
CHAPTER 2. LITERATURE REVIEW
30
Vgctrl in a feedback loop including lock detection and half-rate PD design, allowing
the circuit to adaptively vary Vg depending on PLL locking status.
Yeo et. al. [40] examine a linear PD that does not use D-latches or D-FFs. The
linear Hogge PD [41] exhibits a linear relationship with the phase difference that
ideally drops to zero in the phase-locked condition. While this performance leads to
improved phase noise and jitter performance, linear PDs do suffer from half cycle
skew, where although the net charge injection for a charge pump configuration over
a cycle is zero, there is a charge-up/charge-down characteristic. Another potential
performance issue is the inability of the sequential D-FFs at high data rates to switch
and settle fast enough. The authors propose a linear PD composed of a half-cycle
delay element, two XOR gates and an AND gate. By delaying the data input by
one half of the delay input period TD and XORing it with itself, a reference pulse
REF of width TD /2 is generated at each data transition. The CLK input is XORed
with ’0’ to compensate for any delay in the data XOR gate; the output CLK delay is
a delayed version of CLK. When REF and CLK delay are ANDed the output (DIF)
will be ’1’ when both REF and CLK are high. The output DIF pulse width will be
linearly proportional to the phase difference between the data input and the CLK.
In the locked case, the DIF and REF pulses have equal width and are generated at
the same time, allowing the charge pump to be charged and discharged at the same
time, keeping the VCO control line constant and reducing jitter. The circuit was laid
out in 0.18-µm CMOS technology using MOS current mode logic (MCML) circuits
for high speed. The simulated performance of the PD exhibited significantly better
linear performance than a half-rate linear PD considered (operational input phase
difference range of 15 to 90 ps, vs. 40 to 80 ps for the half-rate PD).
CHAPTER 2. LITERATURE REVIEW
31
Robustness of design across process variations and technologies is an important
consideration for circuits. Rennie and Sachdev [42] presented a three-state binary
phase detector that shows considerably lower static phase offset variations than an
Alexander phase detector [43] constructed in the same CMOS technology. In previously published work [44] the authors had identified that sequential PDs including
the Alexander PD displayed a sensitivity to process variation and scaling. This was
attributed to the use of back-to-back flip-flops clocked on opposite edges of the CLK
signal. A single-stage D-FF PD was shown to be the most robust to process variations, but was not a tri-state device. The performance goal of the proposed PD was to
duplicate the performance of the Alexander PD but improve the robustness. The authors used a single-stage D-FF for phase detection, with a separate circuit composed
of two back-to-back D-FFs and an XOR gate for data retiming and creation of a reference pulse. The reference pulse is used to enable the operation of the charge pump on
a data transition, making the combination of D-FF phase detector and charge pump
a tri-state phase detector. Simulated total variation of the zero-crossing point for the
proposed PD showed a 75% reduction compared to an Alexander PD (3.55 ps static
phase offset variation vs. 13.9 ps). The PD designs were simulated in 0.18-µm CMOS
using standard process corners (SS, TT, and FF) and resistor variations (±20% at
each corner).
Rennie and Sachdev recently presented a CDR circuit incorporating an automatically calibrated linear phase detector [45]. The authors use a digital calibration technique on a Hogge linear PD to correct for static phase offsets. For a linear three-phase
detector in a locked condition where the CLK and data are perfectly synchronized the
DOWN and UP pulses have an ideal width of one half the data period (TD /2). For
CHAPTER 2. LITERATURE REVIEW
32
circuits affected by static phase offset the DOWN pulse maintains its TD /2 duration,
but the UP pulse has a width of TD /2 + ΦO , where ΦO is the static phase offset in
seconds. In spite of the unequal UP and DOWN pulsewidths the charge added by the
UP pulse is required to be equal to the charge removed by the DOWN pulse. This is
accomplished by varying the current associated with the UP pulse.
The calibration circuit discussed is designed to sense and compensate for static
phase offsets. The calibration is a two-step process: the first step is generation of an
internal data signal that is phase aligned with the clock signal, and the second step
is to set charge pump currents so as to eliminate any static phase offset effect. In
the first step, the external data source is disconnected and the VCO control voltage
on the LPF is set to a DC value for stability. The calibration data signal is created
by dividing the CLK signal derived from the VCO by 2. To compensate for the
finite phase difference due to the divide-by-2 operation between the CLK and data
signal, the CLK signal is fed through a programmable delay line; the delay is varied
by calibration logic until the secondary binary phase detector determines that the
CLK and data signals are phase aligned. The second step also requires that the
external data be disconnected; the VCO control voltage is no longer set to a DC
value and the phase aligned CLK and data signals generated in Step 1 are fed to the
linear Hogge PD. With the DOWN current set to a reference value the UP current
is then gradually increased from its minimum via control logic until a comparator
monitoring the voltage on the LPF determines that an equal amount of charge is
being added and subtracted. In normal operation after calibration the external data
is reconnected and values of UP and DOWN current are set as determined in Step 2.
The calibration circuitry is no longer active, and the CDR circuit operates without
CHAPTER 2. LITERATURE REVIEW
33
calibration interaction.
The circuit was implemented in a 0.18-µm CMOS process. When tested at 5 Gb/s
using a bit error rate test the circuit showed considerable bit error rate improvement
after calibration; for a pseudo-random bit sequence of 27 −1 the bit error rate dropped
from 4.6 × 10−2 to less than 10−13 .
A quadruplicate-harmonic-locked phase detector was presented as a component of
a 50.8-53 GHz clock generator [46]. The circuit was realized in 0.13-µm CMOS and
used a conventional frequency detector in parallel to the described phase detector.
The internal clock frequency is four times the input CLK frequency. The PD is
composed of two D-flip-flops, two XOR gates, an inverter and an OR gate. An UP
signal is generated by passing the internal clock signal through the inverter. The
DOWN signal is generated by ORing two pulse streams generated by XORing each of
the quadrature input CLK signals with a internal-clock-timed flip-flop-delayed version
of itself. The relative width of the DOWN pulse with respect to the UP pulse is used
to determine if the internal clock is early or late; at a locked case the UP and DOWN
pulse widths will be equal. Voltage-to-current converters are used in conjunction with
the lowpass filter to convert phase and frequency errors to a VCO control voltage and
reduce ripple in the loop filter.
A review of recently published PLLs and PLL components has been presented.
Ch. 2 will review the operation of the PLL frequency multiplier, and consideration
will be given to the selection of the operational sub-circuits.
Chapter 3
Phase-Locked Loop Frequency
Synthesis
3.1
Introduction
This chapter reviews the operating principles of a phase locked loop (PLL) for frequency synthesis, considering both time and frequency domain analyses for the Type I
second order PLL that was designed. Phase noise performance of the PLL is reviewed
with consideration given to the contributions of various noise sources within the loop.
PLL locking and tracking bandwidths are examined. The selection of PLL loop
parameters are then presented,with their implications for system-level performance.
Design considerations for the loop sub-circuits are considered, with justification for
the configurations selected.
34
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
3.2
35
PLL Operation
A PLL may be described as a linear feedback system that compares the system output
phase generated by a voltage controlled oscillator (VCO) with an input reference
phase using a phase comparator or detector (PD). A difference in phase between the
output RF signal and the input reference signal generates an error voltage that, after
filtering by a loop/lowpass filter (LPF), is used to change the frequency/phase of the
VCO in such a way that the error is minimized, leading to a locked state.
Consider the simplified feedback system of Figure 3.1, where θin (s) is the reference
θ in(s)
A(s)
θ out (s)
B(s)
Figure 3.1: Block Diagram, Feedback System
input phase, θout (s) is the total output phase, s=jω=j2πf, f is frequency, A(s) is
the forward gain and B(s) is the feedback gain. The open and closed loop transfer
functions G(s) and H(s)|closed,I/P for this system may be written as
G(s) = A(s)B(s)
H(s)|closed,I/P =
θout (s)
A(s)
=
.
θin (s)
1 − G(s)
(3.1)
(3.2)
PLLs are classified according to two criteria: Type and Order [47]. The numerator and
denominator of G(s) will be composed of polynomials. The roots of the denominator
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
36
polynomial are the poles of the transfer function, while the roots of the numerator are
the zeros of the transfer function. The Type of the PLL is determined by the number
of transmission poles of G(s) located at s=jω=0, i.e., at f=0 Hz. A Type I PLL has
one s=0 pole, a Type II PLL has two s=0 poles, etc. The denominator polynomial of
the closed loop function H(s)|closed,I/P will be of a certain degree; this degree is said
to be the order of the PLL. A Type I Second Order PLL will have one s=0 pole in
the open loop gain G(s), and a total of 2 poles in the closed loop gain H(s)|closed,I/P .
PLL performance may be analyzed in either the time or the frequency domain.
Time domain analysis is useful for examining transient properties of the PLL, such
as locking time and locking bandwidth. Frequency domain analysis is useful for
examination of noise characteristics in the steady state. Because of the usefulness of
both time and frequency analysis, PLL performance in each domain will be examined.
3.2.1
Time Domain Analysis
Analysis of PLLs is often carried out under the assumption that the loop is considered
linear. This assumption will be true for cases where the input reference signal and the
VCO-derived internal signal are close to lock. For cases where the input reference and
VCO are not close to lock, a non-linear solution provides useful insight into the locking
mechanism in the time domain. Viterbi [48] examines the time domain solution for a
non-linear PLL response. The analysis presented here follows his work for the PLL
configuration being considered. A solution to the non-linear PLL loop equation using
phase plane analysis will provide insight into the determination of locking range for
the PLL.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
37
Figure 3.2 shows time- and frequency-domain block diagrams for a frequencymultiplying PLL. The phase detector (PD) compares two input phases and outputs
PD
LPF
x(t)
e(t)
VCO
θ in(t)
θ out (t)
θ ’(t)
Divide−by−N
1
N
(a)
PD
θ in(s)
+
Σ
LPF
X(s)
KD
VCO
E(s)
F(s)
K0
s
θ out (s)
−
θ ’(s)
Divide−by−N
1
N
(b)
Figure 3.2: Block Diagram, Frequency-Multiplying PLL (a) Time Domain (b) Linear
Frequency Domain
an error signal x(t); θin (t) is the input reference phase and θ0 (t) is the output phase
multiplied by the feedback gain. The loop or lowpass filter (LPF) filters the PD
error signal x(t) and outputs the filtered error signal e(t). This filtered error signal
is then input to the VCO, which changes the output frequency and total output
phase θout (t). The total output phase is divided by a factor N before application to
the phase detector, such that θ0 (t) = θout (t)/N . The division of the output signal
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
38
phase/frequency by a factor N before application to the PD means that in a locked
state fout = N fin . This PLL therefore generates an output signal at N times the
input signal frequency.
Let the total output phase be
θout (t) = ω0 t + θo (t),
(3.3)
where ω0 is the free-running frequency of the VCO and θo (t) is the output total excess
phase. The total phases at the inputs to the phase detector may be represented by
θin (t) = ωref t + θref (t)
(3.4)
θo (t)
ω0
t+
,
N
N
(3.5)
θ0 (t) =
where ωref is the input reference frequency, θref (t) is the reference total excess phase,
and N is the loop division factor. For analysis purposes the reference and divided VCO
signal will be sin(θin (t)) and cos(θ0 (t)), respectively. The phase detector used for this
circuit is a mixer which multiplies the two input signals sin(θin (t)) and cos(θ0 (t)).
The multiplication will result in terms at the sum and difference of the two input
total phases
x(t) = Kd [sin(θin (t) − θ0 (t)) + sin(θin (t) + θ0 (t))],
(3.6)
where Kd is the phase detector constant and represents the linear voltage output per
unit phase difference between θin (t) and θ0 (t) with units of Volts per radian.
Many performance parameters of the PLL are influenced by the loop filter, including the PLL natural frequency ωn , the damping factor ζ and the PLL bandwidth.
The simplest loop filter consists of a capacitor; while simple in structure and analysis,
this configuration suffers from tradeoffs between settling speed, ripple on the control
voltage, phase error, stability and lock acquisition range [36]. Consider the 2-element
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
39
lowpass filter of Figure 3.3; this filter structure is used in PLL applications because
of its simple realization. For on-chip applications, the challenge of using this type of
RC loop filter is the capacitor area if narrow loop bandwidth is required. This LPF
R
+
+
Vin
C
−
Vout
−
Figure 3.3: First Order LPF
has a voltage transfer function in the frequency domain, F(s), that may be written
F (s) =
Vout
1
.
=
Vin
sCR + 1
(3.7)
In the time domain, the filter is assumed to be linear and time-invariant and acts on
the input x(t) to produce the generalized output [48]
Z t
e(t) = e0 (t) +
x(u)f (t − u)du,
t ≥ 0,
(3.8)
0
where e0 (t) is the zero-input response and f (t) is the impulse response of the filter.
Normally e0 (t) is set to zero such that e0 (t) ≡ 0 for all t, simplifying (3.8) to
Z t
e(t) =
x(u)f (t − u)du, t ≥ 0.
(3.9)
0
The input-output relation of (3.9) in the time domain can be expressed as a
differential equation of the form
am
dm x(t)
dm−1 x(t)
+
a
+ · · · + a0 x(t) =
m−1
dtm
dtm−1
dn e(t)
dn−1 e(t)
bn
+
b
+ · · · + b0 e(t)
n−1
dtn
dtn−1
(3.10)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
40
where m ≤ n. The transfer function of the circuit can be written as
F (s) =
am sm + am−1 sm−1 + · · · + a1 s + a0
.
bn sn + bn−1 sn−1 + · · · + b1 s + b0
(3.11)
An ordinary differential equation with constant coefficients such as (3.11) has a solution (3.9) where f(t) is the inverse Laplace transform of the transfer function F(s) [48].
If m < n in (3.11) then f(t) is analytic (having a derivative that exists throughout
some neighbourhood of t [49]); if m = n then f(t) is the sum of an analytic function
and a Dirac delta function.
The VCO outputs a sinusoidal signal at a frequency based on the input error
voltage e(t). Let the total output phase be rewritten as
θout (t) = (ω0 + K0 e(t))t + θo ,
(3.12)
where K0 is the VCO gain constant that gives the VCO frequency change in radians/second per unit of input voltage (rad/sec/V), and θo is the VCO total excess
phase in radians. The VCO output frequency may be defined in terms of the total
output phase θout (t) as
dθout
= ω0 + K0 e(t).
dt
(3.13)
It is now possible to derive a general differential equation for the entire PLL
in terms of the two inputs to the phase detector. Using (3.13), the divided VCO
frequency input to the PD is
dθ0
ω0 K0
=
+
e(t).
dt
N
N
(3.14)
The PD output error term x(t), assuming the sum term at frequency (ωref + ω0 /N )
is rejected by the loop filter, is
x(t) = Kd [sin(θin (t) − θ0 (t))].
(3.15)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
41
The filtered error term e(t) may then be written as
Z
t
e(t) =
f (t − u)Kd [sin(θin (u) − θ0 (u))]du.
(3.16)
0
Finally, substituting (3.16) in (3.14), the general differential equation for the PLL
may be written as
dθ0 (t)
ω0 K0
=
+
dt
N
N
Z
t
f (t − u)Kd sin[θin (u) − θ0 (u)]du.
(3.17)
0
Defining the phase error to be
φ(t) = θin (t) − θ0 (t),
(3.18)
the derivative of (3.18) using (3.17) may be written as
dφ
dθin (t) ω0 K0
=
−
−
dt
dt
N
N
Z
t
f (t − u)Kd sin φ(u)du.
(3.19)
0
Let the 2 total phases at the input to the PD be defined relative to the VCO
free-running frequency ω0 divided by N:
ω0
t
N
ω0
θ2 (t) = θ0 (t) − t,
N
θ1 (t) = θin (t) −
(3.20)
(3.21)
where θ1 (t) is the reference relative total phase, and θ2 (t) is the VCO relative total
phase divided by N. It is now possible to simplify (3.19) to
dφ
dθ1 (t) K0
=
−
dt
dt
N
Z
t
f (t − u)Kd sin φ(u)du,
(3.22)
0
where
φ(t) = θ1 (t) − θ2 (t).
Figure 3.4 shows a revised block diagram to reflect equation (3.22).
(3.23)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
42
PD
θ 1 (t)
+
φ (t)
x(t)
sin( )
KD
e(t)
Filter
K0
dθ out (t)
dt
t
θ out (t)
0
−
θ 2 (t)
Divide−by−N
1
N
Figure 3.4: Modified Block Diagram, Frequency-Multiplying PLL
Taking the general differential equation representation of the filter transfer function from (3.10), (3.22) may be rewritten in general form as
Z
K0 t
dφ dθ1 (t)
−
= −
f (t − u)Kd sin φ(u)du
dt
dt
N 0
d
d
dφ dθ1 (t)
b0 + b1 + · · · + bn n
−
dt
dt
dt
dt
d
Kd K0
d
= −
a0 + a1 + · · · + am m sin φ(t).
N
dt
dt
(3.24)
Let the loop filter of Fig. 3.3 now be considered. A comparison of the transfer
function F(s) in (3.7) with the general transfer function of (3.11) shows that F(s) has
the coefficients a0 = 1, b0 = 1 and b1 = RC. Using these values in (3.24) results in
d
dφ dθ1 (t)
Kd K0
1 + RC
−
= −
(1) sin φ(t)
dt
dt
dt
N
d2 φ dφ(t) K0 Kd
dθ1 (t)
d2 θ1 (t)
RC 2 +
+
sin φ(t) −
= RC
.
(3.25)
dt
dt
N
dt
dt2
Using (3.4) and (3.20), (3.25) may be simplified to the following second order
non-linear differential equation
d2 φ(t)
1 dφ(t) ω0 K0 Kd
+
− ωref −
+
sin φ(t) = 0.
2
dt
RC
dt
N
N RC
(3.26)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
43
The differential equation of (3.26) may be rewritten in a more familiar format using
the PLL natural frequency ωn and the damping factor ζ as
ω0 d2 φ(t)
dφ(t) − ωref −
+ ωn2 sin φ(t) = 0.
+ 2ζωn
dt2
dt
N
(3.27)
where
r
K0 Kd
ωn =
=
N
CR
r
1 N ωL
ζ =
.
2 K0 Kd
r
K0 Kd ωL
,
N
(3.28)
(3.29)
and ωL = 1/CR is the 3-dB bandwidth of the loop filter.
Assume that ωref − ω0 /N = 0. Letting x = φ(t), y = dx/dt and rewriting gives
the system of simultaneous differential equations [50]
dx
= y,
dt
dy
= −2ζωn y − ωn2 sin x.
dt
(3.30)
For the set of equations of (3.30) the point x = 0, y = 0 is a critical point where
dx/dt and dy/dt are equal to zero.
Let the simultaneous equations be of the general form [50]
dx
= F (x, y)
dt
dy
= G(x, y),
dt
(3.31)
where F (x, y) and G(x, y) are continuous and have continuous partial derivatives in
some domain in the x–y plane that contains the critical point. It is assumed that the
identified critical point is isolated; this means that within some circle about the critical
point there are no other critical points. It is assumed that in the neighbourhood of
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
44
the critical point the functions F and G have the form
F (x, y) = ax + by + F1 (x, y),
G(x, y) = cx + dy + G1 (x, y),
(3.32)
where a, b, c, and d are coefficients and ad − bc 6= 0. The functions F1 and G1 must
be continuous, have continuous first partial derivatives, and be small such that
G1 (x, y)
F1 (x, y)
→ 0,
→ 0 as r → 0,
r
r
(3.33)
1
where the polar coordinates are defined as r = (x2 + y 2 ) 2 and tan θ = y/x.
Let the set of equations of (3.30) be rewritten as follows:
dx
= 0x + y,
dt
dy
= −ωn2 x − 2ζωn y − ωn2 (sin x − x).
dt
(3.34)
Comparing terms of (3.34) with (3.32), F1 (x, y) = 0, G1 (x, y) = −ωn2 (sin x − x), and
ad − bc = ωn2 6= 0. To satisfy the last requirement of (3.33) a series expansion is
performed on G1 (x, y) to give
G1 (x, y) =
−ωn2
x3 x5
x−
+
··· − x
3!
5!
=
−ωn2
x3 x5
− +
···
3!
5!
.
(3.35)
From (3.35) for x very small, sin x − x ≈ −x3 /3! = −(r3 cos3 θ)/3! and hence
G1 (x, y)/r → 0 as r → 0. The system of (3.30) is said to be almost linear in
the neighbourhood of the critical point x = 0, y = 0, i.e., it approximates a linear
system.
The stability of the critical point (0, 0) now must be determined. Because the
system is almost linear, the stability analysis used for linear systems is applicable.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
45
For linear systems with differential equations
dx
= ax + by,
dt
dy
= cx + dy,
dt
(3.36)
with ad − bc 6= 0 the critical point is asymptotically stable if the roots r1 6= 0, r2 6= 0
of the characteristic equation
r2 − (a + d)r + ad − bc = 0
(3.37)
are real and negative or have negative real parts. The linear system for the case in
question may be derived from (3.34) as
dx
= 0x + y,
dt
dy
= −ωn2 x − 2ζωn y.
dt
(3.38)
Looking at (3.38) and selecting the appropriate coefficients, (3.37) may be written as
r2 + 2ζωn r + ωn2 = 0.
(3.39)
The roots for this particular characteristic equation are
r1,2
p
ζ 2 − 1 (real roots)
p
= −ζωn ± jωn 1 − ζ 2 (imaginary roots)
r1,2 = −ζωn ± ωn
(3.40)
For the developed PLL the argument of the square root is imaginary and the real part
of the roots is negative; therefore, the critical point (0, 0) is asymptotically stable.
This means that for initial starting conditions within a region of asymptotic stability
over time the solution of the non-linear differential equation (3.26) will converge to
the stable critical point. For the PLL, this corresponds to a ‘locked’ state.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
46
As observed, the system is nearly linear; the corresponding linear differential equation may be written from (3.27) as
d2 φ(t)
dφ(t)
+ ωn2 φ(t) = 0
+
2ζω
n
dt2
dt
(3.41)
where for simplicity ωref = ωo /N . It is possible to obtain a solution for φ(t) for this
second order linear DE, assuming the PLL is initially in a locked state. Using the
imaginary roots of (3.40), the general solution is of the form
p
p
φ(t) = C1 e−ζωn t cos ωn 1 − ζ 2 t + C2 e−ζωn t sin ωn 1 − ζ 2 t .
(3.42)
For initial conditions φ(0) = ∆θ, dφ(0)/dt = 0 where ∆θ is a step change in phase at
time t = 0, the exact solution is
#
"
p
p
ζ
φ(t) = ∆θu(t)e−ζωn t cos ωn 1 − ζ 2 t + p
sin ωn 1 − ζ 2 t .
2
1−ζ
(3.43)
The expression for the output change in phase ∆θo (t) may then be written as
"
"
##
p
p
ζ
−ζωn t
θo (t) = N 1 − e
cos ωn 1 − ζ 2 t + p
∆θu(t),
sin ωn 1 − ζ 2 t
1 − ζ2
(3.44)
where ζ < 1. This expression for the output phase change has several notable characteristics:
1. The PLL output does not change immediately. As time increases (t → large),
the output phase change approaches N times the input phase change, indicating
that the output phase is tracking the input (provided ωref ≈ ω0 /N ),
2. The final output phase change is a factor of N larger than the input phase
change; this is a result of the N division factor in the loop,
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
47
3. The response shows a damped sinusoidal ringing dependent upon the loop parameters.
The behaviour of the PLL under startup and transient conditions such as a step
shift in either phase or frequency may now be considered. For small arguments of φ(t)
the solution to the linear equation of (3.41) is (3.43). The solution to the non-linear
equation of (3.26) may be determined by using an analog computer solution of (3.22).
A phase plane method is used to determine the solution of the non-linear differential equation of (3.22) [48]. The relative phase error φ = φ(t) is plotted on the
ordinate axis and the relative frequency error φ̇ = dφ(t)/dt is plotted on the coordinate axis. The behaviour of the solution is periodic in each strip of width 2π, i.e.,
the solution is the same for 2nπ ± π, n = 0, 1, 2, . . . . For given initial conditions of
φ = φ(0) and φ̇ = φ̇(0), the solution to the equation over time will trace out several
potential trajectories:
1. Trajectories where phase and frequency errors decay immediately towards the
critical point of asymptotic stability (phase lock without cycle slip),
2. Trajectories where for large frequency errors (φ̇) a periodic variation with small
decay over each phase cycle of 2π is observed; the trajectory eventually enters
a region of asymptotic stability and decays to the critical point of asymptotic
stability (phase lock with cycle slip)
3. Trajectories that diverge (no phase lock).
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
3.2.2
48
Frequency Domain Analysis
It is also useful to analyze the performance of the PLL in the frequency domain. The
linear model for the PLL considered is shown in Fig. 3.2(b), where θin (s) and θ0 (s)
denote the PD input phases in the frequency domain (θ(s) = Laplace transform of
θ(t), L{θ(t)}), X(s) is the phase detector output error voltage, F(s) is the transfer
function of the loop filter, E(s) is the filtered error voltage, K0 /s is the Laplace transform of the VCO transfer function, and θout (s) is the output phase in the frequency
domain.
For the PLL of Figure 3.2(b) let the filter function F(s) be represented by the
transfer function of the one pole LPF of Figure 3.3. Comparing Figures 3.1 and
3.2(b), the forward gain A(s) will be (Kd ∗
1
1+sCR
∗
K0
)
s
and the reverse gain B(s)
will be the factor 1/N . The open loop gain A(s)B(s) of the PLL of Figure 3.2(b) is
therefore
A(s)B(s) = Kd ∗
1
K0 1
∗
∗ .
1 + sCR
s
N
(3.45)
The pole locations for A(s)B(s) are at s=0 and s = −1/RC; note that there is only
one pole at s = 0. The closed loop transfer function for this PLL when referenced to
the input is
H(s)|closed,I/P =
=
θout (s)
A(s)
=
θin (s)
1 + A(s)B(s)
Kd K0
CR
s2 +
1
s
CR
+
Kd K0 1
N CR
.
(3.46)
There are a total of 2 poles in the closed loop system transfer function. This representation is therefore a Type I (a single pole at s = 0), second order (a total of two
poles in the closed loop system transfer function) PLL.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
49
The PLL input-to-output transfer function H(s)|closed,I/P is an important characteristic of the PLL as it defines how the system acts in the frequency domain upon a
signal injected at the input. The transfer function may be rewritten using the PLL
natural frequency ωn , damping factor ζ and loop filter 3-dB bandwidth ωL as
H(s)|closed,I/P =
N ωn2
K0 Kd ωL
=
.
s2 + 2ζωn s + ωn2
s2 + 2ζωn s + ωn2
(3.47)
Another closed loop transfer function considered is from the VCO itself to the
output, H(s)|closed,V CO :
1
θout (s)
=
θV CO (s)
1 + A(s)B(s)
1
s(s + CR
)
s2 + 2ζωn s
.
= 2
= 2
1
1
s + 2ζωn s + ωn2
s + CR
s + KdNK0 CR
H(s)|closed,V CO =
(3.48)
The closed-loop transfer functions of (3.47) and (3.48) will be of particular interest for
the consideration of how noise at the reference input and the VCO output contribute
to the PLL output signal when the loop is in a locked state.
3.3
Phase Noise Performance of the PLL
The input and output signals may be represented in the simplest case by the sinusoidal
waveforms
Vin (t) = sin(ωref t + θref (t))
(3.49)
Vout (t) = A cos(ω0 t + θo (t)),
(3.50)
where the terms are as defined in Section 3.2, and A is the amplitude of the output
signal. Variations in the excess phase terms θref (t) and θo (t) manifest themselves
in the frequency domain as a distribution of noise power about the carrier signal
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
50
frequency. The spectrum of noise power about the carrier as a result of variations in
the total excess phase is designated as phase noise.
Phase noise may be contributed at points within the PLL circuit where oscillator
signals are created or injected ,i.e., at the VCO and at the reference input. Figure
3.5 shows a revised linear model for the PLL that includes sources of phase noise.
The input excess phase θref (s), the excess VCO phase θV CO (s), and the excess output
phase θout (s) are identified. the double-sided phase noise spectrum Sφ (s) is written
θ VCO (s)
PD
θ in(s)
+
Σ
LPF
X(s)
KD
VCO
E(s)
F(s)
K0
s
+
+
Σ
θ out (s)
−
Divide−by−N
1
N
Figure 3.5: PLL Linear Model
as
Sφ (s) =
θ2 (s)
dBc/Hz;
Carrier Power
(3.51)
The single-sided phase noise spectrum L(f ), commonly measured or modeled for
devices, is the double-sided phase noise spectrum divided by two, and is referenced
to an offset frequency f in Hz instead of the complex radian frequency s.
The effect of different phase noise sources in the PLL on the output signal is
dependent upon where the phase noise source is located within the PLL, and the
closed-loop transfer function from the phase noise source to the output. Equations
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
51
(3.46) and (3.48) demonstrate the different phase noise transfer characteristics of this
PLL depending on the location of the phase noise sources. For phase noise at the
reference input, the transfer function H(s)|closed,I/P is lowpass in nature. Phase noise
injected at the VCO is operated upon by a highpass transfer function, H(s)|closed,V CO .
The divider factor N in the PLL has a large effect on the closed loop transfer
function of equation (3.46). For low offset frequencies the magnitude of H(s)|closed,I/P
is
lim H(s)|closed,I/P = N,
s→0
(3.52)
implying a direct multiplication of input phase noise by N. The output single-sided
phase noise spectrum Lout (∆ω) at a carrier offset frequency ∆ω is a function of the
single-sided phase noise spectrum of the reference signal Lref (∆ω) and the multiplication factor N, and may be represented as
Lout (∆ω) = N 2 · Lref (∆ω).
(3.53)
High multiplication factors will result in a higher output single-sided phase noise
spectrum because of the N 2 factor.
To minimize in-band phase noise contribution from the reference, it is desirable
to have as low a loop division factor as possible. A high value of N may also limit the
achievable unity gain bandwidth (defined as the frequency at which |A(s)B(s)| = 1),
spurious rejection of H(s)|closed,I/P and phase margin (the difference between loop
phase ∠[A(s)B(s)] and −180o at the frequency where |A(s)B(s)| = 1, which is an
indicator of the stability of the PLL).
The total phase noise at the PLL output will be a linear addition of the individual
sources after being acted upon by the appropriate closed loop transfer function. For
the purposes of linear analysis, noise sources are treated as mutually independent
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
52
and uncorrelated due to being either independent phase noise sources in the case of
oscillators or thermal noise characterized by a zero-mean wideband white Gaussian
process.
3.4
Locking Bandwidth
Locking bandwidth may be defined as the frequency range over which the loop acquires phase lock without cycle slips [47]. The determination of PLL locking bandwidth is a challenging undertaking. The use of phase plane analysis as described in
[48] graphically identifies (based on initial conditions for frequency and phase) regions
of locking with and without cycle slip as well as regions of divergence but does not
present an analytical solution to the sinuous boundary between the various regions.
Approximations are commonly used for higher order PLLs to obtain an estimate of
the locking bandwidth.
Consider the voltage signal fed to the VCO in response to an input step change
in frequency ∆ωstep . The VCO control signal e will have a magnitude of [51]
e(t) = Kd |F (∆ωstep )| sin(∆ωstep t),
(3.54)
where F (∆ω) is the LPF response at radian offset frequency ∆ω. This AC signal
will frequency modulate the VCO output. For the case where the peak frequency
modulation is exactly the same as the step change in frequency ∆ωstep , the PLL
will lock within one single-beat note between the reference and output frequencies.
For this case the maximum frequency difference ∆ωstep is identical to the maximum
lock frequency ∆ωLock . For this particular case the maximum lock frequency may be
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
53
obtained from the non-linear equation
∆ωLock = ±
K0 K d
|F (∆ωLock )| .
N
(3.55)
The locking bandwidth, BWlock , is twice the maximum lock frequency. While (3.55)
does not account for all initial conditions as a phase plane analysis does, it does give
a rough estimate of the magnitude of the locking range.
3.5
Tracking Bandwidth
The tracking bandwidth may be considered as the input frequency range over which
the PLL will hold lock [47]. The tracking bandwidth of the PLL may be determined
by examining the error term φ(t) = θin (t) − θ0 (t). The transfer function from θin to
φ may be written in the frequency domain as
E(s) =
φ(s)
=
θin (s)
1+
Kd K0
N
1
· 1s ·
1
1+sCR
=
s
s+
Kd K0
N
·
1
1+sCR
.
(3.56)
The steady state phase error may be determined by using the final value theorem of
Laplace transforms [47], which states that
lim e(t) = lim sE(s)
t→∞
(3.57)
s→0
where E(s) = L{e(t)}. Applying this theorem to (3.56) gives
s2 θin (s)
.
1
s→0 s + Kd K0 ·
N
1+sCR
lim φ(t) = lim sE(s)θin (s) = lim
t→∞
s→0
(3.58)
For a step input in frequency of ∆ωstep , θin (t) = ∆ωstep t which is ∆ωstep /s2 in the
frequency domain. Substituting into (3.58) gives the linear steady state phase error
lim φ(t) = lim
t→∞
s→0
s+
∆ωstep
Kd K0
1
· 1+sCR
N
=
∆ωstep
Kd K0
N
.
(3.59)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
54
The steady state phase error φ(t) for an input step in frequency is expected, as
the VCO must be shifted to a new frequency to maintain phase lock. The nonlinear steady state response for a sinusoidal phase detector (such as a mixer) is [47]
sin φ(t) = ∆ωstep /(Kd K0 /N ). As the maximum value for sin φ(t) is ±1, the maximum
tracking range ∆ωtrack of the PLL may therefore be defined as
∆ωtrack = ±
Kd K0
,
N
(3.60)
where ∆ωtrack is centred about the input reference frequency ωref .
Consider the ratio of the tracking bandwidth to the locking bandwidth, Eq. (3.60)
divided by Eq. (3.55).
∆ωtrack
1
=±
∆ωLock
|F (∆ωLock )|
(3.61)
If the lowpass filter response is of the form of (3.7), Eq. (3.61) may be rewritten as
s
q
∆ω 2
∆ωtrack
= ± 1 + ∆ωL2 C 2 R2 = ± 1 + 2 L .
(3.62)
∆ωLock
ωLP F
For ∆ωLock /ωLP F >> 1 the tracking bandwidth will be larger then the locking bandwidth. This means that although the PLL will track over a larger frequency range,
the magnitude of the frequency change will be limited by the locking bandwidth; if a
frequency step is applied that is outside of the PLL locking range, the PLL will lose
lock.
3.6
Selection of PLL Loop Constants
The decision was made at the start of the research to develop the PLL in a CMOS
0.18-µm process based on its ready availability, familiarity within the Very High Speed
Circuits research group, and cost. The PLL was a subject of interest because of its
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
55
potential applications in signal generation, modulation and demodulation. The PLL
clock multiplier also presented the opportunity to study a wide range of components
that could be used in a variety of designs, such as VCOs, divider structures and
phase detectors. The definition of the PLL performance parameters and selection of
the various gain constants was based to a large extent on the process selected for
fabrication and the sub-circuits designed in the initial research effort.
The output frequency of 26 GHz was selected based on previous experience within
the research group in the design of high frequency VCOs and the desire to develop
a high frequency PLL. A total division factor of 4 was selected based on published
results [6] that showed the phase noise benefit of a low multiplication factor and the
consideration of using a wider loop bandwidth.
The values for VCO gain K0 and phase detector gain Kd were determined from preliminary design efforts [52], [53]. The initial VCO displayed a resonant frequency of 38
GHz due to the lack of an analytical model or measured data for the AMOS varactors
used. A redesign of the VCO using measured AMOS varactor s-parameters resulted
in a 26 GHz resonant frequency, and a simulated K0 of 0.785 GHz/V (4.932x109
rad/V). The phase detector gain Kd was calculated to be 1.158 V/rad, based on the
simulated response of the designed circuit.
The selection of the lowpass filter has an important effect on the characteristics of
the PLL, as shown in Sections 3.2.1 and 3.2.2. A one pole lowpass filter with transfer
function as per (3.7) was selected based on ease of fabrication and and loop analysis
purposes. The resulting frequency domain linear equations for open- and closed-loop
gain transfer functions take the forms of (3.45) and (3.46), respectively. For an open
loop unity gain bandwidth of 2.34 MHz the RC time constant of the lowpass filter was
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
56
determined to be 6.60x10−6 sec. A tradeoff in the integrated circuit layout (resistor
length versus capacitor area) led to the setting of the lowpass R and C to 36.2 kΩ
and 182.4 pF, respectively.
3.6.1
Time Domain
The values selected for the PLL gains K0 and Kd , the division factor N and the lowpass
filter components were used to calculate the factors ωn and ζ. For the design values,
the natural frequency ωn and damping factor ζ are 14.703 Mrad/sec and 0.0052 when
calculated using (3.28) and (3.29), respectively.
It should be noted at this point that the PLL loop factors ωn and ζ were calculated
after setting the open loop bandwidth. A limitation of the one-pole lowpass filter
selected was an inability to set ωn and ζ independently. This resulted in the very low
value of ζ for the PLL, which may have contributed to simulation difficulties described
in Ch. 5. It is strongly advised that a lowpass filter is used that allows independent
selection of both ωn and ζ. The values for ωn and ζ should also be selected before
the loop filter is designed, leading to a reduction/elimination of ringing (larger value
of ζ) and an improvement in the phase noise transfer functions (selection of ωn to
better match the phase noise contributions from the reference and the VCO).
The values of ζ and ωn will have several important effects on the behaviour of the
PLL:
1. Locking Bandwidth: The PLL locking bandwidth will be narrow, as the loop
LPF has been set for a 2.34 MHz open-loop unity gain,
2. Locking Time: The time for the PLL to settle is exponentially dependent on
ζ and ωn , as shown in (3.44). The time constant for (3.44) is τ = 1/(ζ ∗ ωn ),
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
57
which has a value of 13.1µs. If 5 time constants are assumed for the system
to reach its steady state (corresponding to 99.3% of the input phase step), the
system will take 66µs to settle,
3. Ringing Frequency: In a transient state, the loop will display a ringing frequency
p
of ωn 1 − ζ 2 rad/sec.
It should be noted that capacitor values in the tens of picofarads are challenging
to realize in CMOS integrated circuits because of the large chip area required. Additionally, limitations on the maximum size of MIM capacitors for design rule checking
(DRC) requires many smaller capacitors in parallel to generate the large specified
value. From a practical point of view, capacitor values limit the minimum value of
the open loop unity gain bandwidth.
A phase plane investigation was undertaken for the designed PLL to gain a better understanding of the importance of the initial conditions. For the purposes of
this investigation an analog solution was determined by using a MATLAB Simulink
representation of (3.22) and Fig. 3.4.
Figure 3.6 shows two phase plane trajectories associated with the PLL of Figure
3.4 that display the concept of phase lock without cycle slip and no phase lock. For the
purpose of the analysis, the loop design constants and component values discussed
in Section 3.6 were used. The phase difference between the reference and divided
VCO signals was set to 0 radians; an additional phase offset of 0.7 rad was included
for non-ideal phase detector performance (discussed in Section 4.4). The contours
had a total initial phase error φ(0) of 0.7 radians; the “Phase Lock” curve had an
initial frequency offset of φ̇(0) = (2π · 4.37x106 ) rad/sec while the “No Phase Lock”
curve had an initial frequency offset of φ̇(0) = (2π · 4.38x106 ) rad/sec. The initial
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
58
4e7
3e7
d φ/ dt (rad/sec)
2e7
1e7
(0,0)
0
−1e7
−2e7
No Phase Lock
Phase Lock
−3e7
−4e7
−4
0
4
8
12
φ (rad)
16
20
24
28
Figure 3.6: Phase Plane Trajectories: No Phase Lock and Phase Lock
frequency offsets were selected to show the importance of initial conditions and how
even a relatively small difference between the two initial frequencies could result in a
loss of phase lock.
The “Phase Lock” trajectory of Fig. 3.6 immediately decays towards the critical
point at (0, 0) from its initial condition of (0.7 rad, 2π·4.37x106 rad/s). The “No Phase
Lock” trajectory initial condition of (0.7 rad, 2π · 4.38x106 rad/s) lies just outside the
boundary of asymptotic stability and diverges from potentially stable points.
The trajectory traced out for the “Phase Lock” case displays a gradual decay
towards its stable point; the first loop traversed gives an idea of the sinuous boundary
between the locked and unlocked cases dependent on initial conditions for the phase φ
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
59
and its derivative φ̇. The rate of convergence is based on the relative damping factor ζ
of the PLL, which in turn is a function of the lowpass filter R and C values, the VCO
and PD constants K0 and Kd , and the division factor N. For the design presented
the damping factor ζ is quite small; the PLL response is extremely under-damped,
resulting in a lengthy period for the frequency-phase contours to reach the steadystate condition. The PLL is meant to be a frequency multiplier used to provide a
local oscillator signal to a front end radio receiver. As such, the longer settling time
required for the circuit is acceptable.
3.6.2
Frequency Domain
Linear closed-loop noise transfer functions for the implemented PLL were calculated
using the implemented PLL component values and constants identified in Section
3.6. Transfer functions have been plotted using the component design values for
the input reference θin (s), VCO control voltage reference E(s), and VCO-referenced
θV CO (s) phase noise. Figure 3.7 shows the associated closed-loop transfer functions
vs. frequency.
The transfer function for input-referenced phase noise, H(s)|closed,I/P , shown by
the ‘θin (s) to θout (s)’ curve of Figure 3.7 displays a lowpass behaviour with a multiplying factor of 4 (12.04 dB) from the loop divider circuit. The transfer function
for the VCO-referenced phase noise, H(s)|closed,V CO , (‘θV CO (s) to θout (s)’) displays a
highpass characteristic, implying that the phase noise at offsets significantly greater
than the PLL loop bandwidth is dominated by the phase noise of the VCO.
The transfer function from the VCO control voltage (‘E(s) to θout (s)’ ) displays
significant gain peaking for offset frequencies between 20 kHz and 80 MHz due to the
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
60
90
×
50
Mag. (dB)
10
−30
−70
−110
−150
×
×
×
×
×
×
×
× ×
×
+
×
× ×
×
×
×
+
⊕
×
×
+
+
× + + + + + + +
+ ×
+ ×
+ ×
+ +
+ +
+ ×
+ ×
+ ×
+ +
× +
× ×
×
× ×
× +
× +
× +
× +
+
⊕⊕⊕⊕⊕⊕⊕⊕
⊕
+
+
⊕
+
⊕
+
⊕
+
⊕
+
⊕
+
⊕
⊕
⊕
⊕
⊕
⊕
⊕
+ θ in (s) to θ out(s)
⊕⊕
⊕
⊕
× E(s) to θ (s)
⊕
out
⊕⊕
⊕
⊕
to
θ
(s)
θ out(s)
⊕
VCO
⊕⊕
⊕
⊕⊕
1
10
2
10
3
10
4
5
10
10
Freq. (Hz)
6
10
7
10
8
10
Figure 3.7: PLL Closed Loop Transfer Functions - Type I, 2nd Order
low value of the damping factor ζ. In this frequency range, any noise or spurious
signal that appears at the VCO control line input will be multiplied and appear at
the VCO output. The magnitude of the transfer function means that noise within the
identified frequencies at the the VCO control inputs must be minimized. An alternate
selection of the loop lowpass filter 3-dB rolloff frequency would help to alleviate the
peaking, but would have implications on the closed loop transfer function. The design
of the VCO addresses this susceptibility by using a differential varactor structure to
lessen the effect of noise at E(s); this will be discussed in greater detail in Chapter 4.
The overall PLL output phase noise response is composed of contributions from
various points within the PLL: the reference signal input, the VCO control lines and
the VCO itself. The individual contribution to the overall PLL output phase noise
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
61
will be governed by the magnitude of each noise source and the individual associated
noise transfer function. In Chapter 5 the system phase noise based on the individual
components will be more closely examined.
The desirable performance of the PLL may be deduced by considering the transfer
functions of Fig. 3.7. The total summed phase noise at low offset frequencies from the
carrier is dominated by the reference phase noise multiplied by the loop multiplication
factor N. Contributions from the PD and the Loop Divider are negligible for the
case considered because of the low loop multiplication factor. The VCO phase noise
dominates for larger frequency offsets because of the highpass nature of the closed loop
transfer function. It is therefore possible to achieve considerably lower phase noise
close to the band by using a PLL and a reference with good phase noise performance.
3.7
3.7.1
PLL Design Considerations
VCO Common Mode Noise Rejection
Low-frequency noise or interfering signals from an emitting source can be coupled
into the receptor integrated circuit by many means. These include radiation coupling
(e.g., coupling of the natural and similar electromagnetic environment to the receptor
such as a power line or by proximity to other circuits), conduction coupling (e.g.,
interference carried by power supply lines when the interference emitter and receptor
operate from the same power supply line) or a combination of both (e.g., radiation
from power transmission lines or noisy assemblies coupling into the power cables
or on-chip control lines) [54]. Of particular concern for the VCO are the following
coupling paths:
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
62
1. Coupling of noise or interfering signals onto the VCO control lines (VCOctrl pos,
VCOctrl neg),
2. Coupling of noise or interfering signals onto the VCO voltage supply line (VDD ).
The mode of the coupled interferer is also of importance. Common-mode (CM)
interferences are defined as the unwanted electrical potential differences between any
(or all) current- or voltage-carrying conductors and the reference ground. Differentialmode (DM) interferences are defined as the unwanted potential differences between
any two current-carrying conductors [54].
To examine the effects of CM interference on the VCO consider the various varactor structures of Figure 3.8. The individual varactor element capacitance of Fig.
3.8(a) is dependent on the difference between the control voltage Vctrl on one terminal and the voltage vo on the other terminal (Vctrl − vo ). In the VCO which is not
designed for suppression of common mode interference, CM noise / interfering signals
on either the VCO control line or the the tank arms via supply voltage VDD will
result in phase noise on the VCO because of the varactor capacitance dependence on
Vctrl − vo [55]. Figure 3.9(a) shows the varactor element of Fig. 3.8(a) with common
mode noise vncm injected in addition to the control voltage Vctrl . In the presence of
injected common mode noise voltage vncm at the VCO control node, the capacitance
of the single varactor element of 3.9(a) may be represented over the range of Vctrl as
[13]
C = C0 + kv ((Vctrl + vncm ) − vo ) ,
(3.63)
where C0 is the zero bias capacitance in farads, kv is the varactor sensitivity in
farads/volt, and vncm is the injected common mode noise voltage in volts.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
63
Vctrl
vo
C
(a)
Vctrl
vo−
vo+
C+
C−
(b)
V+ctrl
C+1
C−1
vo−
vo+
C+2
C−2
V−ctrl
(c)
Figure 3.8: Varactor circuits (a) Individual varactor element, (b) Singly-tuned subassembly, (c) Differentially-tuned assembly
Circuits using singly-tuned varactor sub-assemblies similar to Fig. 3.8(b) are
susceptible to CM noise. For the singly-tuned varactor sub-assembly of Fig. 3.9(b)
with common mode noise injected at the VCO control node the capacitances between
Vctrl and vo+ and Vctrl and vo− are
C + = C0 + kv (Vctrl + vncm ) − vo+
C − = C0 + kv (Vctrl + vncm ) − vo− .
(3.64)
(3.65)
The total capacitance between vo+ and vo− is
C +C −
C0 kv
=
+
((Vctrl + vncm ) − vo ) ,
C= +
C + C−
2
2
(3.66)
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
64
C
vo
+
+
−+
vncm
Vctrl
−
−
(a)
v+
o
C+
C−
+
−
+
v−
o
vncm
Vctrl
−
(b)
Figure 3.9: Varactor circuits with injected common mode noise (a) Individual varactor
element, (b) Singly-tuned sub-assembly
where vo+ = vo− = vo . Note that the common mode noise voltage vncm modulates the
varactor capacitance. Because the resonant frequency of the VCO is dependent on the
varactor capacitance the common mode noise voltage is transformed to a variation
in VCO resonant frequency that is evident as phase noise at the VCO output. Both
the single varactor element and the singly-tuned varactor structure capacitances as
shown in (3.63) and (3.66) display this capacitance susceptibility to common mode
noise.
The differentially-tuned assembly of Fig. 3.8(c) is used to minimize low frequency
common-mode noise on either the VCO control lines or VDD . Under the conditions of
varactor symmetry (same zero bias capacitance, opposite sign capacitance sensitivity
for C1 and C2 ) and voltages vo+ = vo− = vo this assembly will minimize contributions
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
65
to phase noise from common-mode sources.
The circuit of Figure 3.10 shows the differentially-tuned varactor assembly of Fig.
3.8(c) with common mode noise voltage injected at the control nodes. The individual
−
+
−
+
C+1
V+ctrl
vncm
C1−
vo−
vo+
C+2
+
C−2
+
−
vncm
V−ctrl
−
Figure 3.10: Differentially-tuned varactor with injected common mode noise
capacitor values may be written as
+
C1+ = C0,1 + kv1 (Vctrl
+ vncm ) − vo+
(3.67)
+
+ vncm ) − vo−
C1− = C0,1 + kv1 (Vctrl
(3.68)
−
C2+ = C0,2 + kv2 (Vctrl
+ vncm ) − vo+
(3.69)
−
C2− = C0,2 + kv2 (Vctrl
+ vncm ) − vo− ,
(3.70)
where C0,1 , C0,2 are the zero bias capacitances under the condition of no injected
noise and kv1 and kv2 are the capacitor sensitivities in farads/volt. The total capacitance between Vctrl and vo+ will be C + = C1+ + C2+ ; similarly, the total capacitance
between Vctrl and vo− will be C − = C1− + C2− . Assume that the varactors are perfectly
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
66
symmetrical (kv2 = −kv1 and C0,1 = C0,2 = C0 ) and that vo+ = vo− = vo . Let the
+
−
differential control voltages Vctrl
and Vctrl
be equally and oppositely offset from the
+
−
+
−
reference voltage vo , i.e. |Vctrl
− vo+ | = |Vctrl
− vo+ | = |Vctrl
− vo− | = |Vctrl
− vo− |. The
expressions for the capacitances C + , C − under these conditions may then be written
as
C + = 2C0 + kv Vctrldif f
(3.71)
C − = 2C0 + kv Vctrldif f
(3.72)
+
−
where Vctrldif f = Vctrl
− Vctrl
. There are no vncm terms in either (3.71) or (3.72),
demonstrating that the common mode noise has been rejected. The total series
capacitance for the differentially-tuned varactor assembly is
Ctotal = C0 + kv
Vctrldif f
.
2
(3.73)
If the differential structure of Fig. (3.10) is used with varactor constants kv1 and kv2
that have opposite signs but are not of the same magnitude (i.e., |kv1 | =
6 |kv2 |) the
equations for C + and C − will be as follows:
Vctrldif f
+ (kv1 + kv2 )vncm
2
Vctrldif f
C − = 2C0 + (kv1 − kv2 )
+ (kv1 + kv2 )vncm .
2
C + = 2C0 + (kv1 − kv2 )
(3.74)
(3.75)
The gain magnitude of the common mode noise for this case will be |kv1 + kv2 |.
3.7.2
VCO Phase Noise
Linear Time Variant (LTV) Model
A consideration of how phase noise is generated in a VCO and its associated response
in the frequency domain is useful when considering design techniques for the VCO.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
67
In his paper [56], Leeson suggested that the phase noise L(∆ω) for a VCO could be
modeled based on a linear time invariant model (i.e., no time dependence) as [57]
"
(
2 # )
∆ω1/f 3
ω0
2F kT
· 1+
· 1+
,
(3.76)
L(∆ω) = 10 · log
Ps
2QL ∆ω
|∆ω|
where F is an empirical parameter (excess noise number), k is Boltzmann’s constant,
T is absolute temperature, Ps is the average power dissipated in the resistive part of
the tank, ω0 is the oscillation frequency, QL is the loaded Q of the tank, ∆ω is the
offset from the carrier, and ∆ω1/f 3 is the frequency of the corner between the 1/f 3
and 1/f 2 regions. Figure 3.11 shows a typical phase noise response L(∆ω) versus the
offset frequency from the carrier ∆ω.
L(∆ω)
1
f3
1
f2
∆ω1
∆ω
f3
Figure 3.11: Typical oscillator phase noise versus offset frequency
Hajimiri and Lee [57] observed that there was a dependence on time of the VCO
output signal to an input current impulse. They proposed a dimensionless, frequencyand amplitude-independent periodic function with period 2π which describes how
much phase shift results from applying a unit impulse at time t = τ : the impulse
sensitivity function (ISF), Γ(ω0 τ ).
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
68
The authors argued that phase noise in the 1/f 2 and 1/f 3 regions could be represented respectively as
Γ2rms i2n /∆f
·
2
qmax
2∆ω 2
L{∆ω} = 10 · log
!
(1/f 2 region)
(3.77)
and
L{∆ω} = 10 · log
c20
2
qmax
i2 /∆f ω1/f
· n 2 ·
8∆ω
∆ω
!
(1/f 3 region),
(3.78)
where Γrms is the root mean square (rms) value of the impulse sensitivity function,
i2n /∆f is the input noise current white power spectral density, c0 is the DC coefficient
of the Fourier series expansion of the ISF and ω1/f is the device noise 1/f corner
frequency.
The LTV model of Hajimiri and Lee has design implications for reduction of
oscillator phase noise:
1. Increasing signal charge displacement qmax (and therefore voltage) across the
capacitor,
2. Noise power around integer multiples of the oscillation frequency has a more
significant effect on close-in phase noise that at other frequencies,
3. Minimization of the DC value of the effective ISF will reduce noise in the 1/f 3
region by shifting the 1/f 3 corner frequency.
The voltage across the LC-tank may be maximized by making the inductor as
large as possible and the capacitor relatively small. A recommended design criterion
is to use only the minimum amount of varactor capacitance needed for the required
tuning range [58].
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
69
The selection of varactor structure will also affect the phase noise of the VCO. Two
types of varactors suitable for integrated circuits are commonly supplied by foundries;
the AMOS varactor of Fig. 4.3 and the junction varactor. A comparison of quality
factors for a 0.18-µm process shows that the AMOS varactor exhibits higher Q-factor
and improved tuning ratio versus the junction varactor [59]. Both AMOS and junction
varactors showed strong Q-factor dependence on gate width Wg , emphasizing the
need for shorter device widths to maximize device quality factor. Analysis on AMOS
varactor physical layout in a CMOS 0.18-µm process has also indicated a quality
factor dependency on proximity of ground contacts to the varactor well and on the
size of the well [60], both of which are related to substrate modeling. The analysis
suggests that varactor Q may be improved by placing ground contacts away from
varactor wells and by minimizing the well size.
The inductor design for low phase noise applications must consider several tradeoffs. A greater inductor value will increase the peak voltage across the tank, as
observed above. For a given inductance value, narrow lines will minimize the area
of the inductor layout, resulting in less coupling to the substrate and a higher selfresonance frequency, albeit at the expense of greater series resistance and lower coil
quality factor (Q). Thicker lines will reduce the series resistance but trade off increased coil layout area with greater substrate coupling and a lower self-resonance
frequency [61]. Tapped inductors may also be used [58] to allow peak tank voltages
that exceed supply voltage limitations or device breakdown voltages at the expense
of additional circuit complexity and increased component count.
Transistor sizing and biasing contributes to phase noise performance in VCOs.
Hajimiri and Lee [9] examined the effects of various noise sources on phase noise in
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
70
a complementary LC oscillator using a tail transistor. The authors observed that
increasing the tail current improved phase noise performance by increasing the tank
voltage in the region of operation identified as current-limited regime. As current was
further increased the tank voltage became limited by the supply voltage in a region of
operation identified as voltage-limited regime resulting in large swings in tail current
and an increased current duty cycle. Phase noise contributions from the tail current
at the second harmonic of the oscillator frequency were reduced through the use of
a capacitor across the tail transistor. The authors finally identified the proper sizing
of the tail and complementary transistors to maintain symmetry and minimize the
up-conversion of 1/f noise from the transistors.
3.7.3
Frequency Dividers
The multiplication factor of the PLL clock multiplier circuit is determined by the
division factor 1/N in the feedback path of the block diagrams of Fig. 3.2. The
divider circuitry is necessary to allow the comparison of the lower frequency reference
signal with the higher frequency output signal at the phase detector.
There are two basic types of divider circuits: analog dividers and digitally-based
dividers. Analog frequency dividers include parametric dividers, regenerative dividers
and injection-locked dividers [47]. Parametric dividers are based on the non-linear
reactance of varactors. When pumped, varactors can generate power not only at the
harmonics of the pumping frequency but also at sub-harmonics [62]. The generation
of sub-harmonics is dependent upon input power and careful design and optimization
of the input and output matching networks. Regenerative dividers such as Miller
dividers [63] use feedback in a modulator loop to generate an oscillation at fractions
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
71
of the input frequency, dependent upon the order of the modulator. The Miller divider
does not oscillate in the case of no applied input signal. Injection locked frequency
dividers (ILFDs) use an oscillating circuit that under proper input frequency and
phase conditions will oscillate at fractions of the input frequency. Verma et. al. [31]
have theorized that regenerative dividers and injection locked frequency dividers are
manifestations of the same operation, and have presented theory supporting this.
The benefits of analog dividers are high operational frequency, reduced noise and
potentially lower DC power consumption. Analog frequency dividers display a limited
operational bandwidth because of the tuned or resonant elements used in the oscillator
circuits. Other limitations of analog dividers are a fixed division ratio and they are
not programmable.
Digitally-based dividers may be further divided into logic-based dividers that use
the standard CMOS logic (CMOS-Logic) family elements to realize the necessary
sequential circuits and gates, and Current Mode Logic (CML) dividers that realizes
the same sequential circuits and gates but uses analog design techniques for increased
operational frequency.
CMOS-Logic dividers use a combination of clock-driven sequential circuits such
as flip-flops; they may also contain digital logic circuits (AND, exclusive OR (XOR),
etc.). Counters are often used as divider circuits, and may be synchronous counters
(where all stages in a counter change at the same time) or ripple counters (where
the change of state propagates down the stages of the counter) [47]. Figure 3.12
shows a two-bit synchronous D-flip-flop (D-FF) counter with its associated timing
diagram [64]. The circuit is composed of 2 D flip-flops (D-FFs), two XOR gates and
one AND gate. For this circuit the D-FFs latch the D inputs on the rising edge of
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
72
XOR1
D1
D Q
Enable
Q1
Q’
AND1
XOR2
D2
X
D Q
CLK
Q2
Q’
(a)
CLK
D1
Q1
X
D2
Q2
(b)
Figure 3.12: Two-Bit Digital Counter (a) Schematic, (b) Timing Diagram
the CLK signal; they may also be configured to latch on the falling edges or even
the level of the CLK signals. When the Enable line is set HIGH, The D-FF outputs
Q1 and Q2 switch at one half and one quarter, respectively, of the frequency of the
input CLK signal, providing divide-by-two and divide-by-four outputs. CMOS-Logic
dividers display very low static power dissipation, but are limited in their operational
frequency.
CML dividers achieve much greater operational frequency by using analog design techniques to realize the required sequential elements such as flip-flops and logic
gates. The tradeoff is an increase in static power dissipation, as the circuits will
be drawing current all the time. CML static dividers can be fabricated using standard CMOS fabrication processes and as such may avoid some of the challenges
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
73
associated with analog circuits. They are readily integrated into circuits containing
other digital devices and are programmable. CML dividers show wide operational
bandwidth, allowing a broad range of operational frequencies. Limitations include a
limited high operational frequency compared to strictly analog dividers such as the
ILFD, increased static power consumption, and potentially increased noise because
of the wider operational bandwidth.
Injection Locked Frequency Divider
Two types of divider circuits were considered for the first division stage for the PLL:
a static divider composed of two cascaded D flip-flops and an injection-locked frequency divider (ILFD). Static flip-flop based dividers have been reported at frequencies greater than 26 GHz [26], [29], using more advanced CMOS fabrication processes
(such as 120 nm or 90 nm) to achieve the required operational frequencies. Static
dividers using novel high-speed latch designs in CMOS 0.18-µm processes have been
reported at up to 40 GHz [27], [28] but require more complex biasing circuitry. An
inductively-loaded source-coupled logic divider has been reported at 24 GHz using a
CMOS 0.18-µm process [7] that required stacking of the VCO and divider to minimize
voltage drop.
The injection locked frequency divider (ILFD) is a circuit which provides a divideby-M function for on-chip applications. The ILFD uses a tuned oscillator core resonating at a free-running frequency ω0 . Under proper phase and magnitude conditions,
when an input signal at frequency M ω0 is injected the oscillator will output a signal
at (1/M) times the input frequency. For the ILFD used in this research, M has a
value of 2.
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
74
Injection-locked oscillators used as dividers have several advantages over flip-flop
based dividers. They generally consume less power than current mode logic dividers
due to the tuned nature of the circuit, and they are capable of working at higher frequencies. One disadvantage is a more limited input locking range than for static dividers. This can be compensated for by adding additional capacitor banks to increase
the tuning range of the ILFD [33]. ILFD circuits have been reported at frequencies
in excess of 50 GHz using a 0.18-µm CMOS process [65]. An attractive consideration
for the selection of the injection-locked frequency divider was the existing design of
the VCO of Section 4.2; re-use of the neg-gm core and biasing circuitry for the ILFD
simplified the initial simulation and layout and reduced development risk. Based on
its high frequency performance capability and the desire to minimize development
risk by re-using an existing VCO design the ILFD was selected for the first-stage
divider in the PLL.
An oscillator may be injection-locked by injecting the locking signal at various
points within the circuit. ILFD circuits have been reported where the locking signal
has been injected at the tail transistor input Vtail , as shown in Fig. 3.13 [4] [66].
Other reported injection points include at the common mode between the LC-tank
tuning varactors via a tuned circuit [65] and directly across the oscillator LC tank
via switches [33].
The tail-injected ILFD circuit of Fig. 3.13 has a common source current that
displays a frequency component at twice the output frequency of the oscillator, making
it an obvious choice for injection of the signal to be divided [4]. The tail transistor for
this configuration has a dual application: it is used to generate DC bias current and
it provides the input transconductance for the RF signal [33]. The input capacitance
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
75
VDD
ILFD_OUT +
ILFD_OUT −
VTAIL
Figure 3.13: Injection-Locked Frequency Divider: Tail Injection
of the tail transistor can, however, limit the operational frequency and the locking
bandwidth of this configuration. The input is also single-ended, whereas the signal
on-chip from the VCO is differential in nature.
For the first divide-by-2 circuit an ILFD was selected that more fully meets the
requirement for a fully differential layout; the design details are presented in Section
4.3.1.
Static Master-Slave Flip-Flop Divider
In the CMOS 0.18-µm technology used it is possible to use the standard logic family
realizations to construct the logic gates and flip-flops used in digitally-based divider
circuits. CMOS structures are attractive because of the very low static power dissipated by current drawn in the steady state; dynamic power is consumed when the
current flows because of changes in signal level and is the primary power dissipation
method in CMOS logic circuits [64]. Figure 3.14 shows a logic level-based D flip-flop
constructed of 4 NAND gates and an inverter. The CMOS logic family realizations
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
76
D
Q
CLK
Q
Figure 3.14: CMOS level-based D flip-flop: logic circuit diagram
for digital circuits are limited to lower frequency operation because of the time constants associated with switching between logic ’0’ and logic ’1’. However, it is possible
to design circuits employing current mode logic (CML) that, while consuming more
static power, are functional at higher operating frequencies. These circuits present
digital-type timing responses, but employ design techniques more commonly found
in analog circuits. Based on the higher operating frequencies required, a static CML
design was used for the second stage divider.
The second divide-by-two stage was accomplished using a static master-slave flipflop (MSFF) divider, as shown in Fig. 3.15. This structure is composed of two
cascaded D flip-flops with negative feedback created by connecting the inverted slave
outputs to the master inputs [26], [27]. The MSFF divider toggles the output after
D+
Q+
MASTER
D−
Q−
CLK+ CLK−
D+
Q+
SLAVE
Q−
D−
CLK+ CLK−
+
OUTPUT
−
+
INPUT
−
Figure 3.15: Master-Slave Flip-Flop Frequency Divider Block Diagram
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
77
every clock cycle, causing the output to toggle at a rate of one-half the input clock
frequency, resulting in division by two [27].
Fig. 3.16 shows the circuit diagram for a single D flip-flop. This design is based on
a conventional latched circuit and has been previously reported [26]. Recent efforts
to increase operational frequency using novel high-speed latch designs in CMOS 0.18µm processes have been undertaken, with operational frequencies of 40 GHz reported
[28]. Based on simulation and the 13 GHz operational frequency the conventional
latched circuit of Fig. 3.16 was selected with slight modifications.
VDD
SENSE
Rd
LATCH
D+
Q+
Q−
Rd
M1 M2
M3
M4
D−
CLK+
M5
M6
CLK−
TAIL
10k
M tail
Figure 3.16: Schematic diagram of the D Flip-Flop
The D flip-flop in Fig. 3.16 has clock signal (CLK+/CLK-) and data (D+/D) differential inputs; (Q+/Q-) are the differential outputs. Gate voltages for the
CLK switching pair (M5 /M6 ) are provided by resistor divider networks (not shown),
and DC biasing current for the circuits is provided by the TAIL voltage for the tail
transistor MT ail . The flip-flop contains a SENSE circuit constructed of a differential
pair (M1 /M2 ), and a LATCH circuit constructed of a cross-coupled differential pair
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
78
(M3 /M4 ). The SENSE circuit develops voltages based on the currents at the drain
resistances Rd , which in turn are determined by the data inputs. The LATCH circuit
maintains a constant voltage at the drains because of the cross-coupled pair when
enabled.
Either the SENSE or the LATCH circuit is enabled by the CLK input at the
differential pair M5 /M6 . When CLK is high the SENSE section of the circuit is
enabled, and the LATCH section is disabled. In this case, outputs Q+/Q- track the
input data. When CLK is low, the SENSE section is disabled and the LATCH section
is enabled. The last state of the SENSE circuit is captured and held by the LATCH.
In this configuration, variations on the D inputs do not affect the state of the flip-flop.
3.7.4
Phase Detector
The phase detector (PD) outputs a control voltage that is used to vary the VCO
frequency. This control voltage is dependent upon the phase difference between the
input reference signal and the divided voltage-controlled oscillator (VCO) signal.
Phase detectors may be broadly categorized into two classes: multiplier (or combinatorial) devices and sequential devices [47]. Multiplier PDs generate a useful DC
error output as the average product of the input reference signal and the local oscillator signal. Multiplier PDs can operate over a wide frequency range and are capable
of working with low-level input signals. For sinusoidal inputs the detection range
is limited to nπ/2 ± π/2, n = ±1, ±2, . . . with a sinusoidal output characteristic.
Multiplier PDs cannot detect the frequency error of the inputs [34]. Sequential PDs
generate a useful error voltage based solely on the time interval between transition of
the input reference signal and the local VCO signal [47]. These phase detectors show
CHAPTER 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIS
79
Property
Multiplier PD Sequential PD
Acquisition Range
π
≥ 2π
Operational Frequency
High
Moderate
Noise Sensitivity
Good
Moderate
Output
Continuous
Lock dead zones
Table 3.1: Performance Comparison, Multiplier and Sequential Phase Detectors
improved acquisition range and can be used to detect frequency differences between
the reference and VCO signals. The output for square wave inputs is a pulsewidthmodulated waveform whose average value is proportional to the time interval between
waveform transitions. In the vicinity of PLL lock, the pulse width may become insufficient to properly drive a charge pump gate, resulting in dead zones and VCO output
jitter/phase noise [34]. The output is sensitive to input data patterns, particularly
duty cycle. Because these detectors are transition-based, they are intolerant of missing or extra transitions and hence are more sensitive to noise than multiplier PDs.
Table 3.1 compares the two classes of phase detectors. Based on the high operational
frequency and continuous differential output, a multiplier PD was selected for the
research design.
A description of the sub-circuits used in the PLL frequency multiplier has been
presented, as well as the justification for the selected configurations. Ch. 4 will review
the individual circuits in greater detail.
Chapter 4
Component Description
4.1
Introduction
This chapter describes the analysis, design and layout of the subcomponents used
in the PLL clock multiplier. Each subcomponent was designed using either Agilent EESof ADS or Cadence Spectre. The subcomponent designs used innovative
techniques for design and test wherever feasible. This chapter will review the subcomponents that make up the PLL, and identify where novel design techniques were
used as well as innovative testing techniques for performance verification.
4.2
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) is used to generate the 26 GHz output signal
that, in a locked state, will be equal to four times the input reference signal. The
VCO phase noise performance is important, as the PLL system phase noise outside
the PLL bandwidth will be dominated by it.
80
CHAPTER 4. COMPONENT DESCRIPTION
81
Figure 4.1 shows the circuit schematic for the VCO. The VCO is a cross-coupled
2.8 V
L
VCOctrl_pos
C var
VCOctrl_neg
VCO_pos
VCO_neg
M1
5.7k
M2
10k
10k
2V
14.3k
C TAIL
VTAIL
MTAIL
Figure 4.1: Circuit Schematic, negative gm VCO
differential structure with an LC tank. The NMOS cross-coupled transistors M1 and
M2 (gate width of 45 µm each) generate a negative resistance to cancel resistive tank
losses. Drain-to-opposite-gate blocking capacitors (realized as 3 pF metal-insulatormetal capacitors (MIMcaps)) allow the oscillator core gates to be biased independently of the drain voltage, enabling a reduction in device current draw. The drain
voltage for the negative gm (“neg-gm”) transistors is fed via a centre tap in the tank
inductor. The neg-gm transistor gate bias voltages are set by a resistive divider network with 10 kΩ decoupling resistors. This particular feature is a relic from the initial
CHAPTER 4. COMPONENT DESCRIPTION
82
VCO design where setting of the neg-gm gate voltages was implemented for bias control. The tail transistor MT AIL (gate width 100 µm) is used to set the bias currents
for the VCO. A MIM capacitor CT AIL of value 0.44 pF between the tail transistor
drain and source was placed to reduce tail current noise. Fig. 4.2 shows the layout
for the VCO.
80 µm
Spiral Inductor
Differential Varactors
Negative gm Transistors
Tail Transistor
Blocking Caps
Figure 4.2: Layout, negative gm VCO
The tank inductor uses a square one-turn centre-fed design with dimensions of
80x80 µm and trace width of 10 µm. The inductor is fabricated on the top metal
CHAPTER 4. COMPONENT DESCRIPTION
83
layer (M6) and has a simulated inductance at 26 GHz of approximately 138 pH.
The varactor circuit is composed of a differential accumulation-mode metal-oxide
semiconductor (AMOS) varactor configuration [52]. AMOS varactors were selected
for this application because of their large potential tuning range. A nine-fingered
varactor design served as the basic element for the differentially-controlled varactor
assembly. Two of the basic design elements were connected in a series-opposing
connection with gates tied together at a voltage control/tuning node and opposing
diffusions connected to the opposite sides of the VCO tank. This arrangement is
identified as a gate-tuned varactor sub-assembly; Figure 4.3(a) shows a simplified
diagram of the structure. To complement the gate-tuned varactor sub-assembly, two
of the basic design elements were series-opposing connected with the diffusions tied
together at the voltage control/tuning node and the opposing gates connected to the
opposite sides of the VCO tank. This arrangement is identified as a diffusion-tuned
varactor sub-assembly, and is shown in Figure 4.3(b).
A differential varactor assembly (Cvar of Fig. 4.1) was constructed by placing three
gate-tuned varactor sub-assemblies in parallel with three diffusion-tuned varactor subassemblies across the VCO tank. Figure 4.4 shows a circuit diagram of the differential
varactor assembly.
The quantity of 3 gate-tuned and 3 diffusion-tuned varactor sub-assemblies in
parallel was selected to generate the correct VCO oscillation frequency and to provide
a wide tuning range for the VCO.
CHAPTER 4. COMPONENT DESCRIPTION
v o+
84
v o−
V ctrl
11111
00000
000000
00000
11111
000000
00000
11111
00000111111
11111
000000
111111
00000111111
11111
000000
111111
00000
11111
00000
11111
000000
00000
11111
000000
00000
11111
G111111
G111111
S
D
S
D
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000111111
11111
000000
00000111111
11111
000000
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
11111
111111
11111
111111
11111
00000
000000
00000
000000
00000
000000
111111
00000
11111
000000
111111
00000
11111
n+
n+
n+
n+
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000 111111
11111
000000
00000
11111
n well
n well
p substrate (body)
(a)
v o+
v o−
V ctrl
00000
11111
11111
00000
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
00000
11111
000000
00000
11111
G111111
G111111
00000
11111
D
S
S
D
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
00000
11111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000
11111
n+
n+
n+
n+
000000
111111
00000
11111
000000
111111
00000
11111
000000
111111
00000 111111
11111
000000
00000
11111
n well
n well
p substrate (body)
(b)
Figure 4.3: AMOS varactor sub-assemblies: (a) Gate-tuned, (b) Diffusion-tuned
4.3
Frequency Dividers
The PLL has a total division factor of 4. If the division is split into two stages, the
first divider must operate with an input of 26 GHz and an output of 13 GHz, and
the second division stage must operate with an input of 13 GHz and an output of
6.5 GHz. As detailed in Ch. 2, an injection-locked frequency divider (ILFD) was
selected for the first divide-by-2 stage, and a master-slave flip-flop (MSFF) divider
was selected for the second divide-by-2 stage.
CHAPTER 4. COMPONENT DESCRIPTION
85
Vctrl_pos
Gate−tuned varactors
vo+
vo−
Diffusion−tuned varactors
Vctrl_neg
Figure 4.4: AMOS differential varactor assembly
4.3.1
Injection Locked Frequency Divider
Fig. 4.5 shows the circuit schematic of the direct injection ILFD used in the circuit.
The ILFD core is a symmetric structure composed of stacked PMOS and NMOS
neg-gm sub-circuits. This dual core configuration was selected to present a balanced
structure in keeping with the fully-differential nature of the PLL. The additional
PMOS neg-gm cell also acts to increase the negative resistance used to counteract
the losses in the LC tank.
Instead of injection into the tank circuit via the transconductance of the tail
transistor, the input signal is directly injected across the LC tank through the use of
NMOS and PMOS switches. This technique allows the design of the the NMOS and
PMOS switch transistors to be much smaller because of the more efficient injection
scheme and because the switches do not have a biasing function [33]. This type of
injection gives a quasi-differential structure that is suited to the differential input
signal.
Harmonic balance simulations using Agilent EESof ADS were carried out on the
direct-injected ILFD used in the designed PLL to determine locking range and divider
CHAPTER 4. COMPONENT DESCRIPTION
86
L
ILFDvar_pos
C var
ILFDvar_neg
4.3 V
M1
M2
ILFD_IN +
PSW
ILFD_IN −
NSW
ILFD_OUT +
ILFD_OUT −
4.3 V M
M4
3
10.7k
10k 10k
9.3k
C TAIL
VTAIL
M TAIL
Figure 4.5: Injection-Locked Frequency Divider: Direct Injection
output phase noise. The VCO and interconnecting circuitry were used to generate
the ILFD input signal to insure realistic realistic loading was achieved. A VCO-ILFD
circuit was also investigated where one of the differential VCO signals was injected
into the ILFD tail transistor gate. Table 4.1 summarizes the simulation results. The
direct-injection ILFD displays a substantially larger locking bandwidth than the tailinjected ILFD (3.2% versus 1.17%). The difference in phase noise between the ILFD
input and output signals was -5.99 dB; based on a theoretical input-to-output phase
noise voltage ratio of 0.5 (-6.02 dB) there is minimal phase noise addition as a result of
CHAPTER 4. COMPONENT DESCRIPTION
87
Property
Tail Injection Direct Injection
Injected Centre Frequency (GHz)
25.71
25.76
Injected Locking Bandwidth (GHz)
0.302
0.825
Locking BW/Centre Freq (%)
1.17
3.20
Output/Input Phase Noise @ 1MHz (dB)
–
-5.99
Table 4.1: ILFD Locking Bandwidth: Tail- vs. Direct-Injection
the divider. Simulations of output vs. input phase noise for the tail-injected ILFD did
not converge. The increased locking bandwidth and minimal phase noise degradation
of the direct-injected ILFD show the benefit of this design.
Fig. 4.6 shows the layout for the ILFD with the major circuit elements identified. The design of the ILFD used many of the elements of the VCO of Section 4.2.
Complementary NMOS and PMOS cross-coupled neg-gm cells were used to provide
negative resistance to compensate for losses in the LC tank. The PMOS neg-gm transistors (M1 /M2 ) had total width of 40 µm each, while the NMOS transistors (M3 /M4 )
had total width of 37.5 µm each. Drain-to-opposite-gate blocking capacitors (3 pF
MIMcaps) were used, as was a 0.44 pF tail transistor for noise suppression. Bias
current was supplied from a 4.3 V source through the common source of the PMOS
transistors; the sizing of the the PMOS transistors was selected to obtain a 2.8 V DC
bias voltage at the PMOS/NMOS drains and LC tank arms. Bias current was set by
an NMOS tail transistor (total width 100 µm).
The PMOS and NMOS direct injection transistors were sized to provide the required switching while minimizing the loading on the VCO signal. The NMOS switch
transistor (NSW) had total width of 10 µm, while the PMOS switch transistor (PSW)
had total width of 12.5 µm. The widths were selected to provide similar loading to
the VCO output signals.
CHAPTER 4. COMPONENT DESCRIPTION
88
99 µm
Spiral Inductor
(2−turn)
Differential Varactors
PMOS neg−gm
Switches (PMOS, NMOS)
NMOS neg−gm
Tail Transistor
Blocking Caps
Figure 4.6: Layout, injection-locked frequency divider
The tank inductor uses a square two-turn centre-fed design with dimensions of 99 x
99 µm, trace width of 10 µm and trace separation of 10 µm. The inductor is fabricated
primarily on the top metal layer (M6) with the crossover on metal layer 5. The
simulated inductance at 13 GHz was approximately 360 pH. The differential varactor
structure used in the VCO (section 4.2) consisting of three gate-tuned varactor subassemblies in parallel with three diffusion-tuned varactor sub-assemblies was included
to allow for tuning of the ILFD oscillator to increase the operational frequency range
CHAPTER 4. COMPONENT DESCRIPTION
89
for testing purposes.
4.3.2
Static Master-Slave Flip-Flop Divider
Fig. 4.7 shows the circuit schematic for the MSFF divider. The schematic shows the
4.3 V
MSFF_OUT +
Lpeak
Lpeak
Lpeak
Lpeak
Rd
Rd
Rd
Rd
M 1,M
M 2,M
M 3,M
M 4,M
M 1,S
M 2,S
M 5,M M 6,M
MSFF_Tail
10k
M 5,S
10k
M tail,M
MASTER
M 3,S
MSFF_OUT −
M 4,S
M 6,S
M tail,S
SLAVE
ILFD −
ILFD +
Figure 4.7: Schematic diagram of the Master-Slave Flip-Flop Divider
master and slave flip-flops with the inverted slave outputs fed back to the master input. The ILFD signal is injected at the CLK inputs, resulting in a divide-by-2 output
signal at MSFF OUT. Circuit DC bias current is drawn from a 4.3V source and is controlled via the tail transistors in the master and slave flip-flops (MT ail,M and MT ail,S ).
Fig. 4.8 shows the MSFF divider layout. The Master and Slave flip-flop layout
and transistor sizes are the same for symmetry purposes. For the sake of clarity, only
the Master transistors have been identified in Fig. 4.8. Transistor gate widths for the
SENSE transistors (M1 /M2 ) and LATCH transistors (M3 /M4 ) are 20 µm each; the
gate widths of the CLK transistors (M5 /M6 ) are 40 µm each, and the gate widths
CHAPTER 4. COMPONENT DESCRIPTION
90
From
ILFD+
Slave
Shunt Peaking
Inductor
Latch
MSFF Output
100 µm
4.3 V DC
Sense
Clk
Tail
From
ILFD−
Master
Figure 4.8: Layout, master-slave flip-flop divider
of the tail transistors, MT ail,M and MT ail,S , are 70 µm each. Decoupling capacitors
(1 pF MIMcaps) are included at the ILFD inputs and the divider outputs to allow
for independent DC biasing. Gate biasing for the CLK/ILFD input transistors is
achieved via resistor divider networks (not shown).
A large challenge of the MSFF divider design was the reduction of parasitic capacitances and associated RC time constants that limit the operational frequency of the
circuit. For this reason, the output-to-input feedback connections were DC coupled.
CHAPTER 4. COMPONENT DESCRIPTION
91
The input and output decoupling capacitors were set to 1 pF, interconnecting wire
runs within the circuit were minimized and drain resistors Rd were set to 300 Ω to
reduce the RC time constant associated with circuit capacitances.
Inductors (Lpeak ) have been included in the SENSE drain circuits to increase the
operational frequency by shunt inductive peaking [26]. Shunt inductive peaking is
a technique that is used in active devices to increase operational bandwidth and
frequency by introducing an inductor Lpeak in series with the drain resistance Rd to
offset the effect of the load capacitance at the SENSE differential pair drains [58]. 1
nH inductors were inserted as part of the drain circuitry for the SENSE circuits. The
peaking inductors are asymmetric square three-turn with dimensions of 100x100 µm,
trace width of 5 µm and trace separation of 5 µm. Simulated results show an increase
in operational frequency of 5% for the inductor value selected. While the increase
in operational frequency is not large, it provides additional frequency margin for the
divider. Impact on the noise transfer function was relatively small, with a simulated
increase of phase noise at a 10 kHz offset of less than 0.2 dB with the inductors
included versus a realization without inductors.
4.4
Phase Detector
A Gilbert cell mixer [35] was selected as the PD for the PLL, based on the high
frequency operational requirement of the PLL, the continuous output, and the ability
to operate with low-level signals. The selection of the Gilbert cell phase detector also
allowed the setting of the common-mode voltage required for the differential VCO
control inputs. Fig. 4.9 shows the schematic for the Gilbert cell PD. Fig. 4.10 shows
the layout for the Gilbert cell PD.
CHAPTER 4. COMPONENT DESCRIPTION
VDD
+
92
VIF
−
Rd
LO
switching
stage
+
VLO
−
M3
RF
+
transconductance V
− RF
stage
Rd
M4
M1
Vtail
VDD
M5
M6
M2
M Tail
Figure 4.9: Circuit schematic - Gilbert cell phase detector
4.4.1
Operation
The input Reference signal is fed to the LO switching stage of the mixer, while the
signal from the MSFF divider (the VCO/4 signal) is input to the RF transconductance stage. The RF transconductance transistors (M1 /M2 ) and the LO switching
stage transistors (M3 /M4 /M5 /M6 ) have gate widths of 10 µm each. A tail transistor
(MT ail ) is used to control the current in the core of the mixer with a gate width of
10 µm. DC bias is supplied from a 4.3 V source. Individual gate biases at the RF
transconductance and LO switching stages are set by high-resistance voltage divider
networks (not shown). The mixer differential output voltage VIF is taken across the
two drain resistors Rd and is used to control the VCO frequency. The drain resistance
of 1657Ω was chosen to set the common mode DC voltage to 2.8 V for input to the
VCO differential varactor control lines.
The mixer differential output is composed of components at the sum and difference
frequencies of the LO and RF input signals. The loop filter (see section 3.2) is used to
CHAPTER 4. COMPONENT DESCRIPTION
93
Biasing Resistors
Rd
RF Trans−
conductance
LO
Switching
Rd
Tail
Transistor
Biasing Resistors
140 µ m
Figure 4.10: Layout, Gilbert cell phase detector
attenuate the higher frequency sum term, leaving only the difference (also referred to
as the intermediate frequency or IF) term. For cases where the LO and RF frequencies
are the same, VIF is a DC voltage representative of the phase difference between the
RF and LO signals. A benefit of the Gilbert Cell PD is the continuous output which
results in lower in-lock jitter and well understood PLL analysis [44].
4.4.2
Non-Ideal Behaviour
Propagation delays resulting in non-ideal behavior have been observed in both digital
and analog PDs [67], [44], [53]. The non-ideal behavior is characterized by a shift in
CHAPTER 4. COMPONENT DESCRIPTION
94
the actual zero-crossing point Φ0,actual with respect to the ideal zero-crossing point
Φ0,ideal ; the difference is known as the static phase offset ΦO [44]. Figure 4.11 shows an
Detector Output (V)
example of static phase offset. ΦO is dependent upon fabrication process, frequency,
−180
−135
−90
−45
Φ0
Φ 0,ideal
0
Φ 0,real
45
90
135
180
Input Phase Difference, deg
Ideal
Real
Figure 4.11: Phase Detector Output versus LO-RF Phase Difference for Ideal and
Real Multiplier PDs
temperature and device bias conditions [67], [44], [68].
The ΦO of a phase detector may have a significant impact on the initial conditions
of a time-domain simulation. Using phase plane analysis [48], the additional phase
offset may place the PLL outside of a region of asymptotic stability for a given
reference signal, resulting in no phase lock. Static phase shift and potential means of
reducing its impact should therefore be considered as part of the PLL design process.
ΦO is composed of two components: layout-related parasitic RC effects ΦO,Cp , and
the intrinsic channel transit time effect ΦO,tr . The intrinsic channel transit time τtr
is a significant contributor to delay in integrated circuits at higher frequencies. A
general relationship for τtr is [69]
τtr =
|Qi |
,
IDS
(4.1)
CHAPTER 4. COMPONENT DESCRIPTION
95
where Qi is the inversion layer charge and IDS is the channel current.
For the case of strong inversion saturation without velocity saturation using the
long channel approximations for inversion layer charge and current [69],
τtr =
αL2g
4
,
3 µ(VGS − VT )
(4.2)
where α is a factor associated with the body effect coefficient, Lg is the gate channel
length, µ is the effective electron mobility, VGS is the DC gate-source voltage, and VT
is the transistor threshold voltage. Φ0,tr may then be written, in degrees, as
Φ0,tr =
τtr
∗ 360◦ ,
(fi )−1
(4.3)
where fi is the frequency of the current waveform through the device.
The individual channel transition times for the RF and LO switching stages (τtr,RF
and τtr,LO ) may be determined using (4.1) (for the case where current is known) or
(4.2). The transition-related static phase shift Φ0,tr for the PD may then be calculated
using
Φ0,tr =
τtr,LO
τtr,RF
+
−1
(fi,RF )
(fi,LO )−1
∗ 360◦ ,
(4.4)
where fi,RF and fi,LO are the frequencies of the currents in the RF transconductance
and LO switching stages. For the case of the Gilbert Cell PD with the LO and RF
signals at the same frequency but out of phase by 90◦ ,
fi,LO = 2 ∗ fi,RF .
Equation (4.4) may then be re-written as
τtr,LO
τtr,RF
+
∗ 360◦ .
Φ0,tr =
(fi,RF )−1 (2 · fi,RF )−1
(4.5)
(4.6)
An investigation into means of controlling the static phase offset by DC bias control has also been undertaken [70]. The investigation varied the PD current through
CHAPTER 4. COMPONENT DESCRIPTION
96
ΦO (deg) Locking Bandwidth (MHz)
43
4.33
37
4.41
34
4.45
0 (ideal)
4.65
Table 4.2: Input-Referenced Locking Bandwidth vs. Static Phase Offset
the applied tail transistor voltage. The appropriate LO switching stage node voltages
were determined using the unified model for device current iD in saturation [58]
−1
µn Cox
Lg Esat
iD =
,
Wg (VGS − Vt )Esat 1 +
2
VGS − Vt
(4.7)
where Cox is the oxide capacitance per unit area, Wg is the device width and Esat is
the electric field at which the carrier velocity is 50% of the low-field velocity. The
same task was then performed on the RF transconductance transistors, and (4.1)
used to calculate Φ0,tr , with the inversion layer charge Qi represented by [69]
2
|Qi | = Wg Lg Cox (VGS − VT ).
3
(4.8)
The effects of channel length modulation for this case were not considered to allow
for a simpler determination of Φ0,tr .
The impact of this additional phase offset is a potential lessening of the locking
bandwidth of the PLL on startup. Consider the case of the Type I, second order PLL
of this research with K0 = 2π ·0.785x109 rad/V, KD = 1.158 V/rad and N = 4. Table
4.2 shows the input-referenced simulated locking bandwidth without cycle slip using
the MATLAB/Simulink simulation for the non-linear differential equation (3.22) for
the measured and ideal values of ΦO . The case with the largest ΦO examined has a
locking bandwidth of 93% of the ideal case.
The designs of the individual elements of the PLL frequency multiplier have been
CHAPTER 4. COMPONENT DESCRIPTION
97
presented. Ch. 5 will discuss the challenges of system level integration, simulation
and analysis.
Chapter 5
Phase Lock Loop - Top Level
5.1
Introduction
Integration and layout of the phase-locked loop components discussed in the previous
chapter required not only a re-examination of the individual component performance
but also analysis of the PLL as a whole.
This chapter first describes the integrated PLL layout with challenges identified.
Determination of key performance parameters for system level analysis is then undertaken. A summary of simulation efforts is given with observations on estimated
simulation time required for the implemented design. A method of evaluating the
noise rejection of the circuit is proposed. Finally, analytical phase noise calculations
are reviewed, with a consideration of the effect of the multiplication factor N on
output phase noise.
98
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
5.2
99
Top Level Layout
The integration of the PLL used the sub-circuits discussed in Chapter 4 with the
goal of generating as symmetric a layout as possible. The PLL is fully differential
by design as a means of alleviating potential interfering common-mode signals and
the effects of common-mode noise. Effort was made to keep sub-circuit designs and
interconnections symmetric.
The top level PLL was laid out in 0.18-µm CMOS technology supplied by the
Taiwan Semiconductor Manufacturing Company (TSMC). The process uses six metal
layers and one polysilicon layer, as well as a self-aligned silicidation (salicide) process
that is used to significantly reduce the parasitic series resistant for MOSFETs [71].
Additional mixed signal/RF processes used include deep n-wells (for increased noise
rejection), high resistivity implants (for large-valued resistors) and metal-insulatormetal (MIM) capacitors (for larger capacitance values). A thick metal top layer
(M6T) option was available, but not used. The TSMC 0.18-µm CMOS process has
a short circuit unity current gain frequency (ft ) in excess of 40 GHz for the design
NMOS transistors and an ft in excess of 13.5 GHz for the design PMOS transistors
[72]. The unity power gain frequency (fmax ) is device size- and bias-dependent; for a
transistor of width 10 µm, VDS =1.8 V, VGS =1.0 V fmax is in excess of 80 GHz.
Figure 5.1 shows the fabricated circuit for the PLL. The overall dimensions of the
circuit are 1733 x 1483 µm. The location of the sub-circuits are identified, as are
the interface pads and supplementary test points. Transmission lines (TLs) between
the sub-circuits are designed as high-impedance co-planar waveguide (CPW) lines
(conductor width 5 µm, gap 10 µm, characteristic impedance Z0 = 78Ω) to minimize
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
100
loading effects on the circuits. CPW lines were selected because of ease of the interface, their ability to shield underlying circuitry from radiated fields, and the close
proximity of the groundplanes to the centre conductor [73].
The 78Ω Z0 was chosen as a tradeoff between high characteristic impedance and
DC resistance of the transmission line.
5.2.1
VCO to ILFD Interconnection
The VCO and ILFD were laid out back-to-back to allow for simple RF interconnection of the differential signals. Figure 5.2 shows the circuit schematic for the VCO
and ILFD with interconnecting circuitry. The VCO differential outputs were taken
directly from the LC tank circuit via 1 pF capacitors to allow independent DC biasing in the in-line buffer amplifiers. The VCO differential signals were then fed
through common-source (CS) buffer amplifiers (MV CObuf f er , total width 30-µm) to
lessen inter-component loading effects discovered when the VCO and ILFD were connected. DC biasing at the VCO buffer CS drains was particularly important. The
direct injection of the VCO signal across the ILFD tank via N- and PMOS transistor switches requires that the nominal switch DC gate voltages be the same as the
ILFD DC tank voltage to maximize the effectiveness of the injection. Small gate bias
differences would cause improper timing operation of the switches; large gate bias
differences would potentially result in one of the switches being biased permanently
on, effectively shorting the LC tank branches. The drain resistor was sized at 160Ω
to generate a DC voltage of 2.73 V on the ILFD input gates.
1483 µ m
MSFF_sample
REF_pos
101
VCOctrl_pos
2.8V DC
VCO_tail
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
ILFD_sample
LPF (pos)
VCO_pos
PD MSFF
ILFD
VCO
REF_neg
VCO_neg
LPF (neg)
VCOctrl_neg
PD_tail
MSFF_tail
ILFDvar_pos
ILFDvar_neg
ILFD_tail
RESET
4.3V DC
1733 µ m
(a)
LPF
PD
VCO
REF
OUT
MSFF
2
ILFD
2
(b)
Figure 5.1: PLL Integrated Circuit (a) Circuit microphotograph, (b) Block diagram
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
2.8 V
102
L
L
C var
2.8 V
M OPbuffer
C var
VCO_neg
4.3 V
4.3 V
RVCObuff
M
VCObuffer
PSW
Buffer
4.3 V
RVCObuff
NSW
M
VCObuffer
Buffer
2.8 V
M OPbuffer
VCO_pos
ILFD
VCO
Figure 5.2: VCO to ILFD Circuit Schematic
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
103
The chip VCO differential outputs (VCO pos, VCO neg) are taken via commondrain buffer amplifiers (MOP buf f er , total width 10-µm) from the VCO-to-ILFD transmission lines.
5.2.2
ILFD to MSFF Interconnection
The layout combination of the ILFD tank inductor and the MSFF divider peaking
inductors necessitated a considerably longer transmission line run between these two
circuits than between the VCO and ILFD (760 µm vs. 260 µm). A T-junction with
equal arms was incorporated to split the signal from the MSFF into master and slave
components. Figure 5.3 shows the circuit schematic for the ILFD and MSFF divider
with interconnecting circuitry.
The ILFD differential outputs are taken directly from the LC tank circuit via 1
pF capacitors. These signals are then fed through CS buffer amplifiers (total width
60-µm) for amplification and to reduce the loading effects on the ILFD from the
MSFF divider and transmission lines. The drain resistor for the buffer amplifier
(RILF Dbuf f ) was selected to be 115Ω to allow maximum voltage swing for the ILFD
output signal. A test output port (ILFD sample) is achieved by using a coupler on
the ILFD-MSFF transmission line (discussed in Section 5.2.4), followed by a commondrain (CD) buffer amplifier (total width 10 µm). While only one test port is brought
out for testing to save layout space, identical circuitry (coupler plus CD amplifier) is
included on the complementary signal line to maintain a symmetrical design. Figure
5.4 shows the simulated coupling factor from the ILFD Buffer output to the input
gate of the ILFD sample CD amplifier. This plot includes the loss of the short section
of transmission line prior to the coupler. The coupling factor at 13.21 GHz is -36.5
Figure 5.3: ILFD to MSFF Circuit Schematic
ILFD
NSW
PSW
4.3 V
C var
L
1 pF
1 pF
2.8 V
M ILFDbuff
RILFDbuff
4.3 V
4.3 V
RILFDbuff
M ILFDbuff
2.8 V
Coupler
Coupler
ILFD_sample
4.3 V
MSFF_OUT +
MSFF_OUT −
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
104
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
105
0
−5
Coupling Factor, dB
−10
−15
−20
−25
−30
−35
−40
−45
−50
0
5
10
15
20 25 30 35
Frequency (GHz)
40
45
50
Figure 5.4: Coupling Factor vs. Frequency, ILFD Buffer Output to Gate of
ILFD sample Common Drain Amplifier
dB.
5.2.3
MSFF to PD Interconnection
The interconnections between the MSFF divider and the phase detector are straight
transmission lines; the loading effects of the subsequent PD inputs and the strength of
the MSFF divider outputs negated the need for inter-circuit buffer amplifiers. Figure
5.5 shows the MSFF-to-PD interconnecting circuitry.
The MSFF differential outputs are first decoupled using 1 pF capacitors and then
fed to the PD RF inputs using relatively short (175 µm) transmission lines.
A test output port (MSFF sample) is constructed using the same coupler design
Rd
106
Coupler
4.3 V
From ILFD
2.8 V
Coupler
Rd
2.8 V
MSFF_sample
REF− REF+ 4.3 V
+ VIF
−
4.3 V
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
Figure 5.5: MSFF Divider to Phase Detector Circuit Schematic
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
107
for ILFD verification and a subsequent common drain buffer amplifier (total width
10 µm). Identical circuitry (coupler plus CD amplifier) was again included on the
complementary signal TL to maintain symmetry.
Figure 5.6 shows the simulated coupling factor from the MSFF divider output to
the input gate of the MSFF sample CD amplifier. This plot includes the loss of the
0
−5
Coupling Factor, dB
−10
−15
−20
−25
−30
−35
−40
−45
−50
0
5
10
15
20 25 30 35
Frequency (GHz)
40
45
50
Figure 5.6: Coupling Factor vs. Frequency, MSFF Divider Output to Gate of
MSFF sample Common Drain Amplifier
one pF decoupling capacitors and the short section of transmission line prior to the
coupler. The coupling factor at 6.5 GHz is -42.0 dB.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
5.2.4
108
Test Coupler
Test outputs were included in the circuit for performance verification of the individual stages. Unlike the VCO output signal the internal test ports provide low power
samples for determination of operational frequencies within the loop. A sampler with
low coupling factor was achieved by using an electrically short (l=15µm) broadside
coupler between the two top metal layers (M5 and M6). Figure 5.7 shows the construction of the coupler.
Metal6
5 um
Metal5
Signal
15 um
Via Array
Coupled
Figure 5.7: Test Coupler Construction
This type of coupler allows a small amount of signal to be sampled while minimally
loading the transmission line. Agilent EESof Momentum was used to determine the
coupling factor for the couplers and associated transmission lines at 13.21 GHz and
6.52 GHz; Table 5.1 summarizes the coupling factors versus frequency for the two
sample ports.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
Coupler
ILFD sample CD Amp I/P
MSFF sample CD Amp I/P
Frequency, GHz
13.21
6.52
109
Coupling Factor, dB
-36.5
-42.0
Table 5.1: PLL Sample Ports Coupling Factor
5.2.5
Loop Filter
The complementary outputs from the phase detector are fed through individual loop
/ low pass filters (LPF) before being input to the VCO differential control lines. As
a result of the mixing operation of the phase detector, the main signal frequencies
at the LPF inputs are the sum and difference of the reference signal and the divided
VCO signal. When the PLL achieves a locked state, the LPF passes the difference
signal (ideally a DC value) and rejects the sum signal (at a frequency of twice the
reference input).
The selection of the LPF order strongly affects the operational loop constants and
the stability of the PLL. Bode plots are used to evaluate PLL stability based on the
open loop gain A(s)B(s). Bode plots provide magnitude and phase responses versus
frequency based on the the transfer function poles and zeros identified in Section 3.2.
In order for the PLL to remain stable (i.e., not oscillate) the open loop gain A(s)B(s)
of Fig. 3.2(b) must have a phase greater than −180◦ at the frequency where its
magnitude is unity (log(|A(ω)B(ω)|) = 0 dB) [47].
Figure 5.8 shows 3 different types of lowpass filters, the open loop gain A(s)B(s),
and the Bode magnitude and phase response diagrams with the poles of the LPF
frequency domain transfer function identified as 1/τ . The PLL is assumed to be of
the form of Fig. 3.2(b), with an open loop gain of
A(s)B(s) = KD ∗ F (s) ∗
K0 1
∗ ,
s
N
(5.1)
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
R1
110
R2
R2
C1
R1
C2
R1
C1
C1
1
1
s (1+ sC 1R 1 )
A(s)B(s) =
Log|A(ω )B( ω)|
1
ω=
τ1
40 dB/dec.
0
Log ω
0
Log ω
−90
−135
−180
(a)
(1+ sC 1R 1 )
1
s (1+ sC 1(R 1 +R 1 ) )
ω=
1
*
s
1
(s2C 1C 2R 1R 2+ s (C 1R 1+ C 2R 2+ C 1R 2 +
) 1)
A(s)B(s) =
1
τ1
20 dB/dec.
1
ω=
τ1
40 dB/dec.
ω=
K0Kd
N
1
τ2
40 dB/dec.
ω=
Log ω
0
Phase (deg)
Phase (deg)
Log|A(ω )B( ω)|
20 dB/dec.
K0Kd
N
Log|A(ω )B( ω)|
K0Kd
N
0
Log ω
−90
−135
−180
(b)
1
τ2
Log ω
60 dB/dec.
Phase (deg)
A(s)B(s) =
Log ω
−90
−135
−180
−225
−270
(c)
Figure 5.8: Lowpass Filters and their effect on open loop gain. (a) First Order One
Pole, (b) First Order One Pole/One Zero, (c) Second Order Two Poles
Where F(s) is the LPF voltage transfer function in the frequency domain.
Fig. 5.8(a) shows the magnitude and phase response for a first order LPF with one
pole. This type of filter is also called a lag filter because the input-to-output voltage
transfer function introduces a negative phase (or lag). The magnitude response shows
a region of -20 dB/decade slope for frequencies less than the pole frequency 1/τ1 and
-40 dB/decade slope for frequencies greater than 1/τ1 . The phase response is greater
than −180◦ for all frequencies, as the phase of A(s)B(s) only approaches −180◦
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
111
asymptotically at an infinite frequency (ω → ∞). This filter is attractive from a
noise rejection perspective, as higher frequency noise will be more rapidly rejected.
The limited number of settable variables does constrain the selection of the loop
damping factor ζ.
Fig. 5.8(b) shows the magnitude and phase response for a first order LPF with
one pole and one zero (also known as a lead-lag filter; phase lead from the zero, phase
lag from the pole). The magnitude response of A(s)B(s) using this filter shows a
regions of -20 dB/decade slope for frequencies ω < 1/τ1 , -40 dB/decade slope for
1/τ1 < ω < 1/τ2 , and -20 dB/decade slope for ω > 1/τ2 . The phase response shows
that for frequencies 1/τ1 < ω < 1/τ2 there is a decrease towards −180◦ that then
returns to −90◦ for ω > 1/τ2 . This filter is often used because of the ability to
set the two time constants, allowing setting of all of the loop variables (ωn and ζ).
The phase response shows that the configuration is stable over all frequencies; the
magnitude response is only -20 dB/decade for high frequencies, making this PLL
more susceptible to high frequency noise.
Fig. 5.8(c) shows the magnitude and phase responses for a second order LPF with
two poles. The phase response shows that depending on the pole frequencies selected
it is possible to have phase < −180◦ for an open loop gain greater than 1, resulting in
instability. This could be corrected by the addition of a zero to the transfer function,
adding further complexity to the LPF design.
The LPF selected for the PLL is a first order single pole filter, based on the
superior noise rejection characteristics at high frequency and the simplicity of the
design.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
5.3
5.3.1
112
Top Level Performance Evaluation
Layout and Circuit Extraction
Layout for the PLL multiplier was carried out using the Cadence software suite. Each
of the main subcircuits (VCO, ILFD, MSFF divider, and phase detector) was laid out
separately and saved in a hierarchical structure. These structures were then placed in
a symmetrical layout with required interconnecting circuitry ( decoupling capacitors,
in-line buffer amplifiers and interconnecting transmission lines). Couplers and sample
buffer amplifiers were then placed, as well as associated sample transmission lines to
the output sample ports.
Input and output high frequency ports are set on the perimeter of the integrated
circuit for interface purposes. The PLL is fully differential by design, including the
clock reference inputs (REF pos / REF neg) and the VCO outputs (VCO pos /
VCO neg). The differential input and output ports are designed to use dual-head
ground-signal-ground (GSG) probes using a 150 µm pitch between the heads. Sample
outputs from high frequency points within the PLL (ILFD sample, MSFF sample) are
intended for signal monitoring and investigative purposes; interfaces to these outputs
were GSG 150-µm head pitch circuit probes. The sample ports were laid out in such
a way that it would be possible to use either one head of a dual-head probe or a
single-head probe for interfacing.
Additional DC control and power interface pads are placed on the chip perimeter.
The two voltage rails (2.8 V, 4.3 V) use 80 µm square pads placed close to the chip
corners. A six-pin DC/Control interface block (80 µm square pads, 150 µm head
pitch) allows multiple DC control lines in a compact area. The interface for the
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
113
VCO tail control line is compatible with a GSG 150-µm head pitch circuit probe;
this allows injection of either a DC voltage (for standard VCO operation) or a DC
and RF signal (for VCO injection locking, as discussed in Section 6.3.1). Interfaces to
the VCO input control lines (VCOctrl pos, VCOctrl neg) are also designed for either
GSG 150-µm head pitch circuit probes or single pin DC probes and are used for signal
monitoring and noise investigations, as described in Section 6.4.2.
The Cadence software suite has the ability to extract the transistors, capacitors
and resistors from the circuit layout. The software can also extract the circuit elements and inter-metal parasitic capacitances associated with the interconnecting
metal layers. The circuit extraction with parasitic capacitances may then be simulated on its own, or exported to a symbol with an attached netlist for simulation
with other subcircuits. The circuit extraction with parasitic capacitances may also
be exported to Agilent EESof Advanced Design System (ADS) using the Dynamic
Link program in Cadence. Performance simulation of the subcircuits on their own
and to other subcircuits used these circuit extractions with parasitic capacitances.
Passive circuits such as the tank inductors, interconnecting transmission lines, and
decoupling capacitors were first laid out in Cadence. The layouts were then exported
to Agilent ADS for simulation using Momentum. S-parameter files were generated
from the simulation, and then used for circuit simulation purposes.
5.3.2
Determination of Component Loop Constants
The calculation of the PLL open loop gain A(s)B(s) is dependent on several constants,
as seen in (3.45): the VCO gain constant K0 (rad/V), the phase detector gain constant
Kd (V/rad), the division factor N, and the loop filter 3-dB bandwidth ωL = 1/CR.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
114
The loop division factor N was set as part of the design criteria; the values of K0 and
Kd were determined by simulation, and the value of ωL was set to meet an open loop
unity gain bandwidth.
The linear VCO gain constant K0 in radians/volt was determined from resonant
frequency simulations versus input differential control voltages. Figure 5.9 displays
the simulated resonant frequency vs. differential control voltage for the VCO. For the
27.7
+
+
27.3
+
VCO Frequency
LS fit: K0=−0.785 GHz/V
VCO Freq. (GHz)
+
26.9
+
26.5
26.1
+
25.7
+
+
25.3
−1.6
−1.2
−0.8
−0.4
0.4
0
V diff. (V)
0.8
+
1.2
+
1.6
Figure 5.9: Simulated VCO Frequency vs. Differential Control Voltage
simulation, a full parasitic extraction of the VCO was used, as described in section
5.3.1. Passive structures such as the VCO tank inductor and interconnecting transmission lines and capacitors were simulated in EESof Momentum and included as
s-parameter files. Two-port s-parameters for the gate- and diffusion-biased varactors
at selected differential voltages over the operating voltage range were collected and
extracted for simulation purposes. A least-squares regression fit (the line LS Fit in
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
115
Figure 5.9) was applied to the simulated results. The VCO linear gain constant K0
was determined to be -0.785 GHz/V, or -4.932x109 rad/V.
A similar technique was used to determine the phase detector gain constant Kd
in V/rad. A full parasitic extraction of the phase detector core was simulated over
a range of input phase differences. Figure 5.10 shows the simulated differential output voltage versus input phase difference for the approximately linear portion of the
+
1.0
+
0.8
+
0.6
+
V_IF (V)
0.4
+
0.2
+
0
−0.2
+
−0.4
+
−0.6
+
+
−0.8
+
PD IF Voltage
LS Fit: KD=1.158 V/rad
+
−1.0
−1.8 −1.6 −1.4 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2
Phase Diff. (rad)
0
Figure 5.10: Simulated Phase Detector Output vs. Input Phase Difference
response in the vicinity of the zero crossing. A least-squares regression was used to
determine the phase detector gain constant Kd of 1.158 V/rad.
The lowpass filter 3-dB bandwidth was next calculated using the open loop gain
A(s)B(s) of (3.45) and setting the magnitude to 1 at a frequency of 2.34 MHz. The RC
time constant of the lowpass filter was determined to be 6.60x10−6 sec. A tradeoff in
the integrated circuit layout (resistor length versus capacitor area) led to the setting
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
116
of the lowpass R and C to 36.2 kΩ and 182.4 pF, respectively. This lowpass filter
has a 3-dB LPF bandwidth of (1/(2πRC) =) 24.1 kHz. The combination of the LPF
RC time constant and the other PLL loop constants (VCO gain constant K0 , phase
detector gain constant Kd and division factor N) are used to determine the locking
frequency ∆ωlock using either the linear approximation of (3.55) or the non-linear
solution using the phase plane analysis described in Section 3.2.1. The two LPF
capacitors occupy a large portion of the chip area (15.7%), as seen in Fig. 5.1.
5.3.3
Simulation
Simulation of the entire closed loop PLL was undertaken to determine transient and
steady-state performance parameters associated with the circuit. The ADS software
platform uses equivalent circuits for determination of phase-locked loop performance,
while the Cadence platform did not have any obvious PLL simulation components.
It was decided to simulate the PLL performance by using at the layout-generated
circuits to obtain a more representative simulation.
Transient parameters of interest included settling time, the PLL natural frequency
ωn and the damping factor ζ. The time domain analyses would also be used to
determine the locking bandwidth ∆ωlock based on initial conditions for phase and
frequency differences between the reference and divided VCO signals. Once a steady
state was achieved, a Periodic Steady State (PSS) analysis (in the case of Cadence
Spectre RF simulation) or a Harmonic Balance (HB) analysis (in the case of Agilent
EESof ADS simulation) would be undertaken to examine steady state performance
parameters such as tracking bandwidth ∆ωtrack and system output phase noise.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
117
The steady-state time domain solution in either platform is required as an initial starting point for harmonic-balance solutions. As such, considerable effort was
expended to develop a closed-loop time domain-convergent circuit analysis.
Time Domain Simulation
The top level performance was simulated using a combination of Agilent EESof Advanced Design System (ADS), Momentum and the Cadence suite for layout and
simulation.
Detailed layout was carried out using Cadence Virtuoso for the individual subcomponents and top level integrated assembly. Layout-generated extractions including
parasitic capacitances for each of the subcomponents were obtained using Cadence
Diva, and used for circuit simulation. Passive components such as the VCO and
ILFD tank inductors, VCO-to-ILFD transmission lines, ILFD-to-MSFF transmission
line/coupler/splitter, MSFF-to-PD transmission line/coupler and 1 pF blocking capacitors were simulated in Momentum and exported as s-parameter files.
A top level schematic was generated for simulation using Agilent EESof ADS and
the extracted subcomponents and s-parameter files. Extracted subcomponent netlists
were imported using Cadence Dynamic Link. Measured s-parameter data from varactor test circuits fabricated on earlier runs were used for the varactors for the ILFD
and VCO for open-loop calculations. A best-fit curve of varactor capacitance versus
bias voltage was used for the VCO varactors to allow for a continuous capacitance
response in the closed-loop simulations.
The goal of the simulation work was to use the Envelope analysis in ADS to
evaluate PLL steady-state and time-varying performance. As Envelope analysis is a
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
118
hybrid of time-domain and harmonic balance analyses, the planned analysis approach
was time-domain first (allowing for confirmation of steady-state solutions) followed
by Harmonic Balance (periodic steady-state) and Envelope (time-varying periodic
solution). The PLL circuit with fully-extracted sub-circuits, s-parameter files and
symbolically-defined devices (SDDs) was quite large and provided technical challenges
in simulation and computing that were not fully resolved.
Initial time domain investigations used Cadence Spectre RF as the top-level simulation tool. The software engine is time-domain based, necessitating S-parameter files
with data that extend from DC to (ideally) infinite frequency, as the inverse Fourier
transform for a function Y(ω) is [74]
1
y(t) =
2π
Z
∞
Y (ω)e−jωt dω.
(5.2)
−∞
S-parameter simulations for passive components such as transmission lines and tank
inductors were simulated adaptively in EESof Momentum from 0 to 70 GHz; this
was slightly less than three times the maximum designed operational frequency of
the VCO, and represented a tradeoff between a large frequency span and simulation
time. The measured varactor data was captured between 15 and 40 GHz, and proved
troublesome when using S-parameter representation. Cadence Spectre RF extrapolated the data to DC values, often resulting in non-physical (i.e., negative real) data
points. A limited number of extrapolated data points (typically 4) from 15 GHz to
DC were added to the data files to improve the extrapolation and avoid non-physical
values. The data was also thinned to every fourth data point (a spacing of 250 MHz)
for the captured data to reduce the extrapolation noise between data points.
A limitation of the time-domain based simulation in Cadence Spectre RF was
the circuit requirement to DC feed the VCO using large (but not infinite) inductors;
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
119
these feed inductors had a noticeable impact on the circuit performance in the time
domain, observed as a reduction in the nominal LC tank DC voltage.
Transient circuit analysis was continued in Agilent EEsof ADS. The subcircuits
with extracted parasitic capacitances were imported into ADS using Cadence Dynamic Link, and a full closed-loop PLL circuit was constructed. DC feeds were used
for biasing the VCO; simulations showed a steady LC tank DC voltage, as desired.
The size and complexity of the circuit as well as the under-damped characteristic
taxed the computing capabilities of ADS. A transient step size of twenty sample
points per period for the third harmonic of the VCO frequency t = 1/(20 · 3 · fV CO )
was selected to ensure that the fundamental and third harmonics of the VCO would
be captured for harmonic balance purposes. Simulated run times of 1 µsec assuming
a VCO frequency of 26 GHz would result in 1.56x106 data samples, causing memory
allocation issues. While there are techniques to decrease the amount of data held
(strobing the data and sampling all data only at the very end of the simulation time)
data manipulation is an issue with very large circuits such as the PLL examined.
Fig. 5.11 shows the output response for the PLL multiplier for a unit step input
u(t-0.2 µs) for both the current PLL frequency multiplier (“Lag LPF” curve) and for a
proposed lead-lag filter (“Lead-lag LPF” curve) that will be discussed in Section 7.2.4.
For these calculated responses, the assumed loop constants were K0 = 2π · 0.785 × 109
rad/V, Kd = 0.571 V/rad, N=4, R1=36.2 kΩ, R2=750 Ω and C=182.4 pF. The
“Lag LPF” response shows a lightly-damped sinusoidal response that is settling very
slowly. The “Lead-lag LPF” shows a critically-damped response that settles quickly
as a result of the additional R2 resistor in the loop filter. Both curves are converging
on an output magnitude of 4 that reflects the multiplication factor of the PLL.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
10
Lag LPF
R1
Lag LPF
Lead−lag LPF
9
120
Lead−lag LPF
R1
C1
R2
8
C1
Magnitude
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
Time (us)
7
8
9
10
Figure 5.11: PLL Input Frequency Step Response vs. Time
A simulated transient response was run for the VCO control line voltages. For this
case the LPF resistor R was 36.2 kΩ and the LPF capacitor C was set to 2 pF. The
much smaller value of the capacitor than in the final PLL design was selected to allow
the simulation to execute and converge in a more reasonable time.This simulation to
a stop time of 1 µs took approximately 24 hours to complete; based on the calculated
attenuation constant, steady state (as defined by a time equal to 5 time constants
τ ) would be achieve after 5 µs, or a simulation time of 5 days. For the design
LPF capacitor value of 182.4 pF and no assumed parasitic capacitive loading the 5τ
time would be 66 µs, with an approximate simulation time of 66 days. This is a
prohibitively long period of time for a typical PLL design and there are issues with
data storage, power continuity, and correct software operation. The simulated results
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
121
do show, however, that it is possible to simulate the PLL using layout-based fullyextracted subcircuits in combination with S-parameter measured and simulated data
files.
Frequency Domain Simulation
Simulation of the fully-extracted closed loop PLL in the frequency domain using Harmonic balance (HB) requires a steady state transient solution as a starting point.
Because of the limitations of the time domain simulation discussed previously, frequency domain analysis was not undertaken for the closed loop PLL.
Harmonic balance simulation was successfully run on the open loop PLL, using full
parasitic extractions for all sub-circuits, S-parameter simulations for interconnecting
transmission lines, and discrete bias-dependent S-parameter data files for the varactor
components. The HB simulation provides a good indication of the proper operation
of the individual sub-circuits. Figure 5.12 shows the derived time domain responses
from the harmonic balance simulation for the case where the VCO and ILFD are
locked. The VCO displays a resonant frequency of 25.972 GHz; the ILFD is phaseand frequency-locked to the VCO, displaying an output frequency of 12.986 GHz (one
half of the VCO frequency). The MSFF divider output tracks the ILFD input with
a frequency of 6.493 GHz. For the purpose of the simulation and convergence of the
HB analysis, the VCO was tuned slightly lower then its free-running frequency to
allow the ILFD to properly lock.
Figure 5.13 shows the derived PD output voltages VCOctrl pos and VCOctrl neg
versus time from the same HB simulation. A reference signal was injected at a
frequency of 6.493092195 GHz, and compared against the exact HB-determined MSFF
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
122
4.0
Magnitude (V)
3.4
2.8
2.2
1.6
VCO
1.0
280.0
280.1
280.2
280.3
Time (ns)
ILFD
280.4
MSFF
280.5
Figure 5.12: VCO Tank, ILFD Tank, and MSFF Divider Output Voltages vs. Time,
PLL Open Loop HB Simulation
divider output frequency of 6.49309219439633465 GHz in an effort to simulate a
near-locking condition for the closed-loop PLL. The expected VCOctrl post-filter
frequency is the difference of the reference and MSFF divider output frequencies
(0.60366535 Hz), which has a period of 1.66 sec, as seen in Fig. 5.13. The VCOctrl pos
and VCOctrl neg outputs are complementary, giving a degree of confidence in the
performance of the actual circuit.
5.3.4
Common-Mode Noise Rejection Verification
The differential design of the PLL is intended to provide a means of rejecting interfering signals in the form of common mode noise. This section will describe how an
interfering signal from another component on-chip or coupled into the VCO control or
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
123
3.6
Magnitude (V)
3.2
2.8
2.4
2.0
1.6
0.0
VCOctrl_pos
VCOctrl_neg
0.8
1.6
2.4
Time (s)
3.2
4.0
Figure 5.13: VCO Control Voltages vs. Time, PLL Open Loop HB Simulation
power lines via radiated or conducted susceptibility will affect the PLL output. The
means of measuring the ability of the PLL to reject these common mode interfering
signals will also be presented.
Angle Modulation by Interfering Signals
Consider the general equation for the PLL output signal, as shown in Eqn. (3.50)
and repeated here, assuming no amplitude modulation and a constant reference input
frequency.
Vout (t) = A cos(ω0 t + θo (t))
Under locked conditions, the injection of the phase deviation term θo (t) will result in
Vout (t) being angle modulated, i.e., Vout (t) will not be a pure sinusoid at frequency
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
124
ω0 but will display a dependence on the phase deviation term θo (t). Let θo (t) be an
undesired interfering signal, which may be injected into the PLL through the substrate
or by a combination of radiated and susceptibilities. Let θo (t) take the form
θo (t) = β sin(ωm t),
(5.3)
where ωm is the angular frequency of the interfering signal and β is the modulation
index of the signal. The resulting output signal is therefore
Vout (t) = A cos(ω0 t + β sin(ωm t)),
(5.4)
which may be expressed in complex exponential notation as
Vout (t) = A<[ejω0 t ejβ sin(ωm t) ]
(5.5)
where <[] denotes the real part of the complex representation. The factor ejβ sin(ωm t)
of (5.5) may be expanded as an infinite series involving the Bessel function of the first
kind of order n and argument β [74]:
jβ sin(ωm t)
e
n=∞
X
=
Jn (β)ejnωm t .
(5.6)
n=−∞
Combining (5.5) and (5.6) and taking the real part yields
Vout (t) = A
n=∞
X
Jn (β) cos(ω0 + nωm )t
(5.7)
n=−∞
which may be recognized as the general expression for an angle-modulated signal.
For the case examined, β is the maximum value of phase deviation [74], also referred
to as the modulation index; its magnitude will determine the depth of modulation of
the output signal. For β = 0 (the unmodulated case) (5.7) simplifies to the output
carrier Vout (t) = A cos ω0 t.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
125
The power ratio in dB between the angle-modulated nth sideband signal power
Pmod,n and the unmodulated carrier power Punmod may be written as
Pmod,n
(dB) = 10 log
Punmod
A2 Jn2 (β) cos2 (ω0 + nωm )t
A2 cos2 ω0 t
= 20 log Jn (β).
(5.8)
The representation of (5.7) shows that there are an infinite number of terms in the
expansion for an angle-modulated signal. However, not all will be significant. The
modulation index will determine the number of significant sidebands in an anglemodulated signal; the larger the modulation index, the greater the quantity of significant sidebands. Using Eq. (5.8) it is therefore possible to determine the modulation
index β of a signal by comparing the significant sideband modulated-to-unmodulated
signal power ratios to the associated Bessel functions of the first kind order n responses for the modulation elements 1 through n, where n is the number of significant
sidebands.
Common Mode vs. Differential Mode
The fully-differential nature of the PLL is designed to reject common-mode (CM)
noise which is coupled into the chip via radiated or conducted interfering signals. To
verify this performance characteristic, the spectrum of the un-modulated carrier signal
will first be measured. An interfering differential mode signal will then be injected at
the differential VCO control lines and the spectrum recorded. From this measurement
using (5.8) the differential mode modulation index βDM will be determined. An
interfering common mode signal of similar magnitude and frequency will then be
injected at the VCO control lines; using this measurement and (5.8) the common
mode modulation index βCM will be determined.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
126
The output voltage vo,opamp of an operational amplifier may be written as [75]
vo,opamp = ADM vIDM + ACM vICM ,
(5.9)
where ADM is the operational amplifier differential gain, vIDM is the input differential
voltage, ACM is the operational amplifier common mode gain, and vICM is the input
common mode voltage. The common mode rejection ratio (CMRR) is a measure of
the ability of the operational amplifier to reject common mode signals in preference
to differential signals and is represented by
CM RR = 20 log
|ADM |
|ACM |
.
(5.10)
At the PLL output, the modulation indices βDM and βCM represent the maximum phase deviations associated with differential mode and common mode signals,
respectively. The associated VCO input differential mode and common mode voltages
(VDM , VCM ) are
βDM
K0
βCM
=
,
K0
VDM =
VCM
(5.11)
where K0 is the VCO gain in rad/V. The CMRR for the PLL may then be calculated
by taking the ratio of the differential- and common-mode input voltages, as shown in
equation (5.12).
CM RR = 20 log
5.3.5
VDM
VCM
= 20 log
βDM
βCM
(5.12)
Analytical Phase Noise Determination
The original intent of the investigation was to use the harmonic balance steadystate simulation to determine the phase noise performance of the PLL multiplier.
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
127
Because of the challenges encountered in circuit simulation, an alternate means of
estimating the phase noise performance was undertaken. The phase noise of the PLL
output signal may be calculated by using closed loop linear transfer functions from
the location of injected noise within the circuit to the PLL output and measured or
characterized phase noise properties of the PLL components.
Kroupa [76] examined the contributions of noises generated in individual PLL subcircuits. Consider the PLL of Figure 5.14, with voltage noise sources and phase noise
sources identified for the phase detector (VP D (s)), loop filter (VF (s)), VCO (θV CO (s))
and frequency divider (θDivN (s)). The output phase noise may be written as
VPD (s)
PD
θ in(s)
+
Σ
+
KD
+
LPF
+
+
Σ
θ VCO (s)
VF (s)
Σ
F(s)
VCO
K0
s
+
+
Σ
θ out (s)
−
Divide−by−N
Σ
+
1
N
+
θ DivN (s)
Figure 5.14: PLL Block Diagram with Noise Sources
VP D (s) + VF (s)
Kd K0 F (s)/N s
·N
θout (s) =
θin (s) − θDivN (s) +
Kd
1 + Kd K0 F (s)
Ns
+ θV CO (s)
1
1+
Kd K0 F (s)
Ns
.
(5.13)
Under the assumption that the noise sources are random by nature and uncorrelated,
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
128
the respective spectral densities may be added as shown in (5.14),
#2
"
K
K
F
(s)/N
s
SV,P D (s) + SV,F (s)
d 0
· N2
Sθ,out (s) =
Sθ,in (s) + Sθ,DivN (s) +
Kd2
1 + Kd KN0sF (s)
#2
"
1
+ Sθ,V CO (s)
.
(5.14)
1 + Kd KN0sF (s)
where the phase-generated noise spectral densities Sθ (s) and the voltage-generated
noise spectral densities SV (s) are defined as
θ(s)2
bandwidth(= 1 Hz)
V (s)2
SV (s) =
bandwidth(= 1 Hz)
Sθ (s) =
rad2
Hz
V2
.
Hz
(5.15)
(5.16)
Let each of the sources be considered individually. For comparison purposes,
assume the VCO free-running phase noise spectral density at a 1 MHz offset is
3.16x10−14 rad2 /Hz (-105 dBm/Hz, assuming a 1 Ω load resistance), and the input reference phase noise spectral density at a 1 MHz offset is 1x10−15 rad2 /Hz (-120
dBm/Hz, 1 Ω load resistance ).
Phase Detector
Let each of the four LO switching stage transistors of the phase detector of Figure
4.9 be modeled as shown in Figure 5.15 [58], where i2nd is the MOSFET drain current
2 is the gate noise voltage source
noise spectral density for a drain current of ind , vng
of constant spectral density derived from the gate noise current ing and rg is a series
resistor of value
rg =
1
5gd0
(5.17)
where gd0 is the drain-source conductance at zero VDS . Although there is a known
correlation factor between the drain noise current ind and the gate noise current ing
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
v 2ng
g
129
rg
+ −
d
C gs
gm Vgs
i 2nd
s
Figure 5.15: MOS noise model
this will not be considered for this analysis to keep the analysis simple. The mean
square drain current noise spectral density i2nd and the mean square gate voltage noise
2 may be represented as
spectral density vng
i2nd = 4kT γgd0 ∆f +
K 2
ω Agate ∆f
f t
2
vng
= 4kT δrg ∆f ,
(5.18)
(5.19)
where k is Boltzmann’s constant, T is the temperature in Kelvin, γ is the transistor
noise coefficient, K is a device-specific constant, ωt = 2πft where ft is the short circuit
unity current gain frequency, Agate is the gate area, and δ is the gate noise coefficient
in long channel devices. At the output the current iv,ng due to the gate noise voltage
is
iv,ng =
gm vng
;
1 + jωCgs rg
(5.20)
The output mean square current noise spectral density due to gate noise voltage (i2v,ng )
is therefore
i2v,ng =
2
gm
· 4kT δrg ∆f.
1 + (ωCgs rg )2
(5.21)
The total mean square drain current noise spectral density i2nd,tot is therefore
i2nd,tot = 4kT γgd0 ∆f +
2
K 2
gm
· 4kT δrg ∆f.
ωt A∆f +
f
1 + (ωCgs rg )2
(5.22)
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
130
For the bias conditions of the NMOS LO switching stage transistor (10.28 µm gate
width W, Vds = 0.83V, Vgs = 0.69V) gm is 0.66x10−3 A/V. For the same transistor,
the drain-source conductance is 1/309 S. The gate-source capacitance Cgs is assumed
to consist solely of the overlap capacitance for the sake of simplicity and has a value
of
Cgs =
(3.9)(8.854 × 10−12 )(0.06 × 10−6 )(10.28 × 10−6 )
ox Aoverlap
=
= 5.22×10−15 F,
tox
4.08 × 10−9
where ox = 0 r,ox , 0 is the permeability of free space, r,ox is the relative permeability
of silicon oxide, tox is the oxide thickness, Aoverlap = W Loverlap is the gate/drain
overlap area and Loverlap is the gate-drain overlap length (assumed to be 0.06 µm)
[60]. Assume that T=290 K, γ = 2/3 (long channel approximation), K = 50 × 10−28
[58], f = 1 MHz, ft = 45 GHz, δ = 4/3, and ∆f = 1 Hz, (5.22) has a value of
i2nd,tot = 4(1.38 × 10−23 )(290)(2/3)(1/309)(1)
50 × 10−28
(2π45 × 109 )2 (0.18 × 10−6 )(10.28 × 10−6 )(1)
1 × 106
(0.66 × 10−3 )2
+
1 + (2π · 6.5 × 109 · 5.22 × 10−15 · 309/5)2
+
·4(1.38 × 10−23 )(290)(4/3)(309/5)(1)
= 7.75 × 10−22 A2 ;
the associated current noise spectral density in a 1 Hz BW is 7.75x10−22 A2 /Hz.
Assuming this noise current is seen directly across the phase detector drain resistance
of 1657 Ω and that in a worst case situation noise power from all four transistors
operating at a switching midpoint add up, the total noise power would be
Pn,total
dBm
dBm
dBm
= (10 log(4i2nd,tot (1657)) + 30)
= −142.9
Hz
Hz
Hz
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
131
As this noise is significantly lower than either the reference or VCO phase noise, it
will be disregarded.
Lowpass Filter
The lowpass filter noise is assumed to be dominated by the resistor. The voltagegenerated noise spectral density SV,F for the lowpass filter resistance may be written
using the Rayleigh-Jeans approximation as
SV,F = 4kT · R
(5.23)
When referred to the input of the PLL, the equivalent LPF phase noise spectral
density Sθ,F is
Sθ,F =
4kT · R
SV,F
=
.
2
Kd
Kd2
(5.24)
For the loop filter resistance of 36.2 kΩ, an ambient temperature of 290K, and a
phase detector constant of 1.158 V/rad, assuming a 1 Hz bandwidth and a 1 Ω load
resistor Sθ,F has a value of 4.32x10−16 W/Hz, or -123.6 dBm/Hz. This is significantly
lower than the assumed VCO free-running power spectral density, and less than the
reference phase noise power spectral density. As such, the contribution of the loop
filter will be ignored for this calculation.
Divider
The injection locked frequency divider is locked to the input VCO frequency. As such,
the phase noise output will be the input phase noise. It is assumed that the phase
noise is dominated by the input noise [76].
MSFF digital divider phase noise has been analyzed by Levantino et. al. [77] using
a latch structure similar to Fig. 3.16. The dual-sided phase noise spectral density of
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
the divider may be determined by
kT CL
γ γT gD0,T RL
2
Sθ,DivN = 2 · 8π · 1 + +
·
· fsample,out ,
α
2
IB2
132
(5.25)
where γ is the noise coefficient of the RF transconductance stage differential pair,
α is a constant less than 1, γT is the noise factor of the tail transistor, gD0,T is the
MOS drain-source conductance at zero VDS of the tail transistor [58], RL is the load
resistance, CL is the load capacitance, IB is the tail bias current, and fsample,out is
the frequency at which the the output phase is sampled. Assume all phase noise of
interest is within 2 times the PLL unity gain bandwidth of 2.34 MHz; if the Nyquist
sampling rate is used to capture this noise, the output sampling rate fsample,out will
be 2 · 2 · 2.34 MHz = 9.36 MHz. Assume an ambient temperature of 290K, IB at the
design current of 4.925 mA, CL of 247x10−15 F, RL of 50Ω, α = αT = 1, γ = γT = 2/3
(long channel assumption), and gD0,T = 1/50.3Ω for a tail transistor gate width of
70 µm. The double-sided phase noise power spectral density assuming a 1Ω load
resistance is calculated as
Sθ,DivN
2/3 (2/3)(1/50.3)(50)
+
= 2 · 8π · 1 +
1
2
(1.38 × 10−23 )(290)(247 × 10−15 )
· 9.36 × 106
·
−3
2
(4.923 × 10 )
2
= 1.20 × 10−19 W/Hz = −159.2 dBm/Hz
As this value is lower than the reference or free-running VCO phase noise power
spectral density the contribution from the divider will be ignored.
Phase Noise Contribution from VCO and Reference Signals
For the purpose of the analysis only the phase noise of the oscillator signals in the circuit (the reference input carrier Lref (∆ω) and the free-running VCO LV CO,f ree (∆ω))
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
133
will be considered. The VCO is a common realization and has not been designed
specifically for phase noise performance; as such, its phase noise performance is modest compared to other more aggressively designed VCOs. Additionally, the VCO-tooutput transfer function is highpass in nature, rendering the phase noise contribution
relatively low at low frequency offsets from the carrier. The reference-to-output transfer function is lowpass in nature, and includes the multiplication factor N; this factor
will dominate at low frequency offsets from the carrier.
The output phase noise Lout (∆ω) may be written as [47]
Lout (∆ω) = |H(i∆ω)|closed,I/P |2 Lref (∆ω) + |H(i∆ω)|closed,V CO |2 LV CO,f ree (∆ω),
(5.26)
where H(i∆ω)|closed,I/P and H(i∆ω)|closed,V CO are the closed-loop transfer functions
from the reference-to-output and VCO-to-output (described in Eqs. (3.47) and (3.48))
evaluated at the offset radian frequency ∆ω.
The magnitude of the Reference signal contribution for phase noise close to the
carrier is dependent on the phase noise of the Reference and the magnitude of
|H(i∆ω)|closed,I/P |2 . Consider the phase noise contribution from both the VCO and
the reference signal at a low frequency offset from the carrier. For frequency offsets
that are small (i.e., ∆ω << unity open loop gain bandwidth A(s)B(s)), (5.26) has a
value of
2
Kd K0
CR
Lout (∆ω) = 2
L (∆ω)
K
K
1
1
0
d
s + CR s + N CR ref
2
1
s(s
+
)
CR
+ 2
LV CO,f ree (∆ω)
Kd K0 1 1
s + CR
s + N CR
≈ N 2 Lref (∆ω)
(5.27)
For low values of offset frequency the output phase noise is effectively the input
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
134
reference noise multiplied by the square of the division factor N.
Selection of Reference Signal Generator
The selection of the Reference signal frequency and phase noise performance will have
a large effect on the output signal phase performance. Consider a 10 MHz crystal
oscillator with LCrystal (100 kHz) of -155 dBc/Hz, as listed in Table 2.2. The multiplied
phase noise contribution at 26 GHz using a division factor of N = 2600 is calculated
using Eq. (5.27) as
Lout (100kHz) ≈ 20 log(N 2 · LCrystal (100kHz))
= (−155 + 68.3) dBc/Hz = −86.7 dBc/Hz
(5.28)
A similar calculation for a DRO from Table 2.2 at 6.5 GHz with a LDRO (100 kHz)
of -119 dBc/Hz and a division factor of N = 4 results in a multiplied phase noise
contribution at 26 GHz of
Lout (100kHz) ≈ 20 log(N 2 · LDRO (100kHz))
= (−119 + 12) dBc/Hz = −107 dBc/Hz.
(5.29)
The DRO multiplication of (5.29) shows a significantly lower phase noise contribution
at 26 GHz than the crystal oscillator multiplication of (5.28). If the phase noise of
the reference is lower and/or the operational frequency is higher, such as for the 100
MHz crystal oscillator listed in Table 2.2 with L(100 kHz) of -172 dBc/Hz the phase
noise can be significantly improved, as shown in Eq. (5.30).
Lout,26GHz (100kHz) ≈ 20 log(N 2 · Lout,100M Hz (100kHz))
= (−172 + 48.3) dBc/Hz = −123.7 dBc/Hz
(5.30)
CHAPTER 5. PHASE LOCK LOOP - TOP LEVEL
135
Higher performance in terms of frequency and phase noise usually is accompanied
by a higher cost, resulting in a performance-cost tradeoff. The important conclusion
from a design standpoint is that for a given phase noise requirement, at the multiplied frequency it is possible to trade off the reference phase noise requirements
and the multiplication factor N: for higher N improved phase noise performance will
be required; for lower N reduced requirements on phase noise performance may be
tolerated.
Chapter 6
Results
6.1
Introduction
The Results chapter is divided into three sections. The first is the component verification section, composed of the voltage controlled oscillator (VCO), the injection-locked
frequency divider (ILFD), the master-slave flip-flop divider (MSFF), and the phase
detector (PD). The second section presents the measured results from the integrated
phase-locked loop (PLL). The third section analyzes the accuracy of analytical calculations and simulations.
6.2
Test Equipment Setup
Performance testing of the PLL and integrated sub-circuits was carried out at the
Very High Speed Circuits (VHSC) Laboratory at Queen’s University. The integrated
circuit was tested on a Wentworth Labs probe station using dual- and single-head
ground-signal-ground (GSG) probes for input and output radio frequency (RF) signals
136
CHAPTER 6. RESULTS
137
Equipment
Spectrum Analyzer
Manufacturer and P/N
Agilent E4446A
Vector Network Analyzer
Agilent 8510C
Signal Generator
Anritsu MG3694A
Function
Spectral Analysis,
Phase Noise
Insertion Loss,
Return Loss
RF Signal Generation
Table 6.1: Major Test Equipment - PLL Performance Verification
and DC biasing. DC supply voltages and control signals were fed to the circuit using
single pin probes and a 6-contact wedge assembly. DC power was supplied from a
combination of battery-based variable DC supplies (to minimize noise pickup from 60
Hz power lines and minimize switching noise) and regulated DC supplies (specifically
for the ILFD varactor tuning voltages).
Table 6.1 lists the major pieces of test equipment used in the performance investigation. The complementary Reference signal input to the PLL was achieved by
feeding the output from an Anritsu MG3694A signal generator to a 180◦ -hybrid (Electromagnetic Technologies Industries P/N HY226-180, operational frequency 2-26.5
GHz). Equi-phase semi-rigid coaxial cables connected the 180◦ -hybrid complementary outputs to their respective dual-head probes for injection into the PLL circuit.
The PLL uses two DC voltage rails: 4.3 V and 2.8 V. The VCO operates using
the 2.8 V rail, while the ILFD, MSFF divider, and PD operate from the 4.3 V rail.
These rail voltages are higher than normally used for several reasons. Tail transistors
have been incorporated in each of the main PLL subcomponents to allow individual
control of the circuits for testing purposes. The second reason was to allow sufficient
headroom for the ILFD PMOS neg-gm cell while setting the tank voltage of the ILFD
to be the same as the VCO tank voltage for proper input switch operation.
Because of the high 4.3 V rail it was necessary at power-up to increase the voltage
CHAPTER 6. RESULTS
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
DC Supply/Control Line
DC-1 to 1V
DC-2 to 1V
DC-5,DC-6 to 1V
DC-1 to 2V
DC-2 to 2V
DC-5,DC-6 to 2V
DC-3 to 0.4 V
DC-4,DC-7,DC-8 to 0.4 V
DC-1 to 3V
DC-2 to 2.8V
DC-5,DC-6 to 2.8V
DC-1 to 4.3V
DC-8 ↑ until ∆IDC−1 =1.2 mA
DC-3 ↑ until ∆IDC−2 =15 mA
DC-4 ↑ until ∆IDC−1 =15 mA
DC-7 ↑ until ∆IDC−1 =15 mA
138
Notes
DC-1 = 4.3 V rail
DC-2 = 2.8 V rail
IDC−1 ≈ 26 mA
IDC−2 ≈ 0.45 mA
IDC−2 slight increase
IDC−1 slight increase
IDC−2 ≈ 0.7 mA
IDC−1 ≈ 56-60 mA
IDC−2 (tot) ≈15.7 mA
IDC−1 (tot) ≈87-91 mA
Table 6.2: Test Equipment - PLL Power-up Sequence. DC pins and referenced power
supplies are shown in Figure 6.1.
rails and selected control lines of the PLL gradually so as not to damage the circuit.
The power-up process is listed in Table 6.2.
Each of the major sub-circuits of the PLL (VCO, ILFD, MSFF and PD) could be
controlled independently via a tail transistor bias. Depending on the testing carried
out (sub-circuit verification or full PLL performance measurement) some or all of the
steps identified in Table 6.2 were executed.
Figure 6.1 shows the test setup used for measurement of PLL phase noise, frequency locking and tracking. The test setup of Figure 6.1 also provided the basis
for sub-circuit verification, with some minor differences that will be identified as the
measurement results are discussed.
CHAPTER 6. RESULTS
139
PSU
DC−2
1
2
3
4
5
6
PSU
Buff
Dual GSG Probe
RESET
Ammeter
VCOctrl_pos
2.8V DC
DC Probe
4.3V DC
VCO_neg
ILFD_tail
PSU
DC−1
REF_neg
ILFDvar_neg
180
ILFDvar_pos
Σ
VCO_pos
MSFF_tail
HY226−180
(2)
REF_pos
PD_tail
0
Dual GSG Probe
Coax Cable
180o Equiphase
Hybrid
Coax
Spec. A.
E4446A
GSG Probe
DC Probe
Sig. Gen.
MG3694A
∆
Coax Cable
VCO_tail
Ammeter
PSU
DC−3
Bias Tee
Coax Cable
VCOctrl_neg
Multipin DC Probe
PSU PSU PSU PSU PSU PSU
DC−8 DC−7 DC−6 DC−5 DC−4 DC−1
Figure 6.1: Test Setup - PLL Phase Noise, Tracking and Locking Bandwidth
6.3
6.3.1
Component Performance Verification
Voltage-Controlled Oscillator
VCO Tuning Range
The VCO in the integrated PLL was tested for operational frequency range versus
differential voltage. The full testing setup of Figure 6.1 was used, with the addition
of 2 DC pin probes at the pads VCOctrl pos and VCOctrl neg as shown in Fig. 6.1 or
Fig. 5.1. These pads allow the voltage at the VCO varactors to be applied externally;
CHAPTER 6. RESULTS
140
Fig. 4.1 shows the VCO control line interfaces. The PLL was partially powered
up (Table 6.2, steps 1-11) and the DC voltage at the VCO tank was determined.
Control voltages were then set at the VCOctrl pos and VCOctrl neg access pads
and the operational frequency of the VCO noted. Differential control voltages were
calculated by
Vdif f = V COctrl pos − V COctrl neg.
(6.1)
Figure 6.2 shows the measured frequency range of the VCO versus the differential
control voltage and the least-squares regression fit for the data. For comparison’s
sake the simulated VCO frequency range versus differential control voltage of Fig.
5.9 has been included. The VCO displays a measured tuning range of 11.5% with
28.50
28.15
+
+
+
+
Frequency (GHz)
27.80
27.45
27.10
26.75
♦
♦
♦
VCO Frequency (meas.)
VCO Frequency (sim.)
LS fit (meas): K0=−0.871 GHz/V
+
♦
+
♦
26.40
+
26.05
♦
25.70
+
♦
25.35
25.00
−2.5 −2.0 −1.5 −1.0 −0.5 0.0 0.5
V diff. (V)
+
♦
1.0
♦
+
♦
+
1.5
+
2.0
2.5
Figure 6.2: Integrated PLL - VCO Tuning Range vs. Differential Control Voltage
respect to the zero-bias operational frequency of 26.34 GHz. The locking range of the
PLL falls comfortably within this range as will be shown in section 6.4.1.
The VCO gain constant K0 was determined from the LS fit to have a value of
-0.871 GHz/V, or −5.473 × 109 rad/V. This value is 10% higher than the simulated
CHAPTER 6. RESULTS
141
value of -0.785 GHz/V; the lower value for simulated K0 is attributed to inaccuracies
in the extraction of the s-parameters for the varactors.
VCO Free-running Phase Noise
Central to the estimation of the integrated PLL phase noise is the determination of
the VCO free-running phase noise spectrum. This is required as part of the noise
transfer calculations carried out on the PLL as a whole for the closed-loop transfer
function. The VCO free-running phase noise spectrum was determined using the
injection-locking method [78], necessitated by the low quality factor (Q) of the VCO
tank. The phase noise spectral density as a function of offset frequency ∆ω of the
locked VCO signal < δφ2V CO,lock (∆ω) > is composed of phase noise contributions from
the free-running oscillator < δφ2V CO,f ree (∆ω) > and the injected signal < δφ2inj (∆ω) >
[78],
< δφ2lock (∆ω) >=
4∆ω 2 < δφ2f ree (∆ω) > +∆ωV2 CO,lock cos2 (Φdetune ) < δφ2inj (∆ω) >
,
4∆ω 2 + ∆ωV2 CO,lock cos2 (Φdetune )
(6.2)
where ∆ωV CO,lock is the injection locking bandwidth and Φdetune is the phase difference
between the free-running and injected signals. Once the injection locking bandwidth
is determined the injected signal is set to the frequency of the free-running signal and
Φdetune becomes 0 radians, simplifying (6.2) as follows:
<
δφ2lock (∆ω)
4∆ω 2 < δφ2f ree (∆ω) > +∆ωV2 CO,lock < δφ2inj (∆ω) >
>=
.
4∆ω 2 + ∆ωV2 CO,lock
(6.3)
Rearranging (6.3) yields an equation that provides the free-running phase noise
as a function of locked and injected signal phase noise spectral densities:
< δφ2f ree (∆ω) >=< δφ2lock (∆ω) > +
∆ωV2 CO,lock
(< δφ2lock (∆ω) > − < δφ2inj (∆ω) >).
4∆ω 2
(6.4)
CHAPTER 6. RESULTS
142
Injection of the locking signal has been reported at both the output of the VCO
via a buffer [78] and at the VCO tail transistor gate [52]. For the designed PLL a
probe point is included that allows for injection of the locking signal into the VCO
tail transistor gate. Figure 6.3 shows the test setup for the VCO free-running phase
noise determination.
Bias Tee
Sig. Gen.
MG3694A
Coax Cable
PSU
DC−3
VCO_pos
ILFDvar_pos
ILFDvar_neg
ILFD_tail
RESET
1
VCO_neg
MSFF_tail
Ammeter
DC Probe
4.3V DC
PD_tail
REF_neg
2
3
4 5
6
PSU
Buff
Dual GSG Probe
VCO_tail
REF_pos
PSU
DC−1
Spec. A.
E4446A
GSG Probe
DC Probe
2.8V DC
Ammeter
VCOctrl_pos
PSU
DC−2
Bias Tee
Coax Cable
VCOctrl_neg
Multipin DC Probe
PSU PSU PSU PSU PSU PSU
DC−8 DC−7 DC−6 DC−5 DC−4 DC−1
Figure 6.3: Test Setup, VCO Free-running Phase Noise
The single-sided phase noise power spectral densities for the injection-locked VCO
CHAPTER 6. RESULTS
143
(LV CO,lock (∆ω)) and injected reference carrier (Lref (∆ω)) were measured using the
phase noise personality of the spectrum analyzer. Figure 6.4(a) shows the single-sided
phase noise power spectral density of the injection-locked VCO LV CO,lock (∆ω) while
Figure 6.4(b) shows the single sided phase noise power spectral density of the injected
reference carrier Lref (∆ω).
The free-running VCO frequency was determined to be approximately 26.323 GHz.
A signal at 26.3228 GHz and signal generator output power of 0 dBm were used for the
locking verification. A bias tee and coaxial cable were used to inject the VCO tail DC
voltage and the RF locking signal at the VCO tail probe input. Measured loss of the
bias tee and coaxial cable was 3.40 dB at 6.5 GHz, resulting in an injected power level
of -3.40 dBm at the VCO tail probe input. The locking bandwidth ∆ωV CO,lock was
determined through measurement to be 2π Mrad/sec (1 MHz). The free-running VCO
phase noise spectrum was calculated using Eq. (6.4); Figure 6.5 shows the calculated
free-running VCO single-sided phase noise power spectral density LV CO,f ree (∆ω).
The VCO free-running phase noise power spectral density of Figure 6.5 shows
phase noise of approximately -100 dBc/Hz at a 1 MHz offset frequency. This value of
phase noise is comparable to the reported phase noise measurements for VCOs in the
20 GHz range of Section 2.3.1. Output power for the VCO is -28 dBm at the VNA;
accounting for cable and bias tee loss (3.82 dB), probe loss (0.62 dB) and loss in the
common-drain output buffer amp (8.06 dB), the power at the VCO tank (PV CO,tank )
was -15.5 dBm. The VCO consumes 42 mW of power from the 2.8 V supply. As the
noise transfer function of the closed loop PLL is highpass in nature from the VCO
output and lowpass in nature from the reference input, the phase noise at low offset
frequencies will be dominated by the injected reference phase noise, as discussed in
CHAPTER 6. RESULTS
144
50
30
Phase Noise dBc/Hz
10
−10
−30
−50
−70
−90
−110
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×
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×
×
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×××××××××××
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×
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×
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×
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×
×××××××
×
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×
×
×
××××××××
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××××××××
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××××××
×
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×
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×
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×
×××××
×
××
×
× ×× × ×××
−130
−150
2
3
10
10
4
5
10
10
Frequency (Hz)
6
10
7
10
(a)
50
30
Phase Noise dBc/Hz
10
−10
−30
−50
−70 ⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕⊕
−90
−110
−130
−150
10
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2
3
10
4
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10
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6
10
7
10
(b)
Figure 6.4: VCO Phase Noise (a) Injection-Locked VCO, (b) Injected Reference Carrier
CHAPTER 6. RESULTS
145
50
30
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10
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−130
−150
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2
3
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4
5
10
10
Frequency (Hz)
6
10
7
10
Figure 6.5: VCO Free-Running Phase Noise (extracted using Eq. 6.4)
Section 3.6.2.
6.3.2
Injection-Locked Frequency Divider
The injection-locked frequency divider (ILFD) serves to divide the VCO output signal
frequency by two. As a tuned element, the ILFD frequency alignment and locking
bandwidth is critical to the proper operation of the PLL system. Verification of the
tuning range and locking bandwidth confirmed the suitability of the design for the
PLL designed.
CHAPTER 6. RESULTS
146
ILFD Tuning Range
The tuning range of the ILFD was determined by varying the differential control
voltage to the ILFD varactors (ILFDvar pos, ILFDvar neg) and observing the ILFD
output frequency with the VCO and PD circuits disabled (Table 6.2, steps 1-9, 1213). The test setup of Figure 6.1 was used for testing the ILFD tuning range. Figure
6.6 shows the ILFD operational frequency range. The ILFD has a total tuning range
13.6
+
13.4
+
+
+
+
Frequency (GHz)
+
+
13.2
+
13.0
+
+
12.8
+
12.6
+
+
+
+
12.4
−4
−3
−2
−1
0
1
ILFD Differential Tuning Voltage (V)
2
Figure 6.6: ILFD Tuning Range
of 12.45 - 13.41 GHz, with a zero differential bias operational frequency of 12.81 GHz
and a common mode voltage of 2.4 V. This range is adequate to tune the ILFD such
that it locks to the nominal zero-bias frequency of the VCO reported in 6.3.1.
CHAPTER 6. RESULTS
147
ILFD Locking Range
The locking range of the ILFD in the circuit was also verified. Using the test setup
of Figure 6.1, the ILFD and VCO were powered up, with the phase detector and
MSFF divider sub-circuits disabled (Table 6.2, steps 1-9, 11-12). A differential bias
voltage was manually applied to the VCO control lines (VCOctrl pos, VCOctrl neg)
via single DC probe pins to vary the VCO frequency. The VCO for this test had
a zero-differential bias free-running frequency of 26.433 GHz. The ILFD differential
control voltage was varied until the ILFD locked to the VCO frequency. The ILFD
differential control voltage was not varied for the duration of the test.
Measured input locking range was 26.22 to 27.01 GHz (13.11-13.505 GHz at the
ILFD output and 6.555-6.753 GHz at the PD operational frequency). Locking bandwidth was 0.79 GHz at the ILFD input (0.395 GHz at the ILFD output and 0.1975
GHz at the PD). The ILFD locking bandwidth is important in the overall operation
of the PLL, as it is a limiting factor to the circuit performance.
The ILFD output power was measured at the ILFD sample output of Fig. 5.1(a).
Losses between the circuit probe and the spectrum analyzer at 13.2 GHz were 2.3
dB for the cable and bias tee. The sample buffer amplifier had a loss of 8.4 dB,
and the coupler had a coupling factor of 36.5 dB, as listed in Table 5.1. For a
measured sample power of -38.4 dBm, the associated ILFD power after the in-line
buffer amplifier (PILF D,Buf ) is
PILF D,Buf (dBm) = −38.4dBm + 2.3dB + 8.4dB + 36.5dB = +8.8dBm.
DC power consumed by the ILFD core circuit was 65 mW from the 4.3 V DC supply.
CHAPTER 6. RESULTS
6.3.3
148
Master-Slave Flip-Flop Divider
As part of the ILFD tuning range investigation presented in Section 6.3.2, the MSFF
divider output was monitored at one-half of the ILFD output frequency. The MSFF
output frequency tracked the ILFD input over the entire ILFD tuning range (input
frequency 12.45-13.41 GHz, MSFF divider output frequency 6.225-6.705 GHz), confirming the proper operation of the MSFF divider. Output power was measured at
the MSFF sample port of Fig. 5.1(a). Losses between the circuit probe and the
spectrum analyzer at 6.5 GHz were 5.7 dB. The buffer amplifier had a loss of 8.5 dB,
and the coupler had a coupling factor of 42.0 dB at 6.52 GHz , as listed in Table
5.1. For a measured sample power of -40.0 dBm, the associated MSFF output power
(PM SF F,output ) is
PM SF F,output (dBm) = −40.0dBm + 5.7dB + 8.5dB + 42.0dB = +16.2dBm.
Tail current used by the MSFF was initially simulated to be 11 mA. During
testing, it was observed that the specified current resulted in marginal MSFF divider
performance, i.e., the divider did not output a strong consistent signal at one-half the
ILFD frequency. When the current was increased to 15 mA, the MSFF output signal
came up consistently. DC power consumption with the 15 mA tail current draw was
68 mW from the 4.3 V source.
6.3.4
Phase Detector
The magnitude and means of controlling static phase offset were investigated recently
[53]. Circuit performance of the PD core was simulated in Cadence Virtuoso-Spectre
using a layout parasitic capacitance (Cpar ) extraction. Figure 6.7 shows the equipment
CHAPTER 6. RESULTS
149
setup for the performance verification. The test setup allows for setting of the relative
phases of the signals input to the PD. The test setup resulted in amplitude imbalances
between the four output ports because of imbalance in the couplers and splitters and
slightly different losses in the cables. This was accounted for in the simulation by
180o Hybrid
Sig. Gen.
Anritsu 3694A
Branch B
φ
RF − 0o
φ
Phase Shifter
φ
RF − 180o
RF+
RF−
IF+
LO −180o
LO−
LO+
Phase Shifter
3−dB Hybrid
Branch A
3−dB Hybrid
φ
DUT
IF−
+
Vdc
−
LO −0o
Phase Shifter
Agilent 8510C
VNA
Figure 6.7: Test Setup, Gilbert Cell Phase Detector
specifying the incident voltage at each PD chip input as calculated from path loss
and reflection coefficient measurements at the coaxial input probe points.
Fig. 6.8 shows simulated (including layout parasitics) and measured PD outputs
for fi,LO = fi,RF = 6.5 GHz. The measured differential results show good agreement
with the simulation and confirm the simulated static phase shift discussed in Section
4.4. The slight misalignment of the measured PD response slopes and magnitudes is
attributed to differences in the calculated and actual test port incident powers due
to power calculations being carried out at the coaxial interface ports and not at the
actual IC test probe tips.
Fig. 6.9 [70] shows the dependency of ΦO to the total current drawn by the PD
at 6.5 GHz. The upper solid curve shows simulated ΦO from the extracted circuit
CHAPTER 6. RESULTS
150
0.9
Detector Output (V)
0.7
0.5
0.3
0.1
−0.1
−0.3
−0.5
−0.7
×
Simulated
Measured
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
−0.9
−200 −160 −120 −80 −40
0
40
80
Differential Phase (deg)
120
160
200
Figure 6.8: Gilbert Cell PD output versus RF-LO phase difference, PD current =
2.63 mA, Freq. = 6.5 GHz
including the effects of layout parasitic capacitance (Cpar ) over a range of PD currents.
The measured results, taken several times on the same chip to give an idea of the
amount of measurement variation, show good agreement, with average percentage
differences of less then 7%.
The lower solid curve displays simulated ΦO for the same PD current range but
without the effects of layout Cpar . Analytical calculations for Φ0,tr from (4.6) using
the total PD current display similar dependence, with a maximum difference between
calculated and simulated values of 12%. The variation between the analytical calculations and the simulation results is attributed to the use of (4.7) for determination
of the required bias conditions. The results do, however, give a good estimate of
Φ0,tr for the circuit examined. Fig. 6.9 confirms that it is possible to decrease the
static phase offset by a factor of > 20% for an increase in PD current of 44%, with a
CHAPTER 6. RESULTS
151
50
46
42
+
×
+
∆Φ0 (deg)
38
+
♦
⊕
⊕
⊕
34
30
Simulated − with Layout Cp
Measured
Simulated − No Layout Cp
∆Φ0,tr calculated as per (6)
⊕
⊕
⊕
+
+
×
×
♦
♦
26
×
♦
22
×
♦
+
×
♦
⊕
⊕
⊕
⊕
+
♦
×
+
+
♦
×
+
♦
×
♦
×
18
14
10
2.6
2.8
3.0
3.2
3.4 3.6 3.8 4.0
Total PD Current (mA)
4.2
4.4
4.6
Figure 6.9: Static Phase Shift vs. PD Total Current: Simulated, Measured, Calculated
corresponding increase in simulated locking bandwidth to 96% of the ideal case.
The phase detector consumed 11 mW of power from the 4.3 V source.
6.4
Integrated PLL measurements
For operational PLL testing, the setup of Figure 6.1 was used. All sub-circuits were
powered up, following Table 6.2, steps 1-13. After successful circuit power up, the
ILFD frequency was adjusted via the ILFD differential controls (ILFDvar pos, ILFDvar neg) until the ILFD output frequency locked to one half the observed VCO
frequency. The VCO output frequency was then noted, and a Reference signal at one
quarter of the VCO frequency was injected. Lock was confirmed by varying the Reference input frequency and observing the PLL output signal changing by a factor of
4. The Reference input power was varied until the observed output spectrum showed
CHAPTER 6. RESULTS
152
minimal sideband levels and the maximum spacing between the VCO carrier and
the adjacent spectral peak (a result of the gain peaking caused by the underdamped
nature of the PLL, as identified in Section 3.6.2).
Fig. 6.10 shows a representative frequency domain plot for the PLL output in a
locked state. The PLL loop corner peaking is evident in close proximity to the carrier
signal. For this particular measurement the PLL output signal was -25.3 dBm at a
carrier frequency of 26.544 GHz.
−20
fosc=26.544 GHz
Amplitude (dBm)
−30
−40
−50
−60
−70
−80
−90
26.533
26.537
26.541 26.545 26.549
Frequency (GHz)
26.553
26.557
Figure 6.10: PLL Output Signal, Frequency Domain
Table 6.3 compares the results reported in [6] and [7] with this work. The work
presented had several design features that contributed to the higher power consumption. Extra circuitry has been incorporated in this work to allow testing of individual
sub-circuits, leading to the use of higher value voltage rails and greater DC power.
Additionally, the VCO and ILFD designs were designed using conservative design
CHAPTER 6. RESULTS
Parameter
CMOS Process
Reference Frequency
Output Frequency
VCO tuning range
Phase Noise
Supply Voltage
Power
153
[6]
0.18 µm CMOS
2.488 GHz
9.953 GHz
N/A
[7]
0.18 µm CMOS
12.1 GHz
24.2 GHz
6%
This work
0.18 µm CMOS
6.575 GHz
26.3 GHz
2.25%
-108dBc/Hz@1MHz
-117dBc/Hz@1MHz
-103.9dBc/Hz@1MHz
1.8 V
77 mW
1V
17.5 mW
2.8 / 4.3 V
186 mW
Table 6.3: PLL - Performance comparison
techniques to assure oscillation and were over-designed. The selection of the singlepole lowpass filter had a strong effect on the phase noise transfer functions that could
have potentially been reduced.
6.4.1
Locking and Tracking Bandwidths
Locking and tracking bandwidths for the PLL were measured in a series of tests on a
single chip. Three combined trials were carried out and the locking and tracking frequency ranges noted. Further explanation of the measurement technique is contained
in the following sections.
Locking Bandwidth
To determine the locking bandwidth, the PLL was set initially in an unlocked state
with the ILFD output frequency at one-half of the free-running VCO frequency. The
reference signal was then increased(decreased) in frequency until the PLL entered a
locked state, observable by the VCO output frequency being four times the reference
frequency. This first lower(upper) locking frequency value was noted. The reference
frequency was then set higher(lower) than the free-running VCO frequency such that
CHAPTER 6. RESULTS
154
the PLL was again out-of-lock. The frequency was decreased(increased) until PLL
lock was acquired, with the second upper(lower) lock frequency noted. The difference
between the upper and lower locking frequencies is the locking bandwidth of the PLL,
BWlock .
Table 6.4 gives the upper and lower locking frequencies (∆flock ) relative to the
locked input reference frequency fref,lock , as well as the total locking bandwidth
(BWLock ). The locking range is taken to be symmetric about the nominal VCO
Trial Min/Max ∆flock (MHz)
1
-8/+0
2
-8/+0
3
-8/+0
BWlock (MHz)
8
8
8
fref,lock (GHz)
6.627
6.627
6.627
Table 6.4: Input-Referenced Locking Bandwidth Results
centre frequency divided by N. For the cases of Table 6.4, this translates to a VCO/4
frequency of 6.623 GHz and a locking bandwidth of ±4 MHz. The predicted locking
bandwidth using (3.55) was ±2.34 MHz, which did not consider effects such as static
phase offset in the phase detector.
A phase plane analysis can be used to graphically determine the PLL locking
bandwidth. This investigation was undertaken using the design values for the various
loop constants: R=36.2 kΩ, C=182.4 pF, VCO constant K0 = 2π · 0.785 × 109 rad/V,
PD constant Kd =1.158 V/rad and loop division factor N=4. A static phase offset
of 0.7 rad was included in the analysis to account for non-ideal performance of the
phase detector. The reference and VCO initial phase offsets were both assumed to
be 0 radians. The phase plane analysis predicts a locking bandwidth of ±4.37 MHz,
for a percentage error of 9%.
CHAPTER 6. RESULTS
155
Tracking Range
From a PLL locked state, the input reference signal was increased(decreased) in 1
MHz steps until the PLL output signal no longer tracked the reference frequency. The
maximum(minimum) tracking frequency was noted. The reference frequency was then
decreased(increased) in 1 MHz steps until the PLL re-acquired lock. While still in
the locked state,the reference frequency continued to be decreased(increased) until the
PLL was no longer able to track the input reference signal; the minimum(maximum)
tracking frequency was noted. The difference between the maximum and minimum
tracking frequencies was the PLL tracking bandwidth, BWtrack . For the purpose of
the measurements, all frequencies are relative to the input reference frequency.
Table 6.5 shows measured input-referenced tracking results. It was observed durTrial Min/Max ∆ftrack (MHz)
1
-44/+61
2
-69/+72
3
-76/+72
BWtrack (MHz)
105
141
148
fref,lock (GHz)
6.627
6.627
6.627
Table 6.5: Input-Referenced Tracking Bandwidth Results
ing tracking testing that as the Reference frequency was stepped to values close to
the operational limits of the circuit (specifically the ILFD operational bandwidth),
time between the frequency steps had to be included to allow the PLL to settle. This
is attributed to longer settling time as the PLL is on the verge of locking.
The theoretical tracking bandwidth, estimated by Eq. (3.60), is ∆ftrack = ±226
MHz, and is calculated at the operational frequency of the PD inputs (1/4 of the PLL
output frequency). This translates to an input-referenced tracking range of 6.397 6.849 GHz (or 452 MHz), using the divided-by-4 VCO zero-bias centre frequency of
6.623 GHz. At the PLL VCO output this would correspond to a range of 25.588 -
CHAPTER 6. RESULTS
156
27.396 GHz. This theoretical range is contained within the measured VCO tuning
range identified in Fig. 6.2.
The calculated tracking bandwidth assumes that there is no limiting bandwidth
imposed by another device within the PLL. For the implemented PLL, the ILFD at
a set frequency has an input-referenced locking range of 6.555 - 6.753 GHz, as shown
in section 6.3.2. This is less than the theoretical tracking bandwidth of the PLL, and
will limit the PLL tracking bandwidth performance. For reference frequencies outside
of the ILFD input-referenced locking range the ILFD will not track the VCO signal
and the PLL will lose lock.
The maximum measured input-referenced tracking range of the operational PLL
was 6.551 - 6.699 GHz. The measured lower PLL tracking limit corresponds closely
to the lower measured input-referenced locking limit of the ILFD discussed in Section 6.3.2. The measured input-referenced upper PLL tracking limit was lower by
approximately 50 MHz compared to the measured upper locking limit of the ILFD.
This is attributed to the ILFD nominal oscillation frequency being slightly lower then
one half the VCO frequency as a result of unmodeled parasitic capacitances or slight
inaccuracies in the EM model of the varactor loop. The ILFD is being operated close
to its upper tuning limit and is also close to the maximum upper locking limit of the
ILFD/VCO combination. The measurement confirms that the tracking bandwidth of
the PLL is limited by the operational bandwidth of the ILFD.
While it is possible for the PLL to track over a reference frequency range of 6.551
- 6.699 GHz, the maximum step size so as not to lose lock is limited to one half the
locking bandwidth. Stepping at greater than one half the locking bandwidth would
result in an initial condition for frequency outside the locking boundary identified
CHAPTER 6. RESULTS
157
in the phase plane analysis, resulting in a loss of lock. This must be considered if
large frequency steps are required in a practical PLL. A possible solution would be
to use a combined phase-frequency detector, as discussed in Section 4.4 although its
performance under large frequency changes is beyond the scope of this work.
6.4.2
Common Mode Interference Rejection
The design of the PLL, as indicated in section 5.2, is fully differential to reduce the
potential effect of common mode interference. To evaluate the design effectiveness the
common mode rejection ratio (CMRR), as outlined in Section 5.3.4, was evaluated for
discrete carrier injection. The case of broadband noise injection was also measured.
The setup of Fig. 6.1 was used, and the PLL was fully powered (Table 6.2, steps
1-13) and locked to the Reference. Using single pin probes, common mode (CM)
and differential mode (DM) signals were injected into the VCO control test points
(VCOctrl pos, VCOctrl neg). Pin probes were used for this measurement because of
the low frequencies and bandwidth (less than 5 MHz) of the injected noise signals.
Figure 6.11 shows the equipment setups used to generate the discrete carrier and
broadband DM and CM noise signals.
Discrete Carrier Injection
When continuous wave (CW) sinusoidal signals were injected at the VCO control
lines the PLL output signal displayed an angle-modulated response, with frequency
components at integer offsets of the injected carrier frequency, as discussed in Section
5.3.4. To determine the modulation indices βDM and βCM for the DM- and CMinjected signals, a least squares fit was calculated between the measured relative
CHAPTER 6. RESULTS
(1)
Arbitrary
Waveform
and Noise
Generator
158
(2)
47 µF
To: VCOctrl_pos
3.9 kΩ
Centre−tapped
47 µF 3.9 kΩ
Transformer
(1) Noise Generator O/P Test Point
(2) Device Injection Test Point
To: VCOctrl_neg
(a)
(1)
Arbitrary
Waveform
and Noise
Generator
(2)
47 µF
3.9 kΩ
To: VCOctrl_pos
To: VCOctrl_neg
Centre−tapped
47 µF 3.9 kΩ
Transformer
(1) Noise Generator O/P Test Point
(2) Device Injection Test Point
(b)
Figure 6.11: Interfering Signal Injection Generator (a) Differential Mode, (b) Common Mode
amplitudes and the ideal relative amplitudes based on the Bessel function values.
This best-fit modulation index for each of the DM- and CM-injected signals was then
used to calculate the common mode rejection ratio (CMRR) for the circuit, using Eq.
(5.12).
Figure 6.12 displays a representative spectral response of the PLL output signal
without an interfering signal compared to differential mode and common mode spectral responses with 10 kHz interfering signals injected at the VCO control lines. For
the spectral plots the delta frequency is measured relative to the PLL output carrier
CHAPTER 6. RESULTS
159
0
−10
Magnitude, dBm
−20
××
××
××
××
× ×
−30
× ×
−40
× ×
−50
×
×
−60
×
×
−70
×
×
−80
−90
××××
× × × ××××× ××
×
× ××××××× ××× ×××××× ××××××××××××××× ×× ×××××××××××
×
××××××× ×××××
××××××× × ×××××××××××××××××××× ×××××××××××××××××××××××× ×××××
××× ×××××××××××××××××××××××××××××××××××××××××× ××××××× ××××× ×××× ×
××× ××
×
××××××××××××××××××××××× × ×
×
×
××
××××××××××××××××××× ×××× ×× ××
×
××××××××××××× ×××××××××××××××××××××××××××××××××××××××××××××××××××××× ×××× ××× ×
× ××××
×× ××××××××××××× ×××××××××××××××××× ×××
××××××××××××××××××××
×
× ×
×× ×××××××××××××××××××××××××××
×× ×
×× × ××××××××××××××××
×
−100
−50 −40 −30 −20 −10 0
10 20
Delta Frequency (kHz)
(a)
0
×
−10
⊕
30
40
50
Differential Mode
Common Mode
Magnitude, dBm
−20
−30
××
××
××
××
−40
××
××
××
××
× ×
−50
−60
−70
−80
−90
××
××
××
××
× ×
× ×
× ×
× ×
×
×
× ×
× ×
× ×
⊕
⊕
×⊕
⊕×
⊕⊕
⊕⊕
× ⊕×
⊕
⊕
×
× ×
××××
× ×
×
× ××× × × × ××××× × ×⊕
×
×
⊕
×× × × ×
×
××⊕⊕ ⊕
×⊕
××⊕
×⊕
××⊕
×××⊕
××⊕
×⊕
⊕
×⊕
× ××⊕
×⊕
×⊕
×××⊕
⊕
××⊕
⊕
××⊕
××⊕
⊕
××⊕
⊕
×××⊕
⊕⊕×⊕
⊕⊕⊕
××⊕
××⊕
×⊕
××⊕
×⊕
×××××⊕
⊕
×⊕
×⊕
××⊕
⊕
××××××××××××⊕
×⊕
×××⊕
×⊕
×⊕
⊕
× ×⊕××× ×××××⊕
××⊕
⊕
×⊕
×⊕
⊕⊕
⊕
⊕
×⊕
⊕⊕⊕
⊕
⊕
⊕
⊕
×××⊕
×⊕
⊕
⊕×⊕⊕
× ××××××××××××⊕
⊕⊕⊕
⊕⊕
⊕
⊕
⊕⊕
⊕
⊕⊕
⊕
×⊕
⊕⊕
⊕
⊕
×⊕
××⊕
×⊕⊕
⊕
××⊕
⊕
⊕
⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕⊕
⊕
⊕
×⊕
×⊕
⊕
×××××××××⊕
⊕
×⊕
×⊕
⊕
⊕
⊕
×⊕
×⊕
⊕
⊕
×⊕
⊕
⊕
⊕
⊕
×⊕
⊕
⊕⊕
⊕
⊕
⊕
⊕
⊕⊕⊕⊕×⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
××⊕
⊕
⊕
⊕⊕
×⊕
⊕
⊕
⊕
⊕⊕⊕
⊕
⊕
⊕
⊕
⊕
⊕
××
⊕
×⊕
×⊕
⊕
××
⊕⊕
××
⊕⊕
× ×
⊕ ⊕
× ×
⊕
⊕
× ×
⊕ ⊕
× ×
⊕
×
⊕
×
⊕
×
⊕
×
⊕
⊕×⊕
××××⊕
× ×
××××⊕
⊕
×××××××××××××××××⊕
⊕
×⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
×
⊕
×⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕⊕
⊕
×
××
××
××
××
× ×
× ×
××××
××
××
× ×
× ×
⊕
⊕×
×⊕
⊕
⊕⊕
⊕⊕
× ×
⊕⊕
× ×
× ×
××××
××
××
× ×
× ×
×
⊕ ⊕
×
× ×
×
×
××
× ×
⊕ ⊕
×××
×⊕ × × × ×××
×××× ×× ××××⊕
××××⊕
×××××××⊕⊕ ⊕⊕
××××××××××××× ×× ×× ×× × × ×
××××⊕
⊕
⊕
××××⊕
××××××⊕
×⊕
×⊕
×⊕
⊕
⊕
×
⊕
×
⊕⊕ ⊕
×⊕
××⊕
×
×
⊕
⊕
×
⊕
⊕
×
⊕
⊕
×
⊕
×
⊕
⊕
⊕
⊕
×
⊕
×
×
⊕
×
××××××××××××××⊕
×
×
⊕
×
⊕
×
⊕
⊕
⊕
×
×
⊕
⊕
×
×
×
⊕
⊕
×
×
⊕
×
×
×
⊕
⊕
×
⊕
⊕
⊕
×
×
⊕
×
×
⊕
⊕
⊕
×
⊕
×
×
⊕⊕⊕⊕
⊕
×⊕
⊕⊕
×⊕×⊕
×⊕
⊕
× ⊕××××××××××××× × × ×
⊕
×⊕
×⊕
×××⊕
⊕⊕
⊕⊕
××⊕
⊕⊕⊕
×⊕
⊕
⊕
××××⊕
⊕⊕
×⊕
⊕⊕
⊕
⊕
⊕⊕
⊕
×⊕
⊕⊕
⊕⊕
×⊕
⊕⊕
⊕
⊕
⊕
⊕
⊕⊕⊕⊕⊕⊕
⊕⊕
×⊕⊕
⊕
⊕
⊕
××⊕
⊕
⊕
⊕
⊕⊕⊕
⊕
××⊕
⊕
⊕
⊕
⊕⊕
⊕
⊕
×××××××××××
⊕
⊕
⊕
××××××⊕
⊕
⊕
⊕
⊕
⊕
⊕⊕
⊕⊕
⊕
⊕⊕⊕⊕
⊕
⊕
⊕⊕
⊕
⊕⊕
⊕⊕⊕
⊕⊕
×⊕
⊕
×⊕
⊕
××⊕
⊕
⊕
×⊕
××⊕
⊕
⊕
⊕
⊕
×⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕
⊕⊕
⊕
×⊕
⊕
⊕
×
⊕ ⊕ ⊕ ⊕⊕⊕⊕
⊕
⊕⊕
⊕
⊕
×⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕
⊕
⊕⊕
⊕
⊕⊕ ⊕
−100
−50 −40 −30 −20 −10 0
10 20
Delta Frequency (kHz)
(b)
30
40
50
Figure 6.12: DM/CM Signal Injection at VCO Control Lines, Frequency = 10 kHz
(a) PLL Unmodulated O/P Spectrum (freq=26.376 GHz), (b) PLL O/P Spectrum
with Injected DM/CM signals
CHAPTER 6. RESULTS
160
frequency of 26.376 GHz. Fig. 6.12 (a) shows the PLL output signal without injected
interfering signals. Fig. 6.12 (b) shows the PLL output signal spectrum for the DMand CM-injected cases. Notice the distinct frequency components at offsets of n · 10
kHz for the CM- and DM-injected cases; these are the spectral components of Vout (t)
identified by Eq. (5.7). The power levels of the spectral components relative to the
unmodulated carrier power will be used to determine the amplitude of the associated
Bessel function arguments, as described in Section 5.3.4.
The ratios of the differential mode spectral component powers to the unmodulated
carrier power were calculated as per (5.8) and are plotted in Fig. 6.13 as “DM
1.0
J 0( β )
0.9
⊕
♦
♦
DM Measured
CM Measured
0.8
⊕
Amplitude
0.7
0.6
0.5
⊕
J 1( β )
0.4
0.3
0.2
J 2( β )
0.1
♦
♦
♦
0.0
0.0 0.2 0.4
βCM = 0.06
⊕
♦
0.6
0.8
⊕
J 3( β )
⊕
1.0 1.2 1.4
βDM = 1.09
1.6
J 4( β )
1.8
β
2.0
Figure 6.13: Modulation Indices βCM and βDM for CM/DM Signal Injection at VCO
Control Lines, Frequency = 10 kHz
Measured”. A similar calculation was performed for the common mode spectral
CHAPTER 6. RESULTS
161
component powers; these are plotted as “CM Measured”. Fig. 6.13 also displays
the Bessel function responses Jn (β) for n = 0 . . . 4 and for β between 0 and 2 for
comparison. Determination of the modulation indices (or Bessel function arguments)
for the DM-excited interfering signal (βDM ) and for the CM-excited interfering signal
(βCM ) used a least-squares fit between the measured/calculated spectral power ratios
and the ideal Bessel function responses. The DM and CM modulation indices (βDM ,
βCM ) are displayed as dashed vertical lines in Fig. 6.13, with their values noted
beneath the graph.
The frequency spectra for the differential and common mode injection cases may
be used to assess the ability of the designed PLL circuit to reject common mode
interfering signals. For both the DM- and CM-induced frequency spectra there are
theoretically an infinite number of sidebands, as identified in Eq. (5.7). Let the
sidebands that have powers above the noise floor in the spectral plot be considered
significant. The number of significant frequency components and their relative magnitudes for common mode injection in Fig. 6.12 (b) are lower than the number/relative
magnitudes of the significant differential mode spectral components. This is indicative of a lower modulation index β for CM-injection vs. DM-injection, a result that
is confirmed in Fig. 6.13.
Injected common-mode signals affect the output PLL signal spectrum to a lesser
degree then injected differential mode signals. This reduction may be quantified by
evaluation of the common mode rejection ratio (CMRR) using Eq. (5.12). Table 6.6
lists the common mode rejection ratio (CMRR) versus injected frequency for measured
test cases between 1 kHz and 2 MHz. The table shows that there is significant
attenuation of common-mode interfering signals by using the fully-differential design.
CHAPTER 6. RESULTS
Injected freq.
1 kHz
10 kHz
100 kHz
1 MHz
2 MHz
162
βDM
1.27
1.09
1.02
1.16
0.72
βCM
0.06
0.06
0.06
0.11
0.13
CMRR (dB)
26.5
25.2
24.6
20.5
14.9
Table 6.6: Common Mode Rejection Ratio (CMRR) vs. Injected Frequency
Further experimental evidence to support the rejection of common-mode interfering signals may be found in Figure 6.14. This series of plots shows measured phase
noise of the PLL output signal for a 10 kHz injected signal at the VCO control lines.
Fig. 6.14 (a) is the phase noise response for a DM-injected signal and Fig. 6.14 (b)
is the phase noise response for a CM-injected signal. As with the spectral results and
analysis of Fig. 6.12 the common-mode phase noise response of Fig. 6.14 (b) shows
fewer significant spectral components with lower magnitudes than the differentialmode phase noise response of Fig. 6.14 (a).
Broadband Noise Injection
In the previous section discrete frequency signals were injected to determine the response of the PLL to narrowband interfering signals. In this section, the effect of
broadband noise injected at the VCO control lines is examined.
For injection of broadband noise the CM-/DM-generator setup of Fig. 6.11 was
used with a Wavetek 132 noise generator as an analog noise source. The noise generator was set for a sequence length of 210 − 1 and a noise frequency of 1.6 MHz
(corresponding analog noise bandwidth of 100 kHz). Increasing the sequence length
results in a decrease in the carrier spacings. Figure 6.15 (a) shows the broadband
spectrum of the noise sampled at both the noise generator output (Test Point (1) of
CHAPTER 6. RESULTS
163
0
−12
−48
+
+
+
+
+
+
+
++
+
+
+
+
+
−60
+
+
Phase Noise (dBc/Hz)
−24
−36
−72
−84
−96
−108
−120
+
+
+
++
++
++
+
+
+
+
+
++
+
+
+
+
+
+
+
+
++
+
+++
+
+
+
+
+
+
+
+
+++
+
+++
++
+++
++
+ + ++
++
++++
++
+
+
+
++
++
+
++
+++++
+++
+++
+
+++
+++
++
+
+++
+
+++
++
+++
+++++
+++
+++++
++
+
++
++ +
++
+++ +
+ +
++++
+
++
++
++
+ +
+
++++
+++
++
++
+
++
++
+
++
++
++
++
+++++
+
++
+
+
+
+
++
++++
+
++
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
++
+++
+++ +
+ +++
++++++++++++
++
+
+
+++++++
++
++
++
+
++ +++ + +
++
+++
+
+
+
++
+++
+
+
++ +++
++
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
++++++++++
+++
++++ +++++
+
+++++
++++
+++++++++++++
+++++
++
+++
+++
++
+
++
++++
+++
+++
++
+++
++
++
+++++
++++
++
++
++
++
++
+++++++++++
+++
+++
++++++
+
++
+++
+
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+++
++++
++
++
+
+
++
++
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++
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++
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++
+
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++
+
+
++
+
++
+
++
++
++++
+
++
+
++
+
++++
+++
++
++
++
++
+
++++++
+++
+
++++
+
++
+
++++++
++
++++
++++
+
+++
++
++ + ++
+++
+
+
+++
+++
++++
+
+
+
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+
++
+
++
+
+
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++
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+
++
+
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+
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+
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+
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+
+
+
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++
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+
+
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+
+
+
+
+
+
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+++
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+
+
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+++
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+
+
+
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+
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+
+
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+
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+
+
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+
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+
+
+
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+
+++
++ +
+
++
+++++++++
+
++++
+
+
+
+
+
++++ +++
+
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++
++++++
+
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+ +
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++++
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++
++++ +
+
+ +++ +
++
+++++
++
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++
+++
+
+
++
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+ ++++
+ +
++
+
++
+
++++
+
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+++ ++
+
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+ +
+++
+++
+++++++
++
+++ +
+ ++
+ +
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+ + +++
+
+
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+
+
+
+
+
+++++
++
+
++
++++++ +
++
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++ +
++
++++ ++
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+++
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+
++
++
+++++++ ++ ++
++++++
+++
+++
++
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++++
+++
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++
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+++++++
++++++++++++++
+
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++++
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+++++
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+
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+ ++++++
+
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+++ +
++
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+
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++
++
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+
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++
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++
+
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++
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+
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+ +
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++
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++++++
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++++
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+++
+++++++++++
+++
+++
++
+++++++++++++++++++
+++
+++++++
+
++
++
+
++
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++
+++++++
+++
+++
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+
+++++++++
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++++ +++ + +
++
++
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++++++++++++
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+
+ +++
++
+
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+
++
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+++
++
+
+
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+
+
++
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+ ++++
+++
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++++
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++
++
+ + +++++++++++
++++
++++++++++++++
+ +++
2
10
3
10
4
5
10
10
Offset Frequency (Hz)
(a)
6
10
7
10
0
−12
Phase Noise (dBc/Hz)
−24
−36
⊕
⊕
⊕
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−48
−60
−72
−84
−96
−108
−120
10
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2
3
10
4
5
10
10
Offset Frequency (Hz)
6
10
7
10
(b)
Figure 6.14: Measured Phase Noise for Differential Mode/Common Mode Signal Injection, Frequency = 10 kHz (a) PLL Output, DM-injected Signal, (b) PLL Output,
CM-injected Signal
CHAPTER 6. RESULTS
164
−20
⊕
−30
Magnitude, dBm
−40
−50
−60
−70
−80
−90
−100
×
Noise Generator Output Test Point
Device Injection Test Point
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××××× ×× × ×
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××××××××××× ×××××××××××××× ×××××× ××
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×××× × ××××××××× ××× ××××××××
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
×
⊕
⊕
××××××××××× ××× ×××××× ×
⊕
⊕
⊕
⊕
⊕
⊕
× ×× ×
⊕
⊕
⊕
⊕
⊕
⊕
⊕
×××××××××××××××××××× ××× ×
⊕
×
⊕ × ×
× ×
×
× ×
×××××××××××××× ×××××××××××××××××××××××××××× ××××××××××× ×× ×× ⊕
× ×
××
×
× × × ××××× ×××××× ××××××××××××× ×× ××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××× ××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××××
×
× × × × ×××× × × ××× × ××× × ××××× × × × ××× ×××××××××××××××× ×××× ×× ××××××× ××××××××××××× ×× ××××××
×
× ×
××
×
−110
−120
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (MHz)
(a)
−30
×
×
Magnitude, dBm
−50
×
×
×
×
×
×
×
×
×
×
×
×
−70
−110
−130
×
×
×
×
××
××
×× ×
×
×
×
×
×
×
×
×
×
×× ×
×
×××
××
×
×
×
×
×
×
×
×
−90
×
×××
×
×
× ××
××
××
×
×××
××××
×× ×
×
×
×
×
×××
××
×
××
××
×
××
×
×
×× ××
×
×
×
×
×× ××
×
×
×
××
××× ×××
×
××
×
×
×
×
×
×
×
×
×
×
××
× ××
×
××
× ×
×
××
×
×× × ×× × ×× ××
×
×
×
×
×
×
× × ×× ××× × × ×
× ×
××
× × ×× × ××
× × ××
×× × × × ×
××× × ××
× ×
× ××× ××××
×× ×××
× ×× ×
××× ×× ××× × ××××××××××××× ×××××××××
×× ×× ××
× × ××××××× × ××××× ×
× ××
× × × ×× × × ×× ××× ×× × ×××××× × ××××××××
× ×
××
×
××× ×××
×
×
×
×
×
×
×
××× ×
× × ×××
××× ×
×
×××××
×
×
×
×
×
× ×××
×
×
××× ×
××
×
×
×× × × ××
×× ×× ××
× ××××××× ××× ×
×
×
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××
×
×××
×
×
×
×
×
× ×
×× × ×
×
×
×
× ×
×
××
×
×
× ×
×
×
×
×
××
×××
××× ××
×
× ×
××
× × ××
× ×××
× ×× ×
× ×× ××
× ×× ×××
××
××
× ××
×
×
×
×× ×
×
×
×
×
×
× ×
×
××
×
××
× × ×××
×× × ×
×× ××× ××
× × ××
× ×
××
× ×
×
××
× ×
××
×
××× ×××××
×
××××××××
××
×
× ×
×
×
×
×
×××
×
×
×
×
×× ×
×
×
×
××
×
×
× × ××
×××××× ××
× ××× ××
×× ×
× × ×
××
×
×
−150
0
2
4
6
8
10 12 14
Frequency (kHz)
(b)
16
18
20
Figure 6.15: Injected Broadband Noise (a) Generator Noise at Generator Output
and Device Injection Test Points (RBW=4.7 kHz), (b) Generator Noise at Generator
Output (RBW=30 Hz)
CHAPTER 6. RESULTS
165
Fig. 6.11 (a)) and at the injection test point (Test Point (2) of Fig.6.11 (a)). The
power spectra for both curves display a 6 dB roll-off at 100 kHz. The broadband noise
was actually composed of multiple discrete noise signals at a spacing of 1.645 kHz, as
shown in Fig. 6.15 (b). The selection of the sequence length of 210 − 1 resulted in a
repeating sequence of 1023 counts of the selected frequency (for the test case, 1.682
MHz). Increasing the sequence length results in a decrease in carrier spacing in the
frequency domain. The resolution of these discrete spectral components is dependent
upon the resolution bandwidth (RBW) selected for the spectrum analyzer.
The measured spectra for the PLL under selected broadband noise injection cases
is shown in Figure 6.16. Responses are plotted for the PLL output carrier without
0
×
−10
Magnitude, dBm
−20
−30
−40
−50
−60
−70
−80
−90
⊕
♦
♦
××
⊕
×⊕
♦
♦
×⊕
⊕
♦
♦
×
⊕
×⊕
♦
♦
×
⊕
×⊕
♦
♦
×
⊕
×⊕
♦
No Injection
DM Injection
CM Injection
♦
♦
×
× ⊕
⊕
♦
⊕
×
⊕
⊕⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕ ⊕⊕
⊕♦
⊕
⊕
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⊕
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⊕
×
⊕
⊕
⊕⊕⊕
⊕
⊕
⊕
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⊕⊕
⊕⊕⊕⊕
⊕
⊕⊕⊕
⊕
⊕
⊕⊕
⊕
⊕⊕
⊕
♦
×
⊕
⊕
⊕
⊕
⊕
⊕
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⊕
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♦
♦
♦
♦
♦
♦♦
⊕
♦♦♦
××
⊕⊕
♦
⊕
♦
♦♦♦
♦
♦
♦
⊕
⊕
⊕
⊕
♦♦
♦♦♦
×××××××
♦
⊕
⊕
♦♦
⊕
♦
♦
♦
♦♦
×
⊕
♦
♦
×××××
♦♦
⊕
♦♦
♦
×
♦
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×
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⊕
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⊕ ⊕⊕
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♦
♦♦♦
⊕
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⊕
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⊕
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××××
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⊕
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⊕
⊕
⊕
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⊕
⊕
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♦ ××××××××××××
♦
⊕
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⊕
⊕
⊕
×
×
⊕
♦ ×××× ×
♦
⊕
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♦×××××× ×
♦
⊕
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⊕⊕
♦
♦
⊕
⊕⊕
×× ♦
♦
×××× ×××××
⊕
⊕
⊕
⊕
×♦
⊕
⊕
⊕
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⊕♦♦× ♦ ♦
♦
♦♦
♦
×♦
⊕
⊕
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⊕
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♦
⊕⊕
×♦
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⊕
♦
××♦
♦
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♦
××××××××××× ×
⊕
♦
⊕
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×⊕
♦
♦♦
×⊕
×⊕
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♦
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⊕♦
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⊕
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××♦
⊕
⊕
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⊕
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⊕
×
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×
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⊕
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⊕
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⊕
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⊕
⊕
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⊕
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⊕
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⊕
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⊕
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×⊕
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⊕
×⊕
×⊕
⊕
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♦××♦
⊕
⊕
××××××××⊕
⊕×⊕
××⊕
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××× × ♦⊕
⊕
×
♦
⊕
×
⊕ ⊕
⊕⊕ ⊕⊕
⊕⊕
⊕
⊕
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♦
⊕
×⊕
⊕
⊕⊕
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⊕
⊕
⊕
⊕⊕⊕
⊕
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⊕
⊕
⊕
⊕⊕
⊕
⊕
⊕
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⊕
⊕
⊕⊕
⊕⊕
⊕
⊕
♦
⊕⊕
×
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
⊕
×
⊕
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⊕
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♦♦
♦
♦
⊕⊕
♦
♦
♦
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♦
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⊕
♦
⊕⊕
×
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⊕
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⊕
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⊕
⊕
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⊕
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♦
×××××× ♦
⊕
♦
××× ♦♦♦♦♦
⊕
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⊕
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⊕
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⊕
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⊕
⊕
⊕
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××××××× ♦♦
⊕
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⊕
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♦
♦
⊕⊕
♦
××××
♦
⊕⊕
♦
×××× × × ♦
♦
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⊕
⊕
⊕
⊕
⊕⊕
××××××××××× ♦♦
♦♦
⊕⊕
⊕
×××× ♦
♦
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⊕
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×
⊕⊕
⊕
×
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×
⊕
×
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⊕⊕
×
⊕
⊕
×
×
×
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⊕
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×× ×××××××××××♦
×
×
×
×
⊕
×
×
♦
♦
⊕ ⊕ ♦♦
×
⊕⊕⊕
⊕⊕
×
♦
×××♦
♦
×
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×⊕⊕
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×⊕
×
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♦
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⊕
♦
♦
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×⊕
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×⊕
♦
×⊕
♦
⊕
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×⊕⊕
×⊕
×⊕
×⊕
×⊕
×♦
×⊕
⊕
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×
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⊕
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⊕
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⊕
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×⊕
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⊕
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×⊕
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×⊕
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⊕
⊕
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×
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×⊕
×
♦
×
♦
×⊕
♦
♦
♦
♦
♦
×⊕
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×⊕
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×⊕
×⊕
♦
♦
♦
×♦
×♦
⊕
♦
♦
×⊕
×♦
♦
×
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♦
×♦
♦
××⊕
×♦
×⊕
××♦
××⊕
⊕
×⊕
×⊕
×♦
♦
×♦
⊕
×⊕
♦
♦
×♦
⊕
××⊕
♦
♦♦
×⊕
×⊕
♦
×⊕
×♦
×⊕
⊕
×♦
⊕
⊕
××××⊕
×⊕
♦
×⊕
×♦
♦
♦
×⊕
×♦
♦
♦
×♦
♦
♦
♦
×⊕
♦
×⊕
×♦
♦
♦
×⊕
×♦
×♦
⊕
⊕
♦
⊕
♦
×♦
♦
♦
×⊕
×⊕
×♦
⊕
♦
×⊕
××♦
♦
×
×⊕
×⊕
⊕
♦
×♦
×⊕
××♦
×⊕
×⊕
×♦
⊕
××⊕
⊕
♦
♦
×♦
♦
×⊕
×⊕
♦♦
×⊕
×⊕
♦
⊕
⊕
××♦
⊕
×⊕
⊕
⊕
×⊕
×⊕
♦
♦
⊕
⊕
♦
×⊕
×⊕
⊕
×××⊕
⊕
⊕
♦
××⊕
⊕
♦
×♦
×♦
♦
×⊕
♦
⊕
♦⊕
×⊕
×⊕
⊕
×⊕
♦×♦
♦
⊕⊕♦
♦
⊕
⊕
♦
⊕
⊕
♦♦
×
−100
−0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2
Delta Frequency (MHz)
0.3
0.4
0.5
Figure 6.16: Unmodulated Carrier versus CM/DM-Injected Broadband Noise Spectra, fosc =26.524 GHz (RBW=4.7 kHz)
CHAPTER 6. RESULTS
166
injected noise, the carrier with DM-injected broadband noise, and the carrier with
CM-injected broadband noise. A reduction of 25 dB in the CM-injected noise adjacent
to the carrier versus the DM-injected noise is evident. This value is consistent with the
CMRR determined for discrete carrier noise injection determined earlier and displayed
in Table 6.6 for offset frequencies less than 100 kHz.
Phase noise measurements are plotted for broadband DM- and CM-injected signals
in Figure 6.17. Figure 6.17 (a) shows the PLL output phase noise with no injected
noise signal while Fig. 6.17 (b) shows the effects of CM- and DM-injected broadband
noise. The spectral response shows the discrete noise spectral components at multiples
of 1.645 kHz previously identified. The jumps in spectral amplitude and the amplitude
differences for components less than and greater than 10 kHz offset frequency are a
result of the analyzer pre-set resolution bandwidths for phase noise determination.
The common mode rejection is evident in the reduced spectral magnitudes for the
CM-injected case of Fig. 6.17 (b). The CM-injected signal shows a 25 dB reduction
in signal level compared to the DM-injected signal for offset frequencies less than 100
kHz.
6.5
Analytical vs. Measured Phase Noise
The analytical model of Eq. (5.26) assumes that the phase noise response for the
PLL is dominated by the reference and VCO phase noises. Using the experimentallyderived phase noise response for the free-running VCO signal of Figure 6.5 and the
measured reference signal phase noise of Figure 6.4 (b) of Section 6.3.1, a comparison
of the analytically-calculated PLL phase noise versus the measured PLL phase noise
was undertaken.
CHAPTER 6. RESULTS
167
−20
−30
Magnitude, dBc/Hz
−40
−50
−60
−70
−80
−90
−100
−110
−120
♦
♦ ♦
♦
♦
♦
♦
♦
♦
♦
♦♦
♦
♦ ♦♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦♦♦
♦
♦
♦
♦
♦♦
♦
♦
♦♦♦
♦
♦♦
♦
♦
♦
♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
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♦
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♦
♦
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♦♦♦ ♦
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2
10
3
10
4
5
10
10
Offset Frequency (Hz)
(a)
−20
Magnitude, dBc/Hz
−50
−60
−70
−80
−90
−100
−110
−120
10
10
×
−30
−40
6
⊕
7
10
DM Injection
CM Injection
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2
3
10
4
5
10
10
Offset Frequency (Hz)
(b)
6
10
7
10
Figure 6.17: PLL Phase Noise for Broadband CM/DM-Injected Noise, Noise BW=100
kHz, fosc =26.524 GHz (a)Unmodulated Output Carrier, (b)Output Carrier with
CM/DM-injected Noise
CHAPTER 6. RESULTS
168
In order to improve the analytical accuracy, the PLL phase detector constant Kd
was determined for input voltage levels used in performance testing. The reference
incident voltages at the REF pos and REF neg probe inputs were calculated from
path losses and reflection coefficient measurements. The phase detector response was
simulated to determine the new value of the detector gain Kd . Figure 6.18 shows
0.6
+
+
0.5
+
0.4
+
0.3
V_IF (V)
+
0.2
+
0.1
+
0
+
−0.1
+
−0.2
+
+
−0.3
PD IF Voltage
Least Squares Best Fit: K d=0.571 V/rad
+
−0.4
−1.8 −1.6 −1.4 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2
Phase Diff. (rad)
0
Figure 6.18: Phase Detector Simulated IF Output Voltage vs. Input Phase Difference
with Least Squares Best Fit Line
the simulated PD IF voltage versus input phase difference under the system test
conditions of -8 dBm output power from the signal generator (0.1325 V at CLKPOS
input, 0.1257 V at CLKNEG input)and 0.3 V internal signal voltages from the MSFF
outputs. The PD gain Kd , determined from the slope of the best fit line is 0.571 V/rad,
with a static phase offset value of 0.5 rad.
The PLL output phase noise was calculated based on the carrier phase noise and
the free-running VCO phase noise determined in Section 6.3.1. Equation (5.26) was
used, with the equations for Hclosed,I/P (i∆ω) and Hclosed,V CO (i∆ω) given by (3.47)
CHAPTER 6. RESULTS
Loop Variable
Ko
KD
C
R
N
169
Value
(2π)0.758×109
0.571
182.4
36.2e3
4
Units
rad/V·sec
V/rad
pF
Ω
-
Table 6.7: Analytical Calculation of Phase Noise - Loop Constants
and (3.48), respectively. The values for the various loop constants are listed in Table
6.7.
Figure 6.19 uses a combination of plots to show the individual contributions and
combined contributions of the PLL phase noise sources considered. The PLL output
frequency is 26.544 GHz with a measured output power of -25.9 dBm. The curves in
the upper graph of Fig. 6.19 are calculated as
P LL − REF L = 20 log(|Hclosed,I/P (i∆ω)|2 Lref (∆ω)), and
(6.5)
P LL − V CO L = 20 log(|Hclosed,V CO (i∆ω)|2 LV CO,f ree (∆ω)),
(6.6)
where the 20 log() terms of (6.5) and (6.6) are the terms from Eq. (5.26). The curves
in the lower graph of Fig. 6.19 show the calculated PLL phase noise as per Eq. (5.26),
the measured PLL phase noise, and the Reference phase noise (all in dBc/Hz). The
vertical lines between the two graphs show the regions where either the Reference or
the VCO (or both) are dominant in the total calculated PLL phase noise (a dominant
contributor for the purpose of this comparison is one that is 10 dB or more greater
than the other).
The analytical calculations show very good agreement with the measured results.
The PLL phase noise to approximately 200 kHz is dominated by the reference phase
noise, as expected, due to the lowpass nature of the Reference-to-output transfer
CHAPTER 6. RESULTS
170
function Hclosed,I/P (i∆ω). The analytical model shows a 12 dB increase in phase
noise with respect to the reference input phase noise for offset frequencies less than
approx. 200 kHz. This 12 dB increase corresponds to the multiplication factor of 4 in
the PLL. Between 200 kHz and 2 MHz the contributions from the Reference and the
VCO are both significant. The effect of gain peaking as a result of the low damping
factor ζ becomes evident in the significant phase response peak at 1.7 MHz offset
frequency. For frequencies greater than 2 MHz, the free-running VCO phase noise
dominates the system phase noise.
The analytical model has correctly identified the resonant peak at 1.7 MHz offset
frequency. The measured PLL phase noise response displays additional phase noise
peaks at harmonics of the resonance frequency. The analytical model does not account
for harmonics, as it assumes a linear transfer function. Nonetheless, the ability to
accurately predict phase noise response based on measured inputs is a useful tool for
the practical design engineer.
CHAPTER 6. RESULTS
−70
−80
Phase Noise dBc/Hz
−90
−100
−110
−120
−130
−140
−150
−160
−170
171
++++ +
++
+ +++
+ ++++++ +
++++++++++
+
+
++
⊕
+ + + ++++++++
++++
⊕
+ + +++++++++++
++
+ + ++++++++++ +++++
+
+
+++++++ ++ +++++++++++++++++++ +++
⊕
+ + ++ +
++ +++++++++++++++++++
+
+
+
+
+
+⊕
⊕
+
+
+
+
+
⊕
++ ++ ++ + ++++++++ ++++++++++++++++++++++++ +++++++++++ ++ +
+ +++++ +++++++++ + +
⊕
+
⊕
++
++ + +++++
+
+
+
⊕
⊕
+ + +++ +++++++ + ++ + + +++ + +++++++++ + +
⊕⊕
+
+ ++++++++
+
+
+
+
⊕
⊕
+⊕
⊕
+
+
⊕⊕
+ + ++++
+
⊕
+
⊕
+
⊕ ⊕⊕
⊕
⊕
⊕
⊕
⊕
+
+
++ ++
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+
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+
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+
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+
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+
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+
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+
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+
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+ ++++++
+
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++
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⊕
+++
+++
+
PLL−REF L
PLL−VCO L
2
10
3
10
4
5
10
10
Offset Frequency (Hz)
6
7
10
10
VCO
and
REF
VCO
−50
−60
Phase Noise dBc/Hz
−70
−80
−90
−100
−110
−120
−130
−140
−150
10
REF. Dominant
⊕
⊕
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♦
♦♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦♦
♦♦
♦ ♦♦
♦
♦
♦
♦
♦ ♦♦ ♦
♦
♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦ ♦♦♦
♦
♦
♦
♦♦
♦
PLL−calc.
PLL−meas.
Reference
2
3
10
4
5
10
10
Offset Frequency (Hz)
6
10
7
10
Figure 6.19: PLL Phase Noise: Contributions from Reference and VCO (top graph),
Analytical versus Measured Performance (bottom graph) and Identification of Dominant Contributions vs. Offset Frequency
Chapter 7
Conclusion and Future Work
7.1
Conclusion
The design of phase locked loops (PLLs) for high frequency applications continues
to draw considerable interest. As newer CMOS process nodes are developed, the
challenge of designers and researchers is to develop designs that meet higher frequency
needs, increasingly stringent phase noise specifications and lower DC power supply
requirements.
The research undertaken successfully delivered an integrated 26 GHz frequencymultiplying PLL using a well-established 0.18-µm CMOS process. The PLL operational frequency is the highest reported to date using a 0.18-µm process. Phase noise
measured at 1 MHz offset frequency was found to be -103.9 dBc/Hz. The core of the
circuit (VCO/ILFD/MSFF Divider/PD) without buffers and supporting circuitry
drew 186 mW of power combined from the 2.8V and 4.3V voltage rails. This DC
power consumption reflects the deliberate over-design of the the VCO and the ILFD
(consuming 57% of the core DC power) to ensure oscillation. VCOs with operational
172
CHAPTER 7. CONCLUSION AND FUTURE WORK
173
frequencies in excess of 20 GHz in 0.18-µm CMOS technology have been reported
with power consumptions below 20 mW [15], [79], indicating a power reduction of
50% in these particular components is possible.
The design of the PLL was specifically selected to be fully differential at all points
within the circuits to mitigate the effects of common mode (CM) noise. The benefit of
the fully-differential circuit is demonstrated in common mode rejection ratio (CMRR)
values in excess of 20 dB for discrete and broadband injected signal frequencies less
than 1 MHz. All sub-circuits were selected and designed based on a differential layout.
The VCO uses a differential varactor structure reported previously [13] [52] to mitigate
the effect of common mode noise on the VCO control and voltage supply lines. The
first divide-by-2 stage injection locked frequency divider (ILFD) uses a direct injection
technique [33] consisting of complementary N- and PMOS switches across its LC tank.
The static master slave flip-flop (MSFF) divider used for the second divide-by-2 stage
uses the differential signal from the ILFD to drive the master/slave clock inputs; the
complementary outputs are in turn used to drive the phase detector (PD) based on the
Gilbert cell mixer circuit topology. Each PD complementary output is then lowpass
filtered and fed back into the differential inputs for the VCO.
The transfer function from the VCO control line inputs to the VCO/PLL output
displays significant gain for offset frequencies between 100 kHz and 30 MHz. Low
frequency noise coupled onto either the VCO control line or the VCO power line
would be transfered to the VCO/PLL output via phase modulation of the carrier.
The differential nature of the PLL reduces this effect by rejecting common mode
interfering noise carriers, making the design an ideal candidate for environments where
the circuit may be exposed to power line noise or strong radiated signals that can be
CHAPTER 7. CONCLUSION AND FUTURE WORK
174
coupled in a common mode fashion into the circuit.
An analytical model for static phase offset in the Gilbert cell phase detector was
presented. The model identified that static phase offset was composed of contributions
from layout-related RC time constants and from the intrinsic channel transit time
effect. Because of the inverse relationship between the intrinsic channel transit time
τtr and the drain current IDS there exists a tradeoff between static phase offset and
DC power consumption. The analytical model for the intrinsic channel transit time
static phase offset showed good agreement with simulated circuit results.
System output phase noise was calculated using an analytical model of the PLL
closed loop transfer functions for the Reference- and VCO-generated phase noise. As a
necessary part of the analysis, the free-running VCO phase noise necessary for system
phase noise analysis was determined by using an injection locking technique with the
locking signal injected at the VCO tail transistor instead of across the output buffer.
A comparison of the calculated and measured PLL output phase noise showed very
good agreement, with the analytical model predicting the correct offset frequency for
the measured gain peak resulting from the closed loop transfer functions.
The PLL clock multiplier design used a low multiplication factor of 4. A consideration of phase noise performance based on selected commercial crystal and dielectric
resonator oscillators showed that the combination of low multiplication factor / high
frequency reference displayed distinct advantages versus a high multiplication factor
/ low frequency reference. Advantages include a simpler divider structure, reduced
reference phase noise upconversion for a given offset frequency within the PLL bandwidth, and the ability to trade off PLL loop bandwidth against VCO phase noise as
a result of the reduced in-band noise contribution.
CHAPTER 7. CONCLUSION AND FUTURE WORK
175
Phase plane analysis was found to be useful in determining the locking bandwidth
of the PLL. Determination of locking bandwidth of a PLL is challenging because
of the dependency of the system on initial phase and frequency conditions. Phase
plane analysis uses an analog solution to a non-linear differential equation in the
time domain. The initial phase and frequency conditions serve as starting points; the
analysis traces out contours versus time that either converge to a point of dynamic
equilibrium (phase lock), converge to a point of dynamic equilibrium after a phase
slip of n · 2π (phase lock with cycle slip), or diverge (no phase lock). Non-ideal
circuit behaviour such as static phase offset in the phase detector can be readily
incorporated into the analysis. The phase plane analysis is also useful in determining
the maximum allowable frequency perturbation in order for the PLL to maintain lock
once in a locked state.
7.2
Future Work
The research undertaken successfully developed a frequency-multiplying PLL in a
0.18-µm CMOS technology. Many aspects of the design would provide interesting
future research investigations, centred primarily around improvement of the VCO
phase noise performance, reduction of power consumption, development of a functional frequency acquisition circuit and the overall PLL structure.
7.2.1
VCO Phase Noise Improvement
The VCO displayed low output power as a result of the relatively small inductor and
the low quality factor of the varactors used. As indicated in Section 4.2, increasing the
CHAPTER 7. CONCLUSION AND FUTURE WORK
176
charge displacement qmax will decrease the phase noise from a given noise source. This
may be accomplished by increasing the inductor value and decreasing the total tank
capacitance, composed of the varactor capacitance Cvar and other parasitic capacitances (such as the gate-drain capacitance Cgd and parasitic capacitances associated
with the drain-gate blocking capacitors). Varactor capacitance could be reduced by
decreasing the total gate width (number of gates multiplied by width/gate). Removal of the drain-gate blocking capacitors of the VCO (shown in Fig. 4.1) would
necessitate a re-biasing of the VCO, but would reduce the associated parasitic capacitances. Quality factor improvements for the LC tank for a given capacitance could
be achieved through re-examination of the varactor layout (shorter device widths, increased distance between the ground contacts and the varactor well and the varactor
well size). Finally, use of a thick metal layer for inductor fabrication would reduce
inductor series resistance.
7.2.2
DC Power Reduction
The reduction of DC power consumption may be accomplished by a re-examination of
the individual sub-circuits and their individual power requirements. The minimization
of power consumption in the VCO and ILFD oscillator circuits was never a design
goal in the frequency multiplier PLL; of greater concern was the proper operation and
biasing of the sub-circuits individually and the PLL as a whole. Circuits were designed
for a high probability of operation despite using transistor models at frequencies far
beyond their intended range; risk was minimized by over-designing the circuits.
Each subcircuit design incorporated tail transistors to allow for individual operation and performance optimization. Removal of the tail transistors would reduce the
CHAPTER 7. CONCLUSION AND FUTURE WORK
177
voltage rail requirement by approximately 1 V.
The design of the two oscillators in the system (the VCO and the oscillator for the
ILFD) used large gate widths for the negative-gm core to guarantee sufficient negative
resistance for the oscillators to operate correctly. With improved LC-tank quality
factor and reduced parasitic capacitances, a re-examination of the total transistor
gate widths may reveal an opportunity to reduce the VCO and ILFD gate widths
and their associated DC biasing currents.
7.2.3
Frequency Acquisition Circuitry
A great deal of effort was spent on lock acquisition for the PLL. The lock acquisition
technique used in the measurements set the Reference frequency based on the VCO
free-running frequency, as opposed to the PLL finding and locking to the user-set reference frequency. For a production-ready design it would be necessary to implement
a frequency acquisition circuit that would sweep through the PLL operational range
and lock to the input reference. This circuit would also allow for frequency variations
due to device variability, temperature and voltage variation.
7.2.4
PLL - Top Level
The selection of a single pole RC lowpass filter affected the performance of the VCO
by limiting the selection of the critical PLL loop parameters of ωn , ζ, and the DC
loop gain. The selection did ensure that loop stability was maintained, and that
there was additional high frequency noise rejection. Selection of a passive filter with
an additional zero would allow increased flexibility in the setting of the PLL loop
constants, at the tradeoff of potentially greater high frequency noise. Fig. 7.1 shows
CHAPTER 7. CONCLUSION AND FUTURE WORK
178
simulated PLL output phase noise for a proposed lead-lag loop filter, for circuit
−50
+
−60
Phase Noise dBc/Hz
−70
−80
−90
−100
−110
−120
−130
−140
−150
10
♦
PLL−calc.
Reference
++++ +
++
+ +++
+ ++++++ +
+ + +
+
+ + +++++++++++ +
+ + + + +++
++++
+ + +++++++++++
+ + +++++++++++ +++
++
+
++++++++ ++ +++++++++++++++++++ +++
+ + ++ +
♦♦ ♦ + ♦
♦ ++++++++++++++++++++++++++
♦
+
+
+
♦
+
+
+
+
+
+
+
+
♦
++ + + + ++++++++ ++++++++++++++++++++ +++++ ++++ + +
++ +++++ +++++++++ + +
♦ ♦
+
+
+
+
+
+
+
+
♦
++ + +++++
+
+
++ +++++ + ++ + + ++ + + ++++ + +
♦
♦ ♦♦♦♦
+
+ ++++++++
♦
♦♦ + + + +++ +
♦ ♦♦
♦
+ + +++++ + + ♦
♦♦
♦♦♦♦♦ + +
♦
♦ ♦ ♦♦♦
+ + ++++
+
♦
♦
♦
♦♦ ♦
♦ ♦ ♦♦ ♦
♦
+++++
♦♦ ♦♦
♦♦♦
♦ ♦♦♦♦
♦♦♦
♦♦
++
♦ ♦ ♦♦
♦
♦
♦♦♦
♦♦
♦♦
♦ ♦♦♦♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
+++++++
♦
♦
♦
♦
♦
♦♦♦♦
♦
♦♦ ♦
♦ ♦♦
♦
♦
♦ ♦ ♦♦
♦
♦
♦
♦♦
♦
♦♦♦
♦♦
♦
♦
♦♦♦
♦♦
♦ ♦♦
♦
♦
++
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦♦♦
♦
♦
♦
♦
♦
♦
♦
♦ ♦ ♦ ♦♦
♦♦
♦♦ ♦ ++++++++++
♦♦
♦♦♦
♦♦
♦
♦♦
♦
♦ ♦♦♦
♦♦♦♦
♦
♦
♦♦♦♦♦♦ ♦♦
♦♦
♦
♦
♦
♦
♦ ♦
♦
♦
♦
♦
+ ++
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
+
♦
♦
♦
♦♦ ♦
♦
♦
♦ ♦♦♦
♦♦♦ ++++++++
♦♦
♦
♦♦
++
♦♦
♦♦ ♦
♦♦♦
♦ ♦ ♦♦
♦♦
♦♦
♦ ♦♦♦
+ +++
♦
♦
♦♦
+ ++ + + +++++++
♦♦♦♦♦
++
+
+++++++
♦♦
+++++++++++++++++++++++++++++++++++
♦
++
♦
♦♦
+
++++++++++++++
+++++
+
♦♦
+
+
♦
+
+
+
+
+
+
+
+
+
+
+
+
+
+
♦♦
+ ++++ ++ + + ++ ++ ++++++ ++++++ +
♦
♦
+ +++ ++++++++++
+
+++++++++++ +++ ++++ ++++++++++++++++ ++
♦
♦
♦
♦
♦
♦
♦
♦
♦
++++++ +++ + ++++++++ ++++++
♦
+
♦♦
++++++++ +++++++++
♦
+
+
♦
+
+
♦
+
+
+
♦
+
+
+
+
+
♦
♦
+ ++++++
++++ +++++++++ ++++
♦
♦
+
♦
+
♦♦
+
+
♦
+
♦♦
♦♦♦
♦♦
♦♦♦
♦
♦
♦
♦♦
♦
♦♦
♦
♦
♦ ♦
♦♦♦
♦♦♦ ♦
♦
♦
♦♦♦♦
♦
♦♦
♦♦
♦ ♦♦
♦
♦♦
♦
♦♦♦
♦♦
♦
♦
♦
♦
♦
♦♦
♦♦♦♦♦♦♦
♦
♦
♦
♦♦
♦
♦
♦♦
♦♦ ♦♦
♦♦
♦
♦
♦♦
♦♦
♦
♦
♦
♦♦♦
♦♦
♦♦ ♦♦
♦
♦
♦♦
♦
♦
♦♦♦♦
♦
♦
♦
♦
♦
♦
♦♦
♦
♦
♦♦
♦
♦♦
♦♦
♦
♦
♦♦
♦
♦
♦
♦ ♦ ♦♦♦♦♦♦
♦♦♦♦♦
♦
♦
♦♦♦
♦
♦
♦
♦♦
♦
♦♦
♦
♦
♦
♦
♦
♦
♦♦♦
♦♦
♦
♦♦♦♦♦
♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦♦
♦♦
♦
♦
♦♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦♦
♦♦
♦ ♦♦
♦
♦
♦
♦ ♦♦ ♦
♦
♦♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦ ♦♦♦
♦
♦
♦
♦♦
♦
R1=36.2 kΩ
R2=750 Ω
C1=182.4 pF
2
3
10
4
5
10
10
Offset Frequency (Hz)
6
10
7
10
Figure 7.1: Calculated PLL Phase Noise, Lead-lag Loop Filter
constants Ko = 2π ·0.758×109 rad/V·sec, KD = 0.571 V/rad, C1=182.4 pF, R1=36.2
kΩ and R2=750 Ω. The resonance evident in the measured results reported in Ch. 6
has been significantly reduced, and there is the potential to change the loop bandwidth
to take better advantage of the reference phase noise performance.
Improved PLL tracking bandwidth can be achieved by optimizing the ILFD to a
free-running frequency that is very close to one half the VCO free-running frequency.
This could be achieved by re-sizing the inductor or by increasing the tank capacitance.
Another option that would benefit the tracking bandwidth would be tying the ILFD
control voltage to the VCO control voltage, allowing the ILFD to track the VCO as
it varies according to the input Reference frequency in a locked case.
CHAPTER 7. CONCLUSION AND FUTURE WORK
179
As a final consideration, the design of the frequency multiplying PLL was undertaken using a relatively inexpensive CMOS process for proof of concept. Improved
performance is possible in more advanced CMOS processes both because of their
higher potential operating frequency and their potential for improved RF quality
factors for passive circuits.
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Appendix A
Simulation of High Frequency
PLLs
A.1
Introduction
Simulation of the PLL sub-circuits and top-level circuits was done using the CadenceSpectre and EESof ADS software packages. The packages are very powerful but at
the same time quite complex. In order to get the simulation to properly execute,
there were many tricks that needed to be done.
192
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
A.2
A.2.1
193
Cadence Spectre
Time Domain Simulation
S-parameter Files
Cadence/Spectre is a time domain-based simulator. It is possible to use S-parameter
data files in the simulation via the nport component. Because of the time-domain
simulation requirement, S-parameter files are represented by inverse Fourier transforms. In the S-parameter information box, interpolation should be set to rational
for most S-parameter data sets.
Another important point is to insure that the data file goes down to DC if possible
(for example when simulating distributed elements such as transmission lines, inductors, etc.). For S-parameter data sets that do not go down to DC the simulator will
extrapolate based on the supplied values; this can lead to non-physical behaviour for
elements such as capacitors. To alleviate this problem, place additional self-generated
interpolation points in the data set to provide a skeleton for the Spectre-based interpolation. The results should be checked in an S-parameter simulation by themselves
to insure that non-physical behaviour is not observed.
When simulating using S-parameter components DC blocking capacitors should be
used to avoid incorrect DC conditions, even for elements that are inherently DC open
circuits (such as capacitors). Additional small-value resistors may also be placed
in series to avoid simulation problems that sometimes crop up. The order of the
series RC has been found to be important for some simulations; Figure A.1 shows
successfully- and unsuccessfully-simulated 2-port S-parameter blocks for measured
capacitor data in a transient simulation.
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
s2port
s2port
(a)
(b)
194
Figure A.1: Schematic-dependent S-parameter blocks for time domain (a) Successful
simulation (b) Unsuccessful simulation
A.2.2
DC Biasing
In practical VCO layouts DC biasing is often provided through a centre-tap of the
tank inductor for differential VCOs. Because of the limitations of S-parameter blocks
in time domain simulations, it is often necessary to feed DC bias voltage and current
through large inductors. If this is the case, (i) include a very small resistor in series
with each inductor (avoids short-circuit loops) and (ii) add a centre-grounded Tcircuit with large resistors to provide the differential ground reference. Figure A.2
shows the recommended centre-fed DC biasing circuit. This particular DC biasing
R=1e−3 L=1 H
R=1G
−
+
VDD
L=1 H
R=1e−3
R=1G
To Differential Circuit
Figure A.2: DC bias feed for differential VCO
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
195
configuration was found to have an effect on the closed-loop PLL during long-duration
simulations, because of the non-infinite nature of the inductor. It has been used
successfully in the sub-circuit simulations using shorter time spans.
A.2.3
Grounding for Phase Noise Analysis
When using Periodic Steady State (PSS) analysis in SpectreRF to determine phase
noise performance it is necessary to have a differential ground circuit. Figure A.3
shows a ground reference circuit that was used in a successful PSS simulation. The
ground reference should be placed in parallel with the nodes at which phase noise
is being calculated; in the case of a neg-gm LC-VCO, it would be placed across the
tank.
1 GΩ
To VCO
Tank
1 GΩ
To VCO
Tank
Figure A.3: Differential Ground Reference for VCO
A.3
A.3.1
Agilent EESof Advanced Design System
DC Biasing
Th DC biasing configuration of Fig. A.2 was found to have an effect on the closedloop PLL during long-duration simulations, because of the non-infinite nature of
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
196
the inductor. To avoid this issue, replace the large bias inductors with the DC
Feedthrough component, and any large blocking capacitors (such as at the input
ports to S-parameter files) with the DC Block component.
A.3.2
Long Duration Transient Analysis - Nodes Returning
Zero Voltage
Long duration transient analysis for the closed loop PLL circuit resulted in some
named nodes displaying zero voltage. Wire labels assigned to a node which also happens to be connected to a port component can result in zero-value returned voltages
for the wire label. Placing a current probe between the signal source and the pin of
the subnetwork and then labeling the node between the signal source and the current
probe can avoid the ”0” voltage problem.
A.3.3
HB Simulation of Injection Locked Frequency Divider
The simulation of the injection-locked frequency divider (ILFD) using harmonic balance (HB) requires care in the setup to successfully complete. The ILFD in a locked
state will oscillate at exactly one-half of the injected frequency for the design investigated. However, if the HB simulation fundamental frequency fILF D is set to exactly
fV CO /2, the HB will not converge due to multiple possible solutions. The method
to arrive at a successful solution is to set the fundamental frequency to a slightly
different value (for example, fILF D = fV CO /2.0000001). This allows the HB analysis
to arrive at distinct mathematical solutions for the VCO and ILFD frequencies. At
the second harmonic of fILF D the difference between 2fILF D and fV CO will be within
the resolution bandwidth of the solution, resulting in a single frequency element at
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
197
fV CO = 2fILF D . If an additional divide-by-2 stage is used, the fundamental frequency
should be set to fV CO /4.0000001.
When searching for an oscillator solution, it may be necessary to try several different harmonics/locations within the circuit. In the divide-by-4 case of the investigated
circuit, oscillator evaluation was undertaken at the VCO tank, with the oscillation
frequency set to 4 times the fundamental harmonic from the HB solution.
To determine the locking bandwidth of an ILFD, the following process was found
to be successful:
1. Run a Transient simulation on the circuit. Write the initial guess for HB.
2. Run HB analysis, with Transient Assisted Harmonic Balance (TAHB) set to
Auto. Use Initial Guess, with saved Transient initial guess file identified. Enable Oscillator Analysis at the node of interest, with the appropriate harmonic
number (eg., for a divide-by-4 structure, Harmonic Number is 4). Note the HB
solution for the fundamental frequency.
3. When HB simulation is confirmed correct, re-run the HB, but write the Final
Solution.
4. For next HB simulation, disable Oscillator Analysis. Set TAHB to off. Set
Harmonic Balance Assisted Harmonic Balance (HBAHB) to Auto; use Initial
Guess of saved HB final solution. Run HB simulation; the answer should be
very close to the TAHB solution. Re-run the HB and write the Final Solution.
This “golden” file is the starting point for the ILFD locking range investigation
- don’t write over it!
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
198
5. Change the input frequency to the ILFD. Use HBAHB with the “golden” initial
guess file. Write the final solution to a different file name.
6. Change the input frequency to the ILFD. Use HBAHB with the previouslygenerated final solution as the initial guess file; write the final solution. Repeat
this step until the HB simulation fails to converge. The final input frequency
that the HB simulation converged to is one limit of the ILFD locking range.
7. Reset the ILFD input frequency to the starting value. Use HBAHB with the
“golden” initial guess file; confirm that response is the same as previously calculated.
8. Change input frequency to the ILFD in the opposite direction. Use HBAHB
with the “golden” initial guess file. Write the final solution to a different file
name.
9. Change the input frequency to the ILFD. Use HBAHB with the previouslygenerated final solution as the initial guess file; write the final solution. Repeat
this step until the HB simulation fails to converge. The final input frequency
that the HB simulation converged to is the other limit of the ILFD locking
range.
The initial HB simulation must have the input frequency to the ILFD and the ILFD
self-resonant frequency lining up, otherwise the HB analysis will not arrive at the
correct solution. The frequency step size was found to be critical for injection locking
range determination, once the HB analysis converges to a solution. If too large a step
is taken, the HB analysis will not arrive at the correct solution, even if it is within
the actual locking range of the circuit.
APPENDIX A. SIMULATION OF HIGH FREQUENCY PLLS
A.3.4
199
Momentum
Ground References
When simulating layout elements such as transmission lines or inductors, each port
must have an associated ground reference. Omission of the ground reference may
result in errors in the S-parameter data.