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Transcript
Routing Considerations Signal Integrity Issues Capacitive Coupling, Resistance, Inductance »Cross talk » Routability design, Coding, and other Design Measures for protection I/O Design Packaging ELEN654 A TM Impact of Interconnect Parasitics • Reduce Robustness • Affect Performance • Increase delay • Increase power dissipation Classes of Parasitics • Capacitive • Resistive • Inductive ELEN654 A TM Capacitive Cross Talk X CXY VX Y CY ELEN654 A TM Capacitive Cross Talk Dynamic Node V DD CLK CXY Y In 1 In 2 In 3 CY PDN X 2.5 V 0V CLK 3 x 1 mm overlap: 0.19 V disturbance ELEN654 A TM Capacitive Cross Talk Driven Node 0.5 0.45 0.4 X VX RY CXY 0.3 Y CY tr↑ 0.35 tXY = RY(CXY+CY) 0.25 0.2 0.15 0.1 V (Volt) 0.05 0 0 0.2 0.4 0.6 0.8 1 t (nsec) Keep time-constant smaller than rise time ELEN654 A TM Dealing with Capacitive Cross Talk ELEN654 Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers A TM Shielding Shielding wire GND V DD Shielding layer GND Substrate (GND ) ELEN654 A TM Cross Talk and Performance - When neighboring lines switch in opposite direction of victim line, delay increases Cc DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES Miller Effect - Both terminals of capacitor are switched in opposite directions (0 Vdd, Vdd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) ELEN654 A TM Impact of Cross Talk on Delay r is ratio between capacitance to GND and to neighbor ELEN654 A TM Structured Predictable Interconnect V S G S V S S G S V S V Example: Dense Wire Fabric ([Sunil Kathri]) Trade-off: • Cross-coupling capacitance 40x lower, 2% delay variation • Increase in area and overall capacitance Also: FPGAs, VPGAs ELEN654 A TM Interconnect Projections Low-k dielectrics Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap Generation Dielectric Constant ELEN654 0.25 mm 3.3 0.18 mm 2.7 0.13 mm 2.3 0.1 mm 2.0 0.07 mm 1.8 e 0.05 mm 1.5 A TM Encoding Data Avoids WorstCase Conditions In Encoder Bus Decoder Out ELEN654 A TM Interconnects Information Theoretic Approach to Address Delay and Reliability in Long On-chip Interconnects ELEN654 A TM Overview ELEN654 A TM Sources of Error on Interconnects Capacitive Coupling Inductive Coupling Process Variations Power Noise ELEN654 A TM Signal Integrity Tradition: » Protect the signal on every single wire. » Design the clock period to be greater than the worst case delay. Questions asked? » Is it an overkill? » Can some errors be tolerated? » Can this be optimized? ELEN654 A TM Capacitive Coupling ELEN654 Signals are influenced by the signals in the adjacent wires due to coupling capacitance Phenomenon known as “Crosstalk” Results in “Deterministic” Delay Variations A TM Modeling Interconnects I(s) ELEN654 G(s) O(s) O(s) = G(s).I(s) A TM Modeling Interconnects I(s) G(s) O(s) Structure Capacitive Coupling ELEN654 A TM Modeling Interconnects I(s) G(s) O(s) Structure Inductive Coupling ELEN654 A TM Modeling Interconnects G(s) I(s) O(s) Randomness Power Noise ELEN654 A TM Modeling Interconnects I(s) G(s) O(s) Randomness Process Variations ELEN654 A TM Transfer Function ELEN654 O(s) = F(s).I(s) F(s) = (1 + L(s)C(s))1 A TM Bus Delay ELEN654 A TM Bus Delay ELEN654 A TM Waveform s ELEN654 A TM ELEN654 A TM Problems in Interconnects ELEN654 Delay Power Reliability A TM Binary Symmetric Channel Inputs, Outputs Є {0,1} Crossover Probability pe 1-pe 0 pe 1 ELEN654 0 pe 1-pe 1 A TM Self Information (of an event) Defined as » - log2(p) – p is the probability of occurrence. Example » if 1 occurs with p = ½, then every time it occurs -log2(1/2) = 1 bits of information is conveyed. ELEN654 A TM Entropy Entropy of a system of random events is the measure of uncertainty Defined as » H(S)= -Σ p.log2(p) – p is the probability of occurrence of each event in the system. Example: » For a random binary system – H = - p1.log2(p1) - p0.log2(p0) – If p1 = p0 = ½, H = 1 bit. ELEN654 A TM Conditional Entropy The uncertainty in one system, given the outcome of the second system. Defined as » H(S1|S2) = -Σ Σ pjk.log2(pjk/pk) – J and k are events in systems 1 and 2 respectively. – The equation represents the entropy of system1 conditioned upon the outcome of system 2. ELEN654 A TM Channel Capacity reduction in uncertainty about the input given the output C = H(Si) – H(Si|So) For p1 = p0 = ½ » C = 1 + pe.log2(pe) + (1-pe).log2(1-pe) ELEN654 A TM Channels with memory Have multiple states » A1, A2,…, An Each state has a probability of occurrence » p1,p2,…,pn Each state has a probability of error » pe1,pe2,…,pen Capacity of each state » Ci = 1 + pei log(pei) + (1+pei) log(1+pei) Capacity of channel » C=Σ pi Ci ELEN654 A TM The States ELEN654 A TM Capacity ELEN654 A TM Capacity ELEN654 A TM ELEN654 A TM ELEN654 A TM Concluding Remark » Non of the simple ad-hoc codes are approaching the capacity Current/Future work » Capacity-approaching bus codes.. and bus design ELEN654 A TM Driving Large Capacitances V DD V in V out CL • Transistor Sizing • Cascaded Buffers ELEN654 A TM Using Cascaded Buffers In Out 1 0.25 mm process Cin = 2.5 fF tp0 = 30 ps ELEN654 2 N CL = 20 pF F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns A TM Output Driver Design Trade off Performance for Area and Energy Given tpmax find N and f Area f 1 F 1 A 1 f f ... f A A A f 1 f 1 2 N N 1 driver Energy min 2 Edriver 1 f f 2 ... f N 1 CiVDD ELEN654 min min F 1 C 2 2 CiVDD L VDD f 1 f 1 A TM Delay as a Function of F and N 10,000 F = 10,000 tp/tp0 1000 p t/t0 p 100 F = 1000 10 1 3 5 7 F = 100 9 11 Number of buffer stages N ELEN654 A TM Output Driver Design 0.25 mm process, CL = 20 pF Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns ELEN654 A TM How to Design Large Transistors D(rain) Multiple Contacts Reduces diffusion capacitance Reduces gate resistance S(ource) G(ate) small transistors in parallel ELEN654 A TM Bonding Pad Design Bonding Pad GND 100 mm Out VDD ELEN654 In GND Out A TM ESD Protection ELEN654 When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate – need guard rings to pick it up. A TM ESD Protection V DD R D1 X PAD D2 C Diode ELEN654 A TM Chip Packaging Bonding wire •Bond wires (~25mm) are used to connect the package to the chip Chip L Mounting cavity L´ Lead frame • Pads are arranged in a frame around the chip • Pads are relatively large (~100mm in 0.25mm technology), with large pitch (100mm) Pin •Many chips areas are ‘pad limited’ ELEN654 A TM Pad Frame Layout ELEN654 Die Photo A TM Chip Packaging An alternative is ‘flip-chip’: » » » » ELEN654 Pads are distributed around the chip The soldering balls are placed on pads The chip is ‘flipped’ onto the package Can have many more pads A TM Tristate Buffers V DD V DD En En Out Out In En In En Increased output drive Out = In.En + Z.En ELEN654 A TM Reducing the swing tpHL = CL Vswing/2 Iav Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal level Frequently designed differentially (e.g. LVDS) ELEN654 A TM Single-Ended Static Driver and Receiver VDD VDD VDD VDD L Out In VDD L Out CL driver ELEN654 receiver A TM Dynamic Reduced Swing Network f VDD VDD M2 M4 Bus In1.f M1 In2.f Cbus Out M3 Cout 2.5 V 2 V asym bus V 1.5 V(Volt) 1 sym f 0.5 0 ELEN654 0 2 4 6 time (ns) 8 10 12 A TM Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: » IR drop » Voltage variations ELEN654 Power supply is distributed to minimize the IR drop and the change in current due to switching of gates A TM RI Introduced Noise V DD f pre I R9 V DD 2 D V 9 X M1 I DV DV R ELEN654 A TM Power Dissipation Trends 160 140 120 100 80 60 40 20 0 3.5 2.5 2 1.5 1 0 EV4 EV5 EV6 EV7 EV8 Supply Current 3.5 120 3 100 2.5 80 2 60 1.5 40 1 20 0.5 0 Better cooling technology needed Supply current is increasing faster! OnOn-chip signal integrity will be a major issue Power and current distribution are critical Opportunities to slow power growth Voltage (V) Current (A) 0.5 140 Power consumption is increasing 3 Voltage (V) Power (W) Power Dissipation Accelerate Vdd scaling Low κ dielectrics & thinner (Cu) interconnect SOI circuit innovations Clock system design micromicro-architecture L o w κ d i e l e c t r i c s & t h i n n e r ( C u ) 0 EV4 EV5 EV6 EV7 EV8 ASP DAC 2000 ELEN654 19 A TM Resistance and the Power Distribution Problem After Before • Requires fast and accurate peak current prediction • Heavily influenced by packaging technology ELEN654 Source: Cadence A TM Power Distribution ELEN654 Low-level distribution is in Metal 1 Power has to be ‘strapped’ in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps A TM Power and Ground Distribution GND VDD Logic Logic VDD GND (a) Finger-shaped network ELEN654 VDD GND (b) Network with multiple supply pins A TM 3 Metal Layer Approach (EV4) 3rd “coarse and thick” metal layer added to the technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 Metal 1 ELEN654 Courtesy Compaq A TM 4 Metal Layers Approach (EV5) 4th “coarse and thick” metal layer added to the technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 2 Metal 1 ELEN654 Courtesy Compaq A TM 6 Metal Layer Approach – EV6 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Significantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd Metal 4 Metal 3 RP1/Vss Metal 2 Metal 1 ELEN654 Courtesy Compaq A TM Electromigration (1) Limits dc-current to 1 mA/mm ELEN654 A TM Electromigration (2) ELEN654 A TM Resistivity and Performance Tr The distributed rc-line R1 RN-1 R2 C1 C2 RN CN-1 CN Vin 2.5 Delay ~ L2 x = L/4 voltage (V) Diffused signal propagation x= L/10 2 1.5 x = L/2 1 x= L 0.5 0 ELEN654 0 0.5 1 1.5 2 2.5 3 time (nsec) 3.5 4 4.5 5 A TM The Global Wire Problem Td 0.377 RwCw 0.693Rd Cout Rd Cw RwCout Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions » Use of fat wires » Insert repeaters — but might become prohibitive (power, area) » Efficient chip floorplanning Towards “communication-based” design » How to deal with latency? » Is synchronicity an absolute necessity? ELEN654 A TM Interconnect Projections: Copper Copper is planned in full sub-0.25 mm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 mW-cm vs. 3.5 for Al(Cu) 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97) » Electromigration is a limiting factor beyond 0.18 mm if Al is used (HP, IEDM95) ELEN654 Vias A TM Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: = 2.2 mW-cm M6 • Increasing die size and device count: we need more wires and longer wires to connect everything Tins • Rising need for a hierarchical wiring network; M5 W local wires with high density and global wires with low RC S M4 H 3.5 Minimum Widths (Relative) 4.0 3.5 3.0 M3 3.0 2.5 2.5 2.0 M2 1.5 M1 1.0 poly 0.5 0.25 mm wiring stack 0.0 M5 M4 M3 M2 substrate ELEN654 Minimum Spacing (Relative) M5 2.0 M4 M3 1.5 M1 1.0 Poly 0.5 M2 M1 Poly 0.0 m m m m m m m m m m A TM Diagonal Wiring destination diagonal y source x Manhattan • 20+% Interconnect length reduction • Clock speed Signal integrity Power integrity • 15+% Smaller chips plus 30+% via reduction ELEN654 Courtesy Cadence X-initiative A TM Using Bypasses Driver WL Polysilicon word line Metal word line Driving a word line from both sides Metal bypass WL K cells Polysilicon word line Using a metal bypass ELEN654 A TM Reducing RC-delay Repeater ELEN654 A TM Repeater Insertion (Revisited) Taking the repeater loading into account For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer! ELEN654 A TM Inductance Issues L di/dt V DD L i(t) V ’DD V out V in CL Impact of inductance on supply voltages: • Change in current induces a change in voltage • Longer supply lines have larger L GND ’ L ELEN654 A TM 2.5 2.5 2 2 1.5 1.5 out (V) L di/dt: Simulation 1 0.5 0.5 V 1 0 0 0 0.5 1 1.5 2 x 10 Without inductors With inductors 0.02 0 decoupled 0 0.5 1 1.5 1 1.5 2 x 10 -9 0.02 0 0 0.5 1 1.5 -9 x 10 1 0.5 2 -9 0.5 L V (V) 2 x 10 1 0.5 0.04 L i (A) 0.04 0 -9 0 0 0 0.5 1 time (nsec) 1.5 2 x 10 -9 Input rise/fall time: 50 psec ELEN654 0 0.5 1 time (nsec) 1.5 2 x 10 -9 Input rise/fall time: 800 psec A TM Dealing with Ldi/dt ELEN654 Separate power pins for I/O pads and chip core. Multiple power and ground pins. Careful selection of the positions of the power and ground pins on the package. Increase the rise and fall times of the off-chip signals to the maximum extent allowable. Schedule current-consuming transitions. Use advanced packaging technologies. Add decoupling capacitances on the board. Add decoupling capacitances on the chip. A TM Choosing the Right Pin Bonding wire Chip L Mounting cavity L´ Lead frame Pin ELEN654 A TM Decoupling Capacitors 1 Board wiring Bonding wire Cd SUPPLY CHIP 2 Decoupling capacitor Decoupling capacitors are added: • on the board (right under the supply pins) • on the chip (under the supply straps, near large buffers) ELEN654 A TM De-coupling Capacitor Ratios EV4 » total effective switching capacitance = 12.5nF » 128nF of de-coupling capacitance » de-coupling/switching capacitance ~ 10x EV5 » 13.9nF of switching capacitance » 160nF of de-coupling capacitance EV6 » 34nF of effective switching capacitance » 320nF of de-coupling capacitance -- not enough! Source: B. Herrick (Compaq) ELEN654 A TM EV6 De-coupling Capacitance Design for Idd= 25 A @ Vdd = 2.2 V, f = 600 MHz » 0.32-µF of on-chip de-coupling capacitance was added – Under major busses and around major gridded clock drivers – Occupies 15-20% of die area » 1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” decoupling – 160 Vdd/Vss bondwire pairs on the WACC minimize inductance ELEN654 Source: B. Herrick (Compaq) A TM EV6 WACC 389 Signal - 198 VDD/VSS Pins 389 Signal Bondwires 395 VDD/VSS Bondwires 320 VDD/VSS Bondwires WACC Microprocessor Heat Slug 587 IPGA ELEN654 Source: B. Herrick (Compaq) A TM The Transmission Line l V in l r l r g c l r g c x g c r V out g c The Wave Equation ELEN654 A TM Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight). tr (tf) << 2.5 tflight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z0/2 ELEN654 A TM Should we be worried? Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] ELEN654 A TM Matched Termination Z0 Z0 ZL Series Source Termination ZS Z0 Z0 Parallel Destination Termination ELEN654 A TM Segmented Matched Line Driver In VDD Z0 s0 s1 c1 ELEN654 s2 c2 ZL sn cn GND A TM Parallel Termination─ Transistors as Resistors V dd )V Mr Out Vdd Mr V dd M rp M rn V bb Out ELEN654 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0 Out NMOS only PMOS only NMOS-PMOS PMOS with-1V bias Normalized Resis 0.5 1 1.5 V R (Volt) 2 2.5 A TM Output Driver with Varying Terminations 4 V d 3 V V 2 V DD in s 1 L = 2.5 nH 120 L = 2.5 nH V in 275 Vs Z 0 = 50 W C L= 5 pF Clamping Diodes 0 V DD 1 0 Vd 1 2 3 4 5 6 7 8 Initial design CL 4 3 L= 2.5 nH o(V) ut V V 2 V V d in s 1 0 1 o(V) ut V ELEN654 0 1 2 3 4 5 6 7 8 time (sec) Revised design with matched driver impedance A TM The “Network-on-a-Chip” Embedded Processors Memory Sub-system Interconnect Backplane Accelators ELEN654 Configurable Accelerators Peripherals A TM