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The Design Process
CPSC 321 Computer Architecture
Andreas Klappenecker
Administrative Issues
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October 10, project deadline
October 17, midterm exam
Office hours
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Klappenecker TW 2:00pm-3:00pm
Bhojwani M 10:00-11:00am, T 1:00-2:00pm
Goyal W 2:00-4:00pm
Levels of Abstraction
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Specification
Architectural Description
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Logic Design
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Gates and Registers
Circuit Design
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Verilog, VHDL, ELLA or other HDLs
Transistors sized for power and speed
Technology mapping
Layout
Levels of Abstraction
System
Module
Gate
Circuits
Device
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+
G
S
n+
D
n+
MOS Transistors
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PMOS transistor
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like a switch
ON if gate is 1
OFF if gate is 0
Current Flow
Source (+)
Drain (-)
NMOS transistor
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OFF if gate is 1
ON if gate is 0
Drain (+)
Source (-)
CMOS Circuits
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Simple
Avoids difficulties
Resilient
Energy efficient
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Current flow only during
switching time
Circuit Design
Layout
Layering and
Fabrication
Hardware Description Languages
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Abstracting from circuits
Structural description
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Behavioral description
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Specify full adder by NAND and NOR gates
Specify full adder by functional behavior
Improves productivity
Natural for Computer Scientists
Verilog
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Structural description
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Gates, wires, input/output
Hierarchical description possible
(define full adder in terms of gates)
Behavioral description
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Abstract formulation
Functional relationships
Structural Verilog Example
module mux(f, a,b,sel);
output f;
input a,b,sel;
wire f1, f2;
not(nsel,
sel);
and(f1, a,nsel);
and(f2, b, sel);
or (f, f1,
endmodule
f2);
b
a
sel
f
Behavioral Verilog Example
module mux2(f, a,b,sel);
output f;
input a,b,sel;
assign f = (a & ~sel) | (b & sel);
endmodule
Another Example
module mux2(f, a,b,sel);
output f;
input a,b,sel;
reg f;
always @(a or b or sel)
if (sel==1)
f = b;
else
f = a;
endmodule
Synthesis
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Compilation
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Optimization
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Verilog code is translated into
a network of logic gates
Try to find a better solution by logic
optimization (limited success)
Technology mapping
Physical design
Logic Gates
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and(y, a, b)
or(y, a, b)
not(y, a)
xor(y, a,b)
nand(y, a, b)
…
Modules
module mod_name (parameters);
input …
output …
reg …
……
endmodule
Full Adder
module fulladd(cin, x, y, s, cout)
input cin, x, y;
output s, cout;
assign s = x ^ y ^ cin;
assign cout = (x & y) | (cin & x) | (cin & y);
endmodule
Full Adder
module fulladd(cin, x,y,s, cout);
input cin, x, y;
output s, cout;
assign { cout, s } = x + y + cin;
Endmodule
The assign statement sets cout to MSB and s to LSB
Conclusions
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Verilog will be the language for our next
projects
Verilog compilers are freely available
Programming in a HDL differs from
software programming
Higher level of abstraction allows to
develop large circuits