Download CMOS Gates

COMBINATIONAL
LOGIC
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
Combinational vs. Sequential Logic
In
Combinational
Logic
Circuit
In
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
EE415 VLSI Design
Sequential
Output = f(In, Previous In)
Out
Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
In2
PUN
InN
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
F(In1,In2,…InN)
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
EE415 VLSI Design
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE415 VLSI Design
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
EE415 VLSI Design
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
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CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
D
CL
Complementary CMOS Logic Style
EE415 VLSI Design
Example Gate: NAND
EE415 VLSI Design
Example Gate: NOR
EE415 VLSI Design
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
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C
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
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Cell Design

Standard Cells
» General purpose logic
» Can be synthesized
» Same height, varying width

Datapath Cells
» For regular, structured designs (arithmetic)
» Includes some wiring in the cell
» Fixed height and width
EE415 VLSI Design
Standard Cell Layout
Methodology – 1980s
Routing
channel
VDD
signals
GND
EE415 VLSI Design
Standard Cell Layout
Methodology – 1990s
Mirrored Cell
No Routing
channels
VDD
VDD
M2
M3
GND
Mirrored Cell
EE415 VLSI Design
GND
Standard Cells
N Well
VDD
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects
Cell height is “12 pitch”
2
Cell boundary
EE415 VLSI Design
In
Out
GND
Rails ~10
Standard Cells
With minimal
diffusion
routing
VDD
VDD
With silicided
diffusion
VDD
M2
In
Out
In
Out
In
M1
GND
EE415 VLSI Design
GND
Out
Standard Cells
2-input NAND gate
VDD
VDD
B
A
B
Out
A
GND
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Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
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GND
A B
Stick Diagrams
Logic Graph
X
A
PUN
C
j
C
B
i
X
X = C • (A + B)
C
B
VDD
j
i
A
GND
B
A
B
C
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A
PDN
Two Versions of C • (A + B)
A
C
B
A
B
C
VDD
VDD
X
GND
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X
GND
Consistent Euler Path
X
C
i
X
B
VDD
j
GND
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A
A B C
OAI22 Logic Graph
A
C
B
D
X
D
X = (A+B)•(C+D)
C
D
A
B
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C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
Example: x = ab+cd
x
x
c
b
VDD
x
a
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
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c
b
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
EE415 VLSI Design
Properties of Complementary CMOS
Gates Snapshot
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
EE415 VLSI Design
CMOS Circuit Styles


Static complementary CMOS - except during switching, output
connected to either VDD or GND via a low-resistance path
» high noise margins
– full rail to rail swing
– VOH and VOL are at VDD and GND, respectively
» low output impedance, high input impedance
» no steady state path between VDD and GND (no static power
consumption)
» delay a function of load capacitance and transistor resistance
» comparable rise and fall times
Dynamic CMOS - relies on temporary storage of signal values on the
capacitance of high-impedance circuit nodes
» simpler, faster gates
» increased sensitivity to noise
EE415 VLSI Design
Switch Delay Model
Req
A
Rp
A
A
Rp
Rp
B
B
Rp
Rn
CL
Rp
A
Cint
A
B
Rn
Rn
Cint
A
A
NAND2
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CL
Rn
Rn
A
B
CL
NOR2
INV
Input Pattern Effects on Delay
Rp
A
Rp
B
Rn


» both inputs go low
CL
– delay is 0.69 Rp/2 CL
B
Rn
A
Delay is dependent on
the pattern of inputs
Low to high transition
» one input goes low
Cint
– delay is 0.69 Rp CL

High to low transition
» both inputs go high
– delay is 0.69 2Rn CL
EE415 VLSI Design
Delay Dependence on Input Patterns
3
A=B=10
2.5
Voltage [V]
2
A=1 0, B=1
1.5
A=1, B=10
1
0.5
0
-0.5
0
100
200
time [ps]
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300
400
Input Data
Pattern
Delay
(psec)
A=B=01
67
A=1, B=01
64
A= 01, B=1
61
A=B=10
45
A=1, B=10
80
A= 10, B=1
81
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
Transistor Sizing
Rp
2 A
Rp
B
Rn
2
B
2
Rn
A
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Rp
4 B
2
CL
Cint
Rp
4
Cint
A
1
Rn
Rn
A
B
CL
1
Transistor Sizing a Complex
CMOS Gate
A
B
8 6
C
8 6
4 3
D
4 6
OUT = D + A • (B + C)
A
D
1
B
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2
2C
2
Fan-In Considerations
A
B
C
D
A
CL
B
C3
C
C2
D
C1
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Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
tp as a Function of Fan-In
1250
quadratic
tp (psec)
1000
Gates with a
fan-in
greater than
4 should be
avoided.
750
tpH
500
tp
L
250
tpL
linear
H
0
2
4
6
8
fan-in
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10
12
14
16
tp as a Function of Fan-Out
tpNOR2
All gates
have the
same drive
current.
tpNAND2
tp (psec)
tpINV
Slope is a
function of
“driving
strength”
2
4
6
8
10
eff. fan-out
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12
14
16
Problems with Complementary CMOS
•Gate with N inputs requires 2N transistors
•other circuit styles use N+1 transistors
•tp deteriorates with high fan-in
•increases total capacitance
•series connected transistors slows down gate
•fan-out loads down gate
•1 fan-out = 2 gate capacitors (PMOS and NMOS)
t p  a1FI  a2 FI  a3 FO
2
EE415 VLSI Design
Fast Complex Gates:
Design Technique 1

Transistor sizing
» as long as fan-out capacitance dominates

Progressive sizing
InN
CL
MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
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Distributed RC line
M1 > M2 > M3 > … > MN
(the fet closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks
Fast Complex Gates:
Design Technique 2

Transistor ordering
critical path
In3 1 M3
charged
CL
In2 1 M2
C2 charged
In1
M1
01
C1 charged
delay determined by time to
discharge CL, C1 and C2
EE415 VLSI Design
critical path
01
In1
M3
CLcharged
In2 1 M2
C2 discharged
In3 1 M1
C1 discharged
delay determined by time to
discharge CL
Fast Complex Gates:
Design Technique 3

Alternative logic structures
F = ABCDEFGH
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Fast Complex Gates:
Design Technique 4

Isolating fan-in from fan-out using buffer
insertion
CL
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CL
Fast Complex Gates:
Design Technique 5

Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )
» linear reduction in delay
» also reduces power consumption


But the following gate is much slower!
Or requires use of “sense amplifiers” on the
receiving end to restore the signal level
(memory design)
EE415 VLSI Design
Sizing Logic Paths for Speed





Frequently, input capacitance of a logic path
is constrained
Logic also has to drive some capacitance
Example: ALU load in an Intel’s
microprocessor is 0.5pF
How do we size the ALU datapath to achieve
maximum speed?
We have already solved this for the inverter
chain – can we generalize it for any type of
logic?
EE415 VLSI Design
Buffer Example
In
Out
1
2
N
CL
N
Delay    pi  g i  f i 
i 1
(in units of tinv)
For given N: Ci+1/Ci = Ci/Ci-1
To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
EE415 VLSI Design
Logical Effort

CL 

Delay  k  RunitCunit 1 
 Cin 
t p  g  f 
p – intrinsic delay (3kRunitCunit) - gate parameter  f(W)
g – logical effort (kRunitCunit) – gate parameter  f(W)
f – effective fanout
Normalize everything to an inverter:
ginv =1, pinv = 1
Divide everything by tinv
(everything is measured in unit delays tinv)
EE415 VLSI Design
Assume  = 1.
Delay in a Logic Gate
Gate delay:
d=h+p
effort delay
intrinsic delay
Effort delay:
h=gf
logical
effort
effective fanout =
Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
EE415 VLSI Design
Logical Effort



Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
Logical effort increases with the gate
complexity
EE415 VLSI Design
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD
A
VDD
A
2
2
B
F
2
F
A
A
VDD
B
4
A
4
2
F
1
A
B
Inverter
g=1
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1
B
2
2-input NAND
g = 4/3
2-input NOR
g = 5/3
1
Normalized delay (d)
Logical Effort of Gates
t pNAND
g=
p=
d=
t pINV
g=
p=
d=
F(Fan-in)
1
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2
3
4
5
Fan-out (h)
6
7
Normalized delay (d)
Logical Effort of Gates
t pNAND
g = 4/3
p=2
d = (4/3)h+2
t pINV
g=1
p=1
d = h+1
F(Fan-in)
1
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2
3
4
5
Fan-out (h)
6
7
4/
3;
p
=
2
Logical Effort of Gates
=
D:
g
tN
AN
=
g
r:
e
t
er
1;
p=
1
v
in
3
pu
4
In
2-
Normalized Delay
5
Effort
Delay
2
1
Intrinsic
Delay
1
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2
3
Fanout f
4
5
Add Branching Effort
Branching effort:
b
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Con path  Coff  path
Con path
Multistage Networks
N
Delay    pi  g i  f i 
i 1
Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Sdi = Spi + Shi
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Optimum Effort per Stage
When each stage bears the same effort:
hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i  h g i
Minimum path delay
Dˆ   gi f i  pi   NH 1/ N  P
EE415 VLSI Design
Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D  NH 1/ N  Npinv
D
  H 1/ N ln H 1/ N  H 1/ N  pinv  0
N


Substitute ‘best stage effort’
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hH
1/ Nˆ
Logical Effort
From Sutherland, Sproull
EE415 VLSI Design
Example: Optimize Path
1
g=1
f=a
a
b
g = 5/3
g = 5/3
f = c/b
f = b/a
Effective fanout, F =
G=
H=
h=
a=
b=
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c
5
g=1
f = 5/c
Example: Optimize Path
1
g=1
f=a
b
a
g = 5/3
f = b/a
c
5
g = 5/3
f = c/b
Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
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g=1
f = 5/c
Example: Optimize Path
1
g1 = 1
b
a
g2 = 5/3
c
5
g3 = 5/3
Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59
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g4 = 1
Example – 8-input AND
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Method of Logical Effort





Compute the path effort: F = GBH
Find the best number of stages N ~ log4F
Compute the stage effort f = F1/N
Sketch the path with this number of stages
Work either from either end, find sizes:
Cin = Cout*g/f
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.
EE415 VLSI Design
Summary
Sutherland,
Sproull
Harris
EE415 VLSI Design
Ratio Based Logic
V DD
Resistive
Load
V DD
Depletion
Load
RL
PDN
V SS
(a) resistive load
PMOS
Load
V SS
VT < 0
F
In 1
In 2
In 3
V DD
F
In 1
In 2
In 3
PDN
V SS
(b) depletion load NMOS
F
In 1
In 2
In 3
PDN
V SS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
EE415 VLSI Design
Ratio Based Logic
VDD
• N transistors + Load
Resistive
Load
• V OH = V DD
RL
• V OL =
F
In1
In2
In3
RDN + RL
VDD
• Asymmetrical response
PDN
• Static power consumption
VSS
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RDN
• tpLH= 0.69 RL CL
t pHL  0.69RL || RPDN C L
Ratio Based Logic Problems
Problems with Resistive Load
•IL = (VDD – Vout) / RL
•Charging current drops rapidly once Vout starts to rise
Solution: Use a current source!
•Available current is independent of voltage
•Reduces tpLH by 25%
EE415 VLSI Design
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
VSS
depletion load NMOS
EE415 VLSI Design
F
In1
In2
In3
PDN
VSS
pseudo-NMOS
Active Loads
Depletion mode NMOS load
•VGS = 0
•IL ~ (kn, load / 2) (|VTn|)2
•Deviates from ideal current source
•Channel length modulation
•Body effect
•VSB != VDD
•varies with Vout
•reduces |VTn|, hence IL gets smaller for increasing Vout
EE415 VLSI Design
Active Loads
Pseudo-NMOS load
•No body effect, VSB = 0V
•VGS = - VDD , higher load current
•IL = (kp / 2) (VDD - |VTn|)2
•Larger VGS causes pseudo-NMOS load to leave
saturation mode sooner than NMOS
EE415 VLSI Design
Load Lines of Ratioed Gates
IL(Normalized)
1
Current source
0.75
0.5
Pseudo-NMOS
Depletion load
0.25
Resistive load
0
0.0
EE415 VLSI Design
1.0
2.0
3.0
Vout (V)
4.0
5.0
Pseudo-NMOS
VDD
A
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
2
V OL
kp


2
k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
2 
2

kp
V OL =  VDD – V T  1 – 1 – -----(assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
EE415 VLSI Design
Pseudo-NMOS NAND Gate
VDD
Out
GND
EE415 VLSI Design
Pseudo-NMOS VTC
3.0
2.5
W/Lp = 4
Vout [V]
2.0
1.5
W/Lp = 2
1.0
0.5
W/Lp = 0.5
W/Lp = 1
W/Lp = 0.25
0.0
0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
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Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
B
C
D
Adaptive Load
EE415 VLSI Design
CL
Improved Loads (2)
VDD
M1
VDD
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
Differential Cascode Voltage Switch Logic (DCVSL)
EE415 VLSI Design
DCVSL Example
Out
Out
B
B
A
B
B
A
XOR-NXOR gate
EE415 VLSI Design
DCVSL Transient Response
V olta ge [V]
2.5
AB
1.5
0.5
-0.5 0
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AB
A,B
0.2
A,B
0.4
0.6
Time [ns]
0.8
1.0
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
EE415 VLSI Design
Example: AND Gate
B
A
B
F = AB
0
EE415 VLSI Design
NMOS-Only Logic
3.0
In
1.5m/0.25m
VDD
x
0.5m/0.25m
Out
0.5m/0.25m
Voltage [V]
In
Out
2.0
x
1.0
0.0
0
0.5
1
Time [ns]
EE415 VLSI Design
1.5
2
NMOS-only Switch
C = 2.5V
C = 2.5 V
M2
A = 2.5 V
A = 2.5 V
B
B
Mn
CL
M1
VB does not pull up to 2.5V, but 2.5V - VTN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
EE415 VLSI Design
NMOS Only Logic:
Level Restoring Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
EE415 VLSI Design
Restorer Sizing
Voltage [V]
3.0
2.0
•Upper limit on restorer size
•Pass-transistor pull-down
can have several transistors in
stack
W/Lr =1.75/0.25
W/L r =1.50/0.25
1.0
W/Lr =1.0/0.25
0.0
0
100
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200
W/L r =1.25/0.25
300
Time [ps]
400
500
Solution 2: Single Transistor Pass Gate
with VT=0
VDD
VDD
0V
2.5V
VDD
0V
Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
EE415 VLSI Design
Complementary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
EE415 VLSI Design
A
F=AÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
EXOR/NEXOR
F=AÝ
Solution 3: Transmission Gate
C
A
C
A
B
B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
EE415 VLSI Design
Resistance of Transmission Gate
30
2.5 V
Resistance, ohms
Rn
20
Rp
2.5 V
Rn
Vou t
Rp
10
0
0.0
EE415 VLSI Design
0V
Rn || Rp
1.0
Vou t , V
2.0
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
EE415 VLSI Design
In2
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
EE415 VLSI Design
Delay in Transmission Gate Networks
2.5
2.5
V1
In
2.5
Vi
Vi-1
C
0
2.5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
(c)
EE415 VLSI Design
CC
Vn
C
Delay Optimization
EE415 VLSI Design
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
S Sum Generation
Ci
P
B
Setup
P
Co Carry Generation
P
Similar delays for sum and carry
EE415 VLSI Design
VDD
A
Ci
A
VDD
Dynamic CMOS

In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
» fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
» requires on n + 2 (n+1 N-type + 1 P-type)
transistors
EE415 VLSI Design
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
CL
PDN
Clk
A
C
B
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
EE415 VLSI Design
1
Out
((AB)+C)
off
Me on
Conditions on Output



Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL
EE415 VLSI Design
Properties of Dynamic Gates

Logic function is implemented by the PDN only
» number of transistors is N + 2 (versus 2N for static complementary
CMOS)



Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect
the logic levels
Faster switching speeds
» reduced load capacitance due to lower input capacitance (Cin)
» reduced load capacitance due to smaller output loading (Cout)
» no Isc, so all the current provided by PDN goes into discharging CL
EE415 VLSI Design
Properties of Dynamic Gates

Overall power dissipation usually higher than static
CMOS
» no static current path ever exists between VDD and GND
(including Psc)
» no glitching
» higher transition probabilities
» extra load on Clk

PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
» low noise margin (NML)

Needs a precharge/evaluate clock
EE415 VLSI Design
Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
EE415 VLSI Design
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
EE415 VLSI Design
Issues in Dynamic Design 2:
Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
CA
Me
EE415 VLSI Design
CB
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
reduced robustness
Charge Sharing Example
Clk
A
A
B
B
B
Cc=15fF
C
C
Ca=15fF
Clk
EE415 VLSI Design
Out
CL=50fF
!B
Cb=15fF
Cd=10fF
Charge Sharing
VDD
case 1) if V out < VTn
VDD
Mp
Clk

Mp
Out
Out C
Ma
A
Ma X
X
A
B0
Mb
B=0
Clk

Mb
Me
Me
EE415 VLSI Design
CL
L
C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
or
Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
CL
Ca
Ca
Cb
Cb
case 2) if V out > VTn
Ca 
 ---------------------
Vout = –V DD 
 Ca + CL 
Solution to Charge
Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
EE415 VLSI Design
Issues in Dynamic Design 3:
Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Out2 =0
CL2
B=0
Clk
Me
Dynamic NAND
EE415 VLSI Design
Static NAND
In
Backgate Coupling Effect
3
2
Out1
1
Clk
0
In
Out2
2
Time, ns
-1
0
EE415 VLSI Design
4
6
Issues in Dynamic Design 4:
Clock Feedthrough
Clk
Mp
A
CL
B
Clk
Out
Me
EE415 VLSI Design
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
In2
1.5
In3
In &
Clk
0.5
In4
Clk
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
EE415 VLSI Design
Other Effects
Capacitive coupling
 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)

EE415 VLSI Design
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0  1 transitions allowed at inputs!
EE415 VLSI Design
Domino Logic
Clk
In1
In2
In3
Clk
EE415 VLSI Design
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
00
01
In4
In5
Clk
PDN
Me
Out2
Why Domino?
Clk
Ini
Inj
Clk
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
EE415 VLSI Design
Ini
Inj
PDN
Properties of Domino Logic


Only non-inverting logic can be implemented
Very high speed
» static inverter can be skewed, only L-H transition
» Input capacitance reduced – smaller logical effort
EE415 VLSI Design
Designing with Domino Logic
VDD
VDD
VDD
Clk
Mp
Clk
Mp
Out1
Mr
Out2
In1
In2
In3
PDN
PDN
In4
Can be eliminated!
Clk
Me
Clk
Inputs = 0
during precharge
EE415 VLSI Design
Me
Footless Domino
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
0
1
0
In3
1
0
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
EE415 VLSI Design
Inn
1
0
1
Differential (Dual Rail)
Domino
off
Mp Mkp
Clk
Out = AB
1
on
Mkp
0
Clk
Mp
1
A
!A
0
!B
B
Clk
Me
Solves the problem of non-inverting logic
EE415 VLSI Design
Out = AB
np-CMOS
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Me
In4
In5
PUN
00
01
Clk
Mp
Out2
(to PDN)
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
EE415 VLSI Design
NORA Logic
Clk
In1
In2
In3
Clk
Mp
11
10
Out1
PDN
Me
In4
In5
PUN
00
01
Clk
Me
to other
PDN’s
WARNING: Very sensitive to noise!
EE415 VLSI Design
Clk
Mp
Out2
(to PDN)
to other
PUN’s
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
Co = AB + C i(A+B)
EE415 VLSI Design
28 transistors
A
B
A Revised Adder Circuit
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
B
A
B
Ci
A
B
24 transistors
EE415 VLSI Design