Download The Inverter

THE INVERTER
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
DIGITAL GATES
Fundamental Parameters
The key parameters that govern a digital
gate’s performance and usability.



Area and Complexity
Functionality and Robustness (Reliability)
Performance
» Speed (delay)
» Power Consumption (dissipation)
» Energy
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Area and Complexity
•Small area very desirable for digital gate
•higher integration density
•smaller die size
•lower fabrication cost
•faster (smaller Cg)
•Implementation area
•depends on number of transistors
•interconnection area
EE415 VLSI Design
Functionality and Robustness
•Prime requirement for digital gate:
•perform designed function
•Measured behavior deviates from expected response. Why?
•variations in process
•noise (unwanted variations of voltages and currents at the
logic nodes)
•Logic levels
•VOH and VOL represent high and low logic levels
•difference is called the logic swing
EE415 VLSI Design
Noise in Digital Integrated Circuits
v(t)
VDD
i(t)
(a) Inductive coupling
(b) Capacitive coupling
(c) Power and ground
noise
EE415 VLSI Design
The Voltage-Transfer Characteristic
•Electrical function of gate is best expressed by its
voltage-transfer characteristic (VTC)
(DC transfer characteristic)
•Plots Vout =f(Vin)
•Gate (Switching) logic threshold voltage, VM:
•VM=f(VM)
•intersection of VTC at Vout=Vin
EE415 VLSI Design
DC Operation:
Voltage Transfer Characteristic (VTC)
V(y)
V(x)
V
OH
f
V(y)=V(x)
V
Switching Threshold
M
VOL
VOL
V
OH
V(x)
Nominal Voltage Levels
EE415 VLSI Design
V(y)
Mapping between analog and digital signals
Problem:
•Output signal deviates from expected nominal value due
to:
•noise
•loading of the gate output
Solution:
•Logic levels represented by range of acceptable values
•Regions of acceptable values delimited by VIH and VIL
•represents points in VTC where (dVout/dVin) = -1
•undefined region known as transition width
EE415 VLSI Design
Mapping between analog and digital signals
"1"
V
OH
V
IH
V(y)
V
OH
Slope = -1
Undefined
Region
V
IL
"0"
V
OL
EE415 VLSI Design
Slope = -1
VOL
V
V
IL IH
V(x)
Noise Margins
•Measure of a gate sensitivity to noise
•Quantize the size of legal “0” and “1”
•Represents level of noise that can be tolerated when gates
are cascaded
•NML (noise margin low)
NML = VIL - VOL
•NMH (noise margin high)
NMH = VOH - VIH
•Should be large as possible for good noise immunity
EE415 VLSI Design
Definition of Noise Margins
"1"
V
OH
NMH
V
IH
Undefined
Region
Noise Margin High
Noise Margin Low
NML
V
V
IL
OL
"0"
Gate Output
EE415 VLSI Design
Gate Input
The Regenerative Property
•Large noise margin alone not sufficient for proper
operation
•Gate must “boost” weak levels back to nominal
values
•Known as regeneration (of levels)
•Non-regenerative gate output will converge to
intermediate value
•Conditions for regeneration:
•VTC transient region gain >1 (absolute value)
•Gain in the two legal zones must be < 1
EE415 VLSI Design
The Regenerative Property
...
v1
v0
v2
v3
v5
v4
v6
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
finv(v)
v0, v2, ...
(b) Regenerative gate
EE415 VLSI Design
f(v)
v0, v2, ...
(c) Non-regenerative gate
Directivity
•A gate must be unidirectional:
•input not affected by output changes
•causes noise in input otherwise
•Real gate:
•full directivity never achievable
•capacitive coupling causes feedback
EE415 VLSI Design
Fan-in and Fan-out
•Fan-out:
•Number of load gates, N, that are connected to the output of
the driving gate
•tends to lower the logic levels
•deteriorates dynamic performance
•gate must have low output resistance to drive load
•library cells have maximum fan-out specification
•Fan-in:
•Number of inputs, M, to the gate
•large fan-in gates are more complex
•results in inferior static and dynamic performance
EE415 VLSI Design
Fan-in and Fan-out
(a) Fan-out N
M
N
EE415 VLSI Design
(b) Fan-in M
The Ideal Gate
Vout
Ri = 
Ro = 0
g=-
Vin
Static CMOS comes close to ideal
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VTC of Real Inverter
5.0
Vout (V)
4.0
NML
3.0
2.0
VM
NMH
1.0
0.0
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1.0
2.0
3.0
Vin (V)
4.0
5.0