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ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey et al., and Gaudet’s lecture notes] 1 OUTLINE Review of Basic Circuit Theory 2 Basic Circuit Elements Resistor (Unit: Ohm) Capacitor (Unit: Farad) Heat Dissipater Charge Storage Inductor (Unit: Henry) High Frequency Blocker 3 Resistance and Ohmic Law +V Resistance of Material I R R Ohmic Law I L A V R Resistors in Series RT R1 R2 R3 Resistors in Parallel 1 1 1 1 RT R1 R2 R3 4 Capacitance +V I C Capacitance of Material C A L Current Behavior I C dV dt Capacitors in Series 1 1 1 1 CT C1 C 2 C3 Capacitors in Parallel CT C1 C 2 C3 5 Inductance +V I Current Behavior V L L dI dt assuming no mutual interaction, Inductors in Series LT L1 L2 L3 Inductors in Parallel 1 1 1 1 LT L1 L2 L3 6 Kirchhoff’s Law Voltage For a closed circuit, the total voltage drops at each elements should add up to the voltage applied to the circuit; Current For any node in a circuit, the total currents entering the node should add up to those leaving the node. 7 OUTLINE PN Junction 8 Silicon IVA element in periodic table Four outer shell electrons Four bonds formed in Si crystal (tetragonal structure) 3D tetragonal structure 2D planar schematic 9 Doping The intrinsic charge carrier concentrations is very low in silicon (semiconductor), leading to high resistivity, which could not be used in circuit. To increase charge carrier concentrations, doping with impurities is necessary. For semiconductor, there’re two ways to dope if doped with impurity element P (phosphorus), with 5 outer shell electrons, the crystal will have excessive electrons, since only 4 electrons of each atom are used to form bonds. 1 phosphorus atom -> 1 free electron n-type If doped with Al (aluminum, 3 outer shell electrons) -> spare sites for electrons, called holes 1 aluminum atom -> 1 free hole p-type 10 PN Junction PN junctions consist of two semiconductor regions of opposite type. Such junctions show a pronounced rectifying behavior. They are also called abrupt junction. The PN junctions are versatile elements. They can be used in the following area: Rectifier, isolation structure and voltage-dependent capacitor. Solar cells, photodiodes, light emitting diodes and even laser diodes. Essential part of Metal-Oxide-Silicon Field-EffectsTransistors (MOSFETs) and Bipolar Junction Transistors (BJTs). 11 PN Junction electron hole still charge p-Si n-Si Before contact, holes and electrons are evenly distributed in p-Si and n-Si respectively. 12 PN Junction diffusion p n after some recombination 13 PN Junction diffusion p n Depleted Region or Space Charge Region after fully recombination 14 Built-in Potential in Depletion Region hole diffusion electron diffusion p (a) Current flow. n hole drift electron drift Charge Density + x Distance - Electrical Field (b) Charge density. x (c) Electric field. V Potential -W 1 W2 x (d) Electrostatic potential. 15 Built-in Potential NAND 0 T ln ni2 T kT 26 mV at 300K q 0 – the built-in potential T – the thermal voltage NA – the acceptor concentrations in p-materials ND – the donor concentrations in n-materials ni – the intrinsic carrier concentration in a pure sample of the semiconductor. (≈1.5x1010 cm-3 at 300K for silicon) q – electron charge k – Boltzman constant 16 Built-in Potential Example 3.1 Built-in Voltage of pn-junction An abrupt junction has doping densities of NA=1015 atoms/cm3, and ND=1016 atom/cm3. Calculate the built-in potential at 300K. 10151016 0 26 ln mV 638mV 20 2.25 10 17 OUTLINE The Diodes 18 The Diode B A Al SiO2 p n Cross-section of pn-junction in an IC process A p Al A n B One-dimensional representation B diode symbol Mostly occurring as parasitic element in Digital ICs 19 Diode Current – the ideal diode equation + ID = IS(eV D/T – 1) VD ID + + VD – (a) Ideal diode model – VDon – (b) First-order diode model IS represents a constant value called the saturation current of the diode. IS is proportional to the area of the diode, and a function of the doping levels and widths of the neutral regions 20 Diode Current – Example 3.2 Assume VS=3V, RS=10kΩ, and IS=0.5x10-16. RS VS-RSID=VD ID=0.224mA, VD=0.757V ID=0.23mA, VD=0.7V ID VS VD 21 Secondary Effects ID (A) 0.1 0 –0.1 –25.0 –15.0 –5.0 0 5.0 VD (V) Avalanche Breakdown 22 OUTLINE The MOS Transistor 23 What is a Transistor? A Switch! An MOS Transistor VGS V T |VGS| Ron S D 24 The MOS Transistor Layout Polysilicon Aluminum 25 MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D G S NMOS Depletion D G S B S NMOS with Bulk Contact PMOS Enhancement 26 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration ND electrons are the majority carriers Polysilicon W Gate Source n+ L p substrate Gate oxide Drain n+ Field-Oxide (SiO2) p+ stopper Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration NA - holes are the majority carriers 27 Switch Model of NMOS Transistor | VGS | Source (of carriers) Open (off) (Gate = ‘0’) Gate Drain (of carriers) Closed (on) (Gate = ‘1’) Ron | VGS | < | VT | | VGS | > | VT | 28 Switch Model of PMOS Transistor | VGS | Source (of carriers) Open (off) (Gate = ‘1’) Gate Drain (of carriers) Closed (on) (Gate = ‘0’) Ron | VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| | 29 Threshold Voltage Concept VGS G + D S - n+ n channel n+ p substrate depletion region B The value of VGS where strong inversion occurs is called the threshold voltage, VT 30 The Threshold Voltage VT = VT0 + (|-2F + VSB| - |-2F|) where VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process VSB is the source-bulk voltage F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon) is the body-effect coefficient 31 The Body Effect 0.9 0.85 0.8 VSB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) 0.75 0.7 0.65 0.6 0.55 A negative bias causes VT to increase from 0.45V to 0.85V 0.5 0.45 0.4 -2.5 -2 -1.5 VSB (V) -1 -0.5 0 32 Transistor in Linear Mode Assuming VGS > VT and VDS VGS – VT VGS VDS G S D n+ ID n+ - V(x) + x B The current is a linear function of both VGS and VDS 33 Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron) When VDS VGS – VT ID = k’n W/L [(VGS – VT)VDS – VDS2/2] where k’n = nCox = nox/tox = is the process transconductance parameter (n is the carrier mobility (m2/Vsec)) kn = k’n W/L is the gain factor of the device For small VDS, there is a linear dependence between VDS and ID, hence the name resistive or linear region 34 Transistor in Saturation Mode Assuming VGS > VT and VDS > VGS - VT VGS VDS G S D n+ ID n+ - V -V + GS T Pinch-off B The current remains constant (saturates). 35 Voltage-Current Relation: Saturation Mode For long channel devices When VDS VGS – VT ID’ = k’n/2 W/L [(VGS – VT) 2] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS – VT However, the effective length of the conductive channel is modulated by the applied VDS, so ID = ID’ (1 + VDS) where is the channel-length modulation (varies with the inverse of the channel length) 36 Effects on Current For of a fixed VDS and VGS (> VT), IDS is a function the distance between the source and drain – L the channel width – W the threshold voltage – VT the thickness of the SiO2 – tox the dielectric of the gate insulator (SiO2) – ox the carrier mobility - for NMOS: n = 500 cm2/V-sec - for PMOS: p = 180 cm2/V-sec ID = k’n W/L [(VGS – VT)VDS – VDS2/2] 37 I-V Plot (NMOS) 6 X 10-4 VDS = VGS - VT 5 VGS = 2.5V 4 VGS = 2.0V 3 Linear Saturation 2 VGS = 1.5V 1 VGS = 1.0V 0 cut-off 0 0.5 1 1.5 2 2.5 VDS (V) NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V 38 I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 VDS (V) -1 0 0 VGS = -1.0V -0.2 VGS = -1.5V -0.4 -0.6 VGS = -2.0V -0.8 VGS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V 39 The MOS Current-Source Model ID = 0 for VGS – VT 0 G ID S D ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+VDS) for VGS – VT 0 with Vmin = min(VGS – VT, VDS, VDSAT) B Determined by the voltages at the four terminals and a set of five device parameters NMOS PMOS VT0(V) 0.43 -0.4 (V0.5) 0.4 -0.4 VDSAT(V) 0.63 -1 k’(A/V2) 115 x 10-6 -30 x 10-6 (V-1) 0.06 -0.1 40 Summary of MOSFET Operating Regions Strong Inversion VGS > VT Linear (Resistive) VDS < VDSAT Saturated (Constant Current) VDS VDSAT Weak Inversion (Sub-Threshold) VGS VT Exponential in VGS with linear VDS dependence 41