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EE4271
VLSI Design
Dr. Shiyan Hu
Office: EERC 518
[email protected]
Device
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
© Digital Integrated Circuits2nd
Devices
Goal of this chapter
Present intuitive understanding of device
operation
 Introduction of basic device equations

© Digital Integrated Circuits2nd
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MOS Transistor Types and Symbols
D
G
S
NMOS
D
G
S
PMOS
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Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
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Vout2
M3
4
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Circuit on the Chip
A transistor
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The MOS (Metal-Oxide-Semiconductor)
Transistor
Polysilicon
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Aluminum
Devices
Simple View of A Transistor
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
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D
Devices
Silicon Basics
Transistors are built on a silicon substrate
 Silicon forms crystal lattice with bonds to
four neighbors

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Doped Silicon



Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
 extra electrons (doped Borons) – n-type
 missing electrons (doped Arsenic/Phosphorus)
more holes) – p-type
n-type
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p-type
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NMOS Transistor
Diffusion
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NMOS - II
Refer to gate, source, drain and bulk
voltages as Vg,Vs,Vd,Vb, respectively.
 Vab=Va-Vb
 Device is symmetric. Drain and source are
distinguished electrically, i.e., Vd>Vs.
 P regions have acceptor (Boron)
impurities, i.e., many holes.
 N regions have donor
(Arsenic/Phosphorus) impurities, i.e.,
many electrons.
 N+ and P+ are heavily doped N and P
regions, respectively.

© Digital Integrated Circuits2nd
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NMOS - III
Gate oxide are insulators, usually, silicon
dioxide.
 Gate voltage modulates current between
drain and source, how?

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Enhancement NMOS
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Enhancement NMOS - II
Does not conduct when Vgs=0, except
that there is leakage current.
 When Vgs is sufficiently large, electrons
are induced in the channel, i.e., the device
conducts. This Vgs is called threshold
voltage.

© Digital Integrated Circuits2nd
Devices
Enhancement NMOS III
Positively Charged
Negatively Charged
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Enhancement NMOS - IV
When Vgs is large enough, the upper part
of the channel changes to N-type due to
enhancement of electrons in it. This is
referred to as inversion, and the channel
is called n-channel.
 The voltage at which inversion occurs is
called the Threshold Voltage (Vt).
 A p-depletion layer have more holes than
p-substrate since its electrons have been
pushed into the inversion layer.
 Does not conduct when Vgs<Vt (Cut-off).

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Enhancement NMOS V
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Enhancement NMOS - VI
When Vgs>Vt, the inversion layer (n
channel) becomes thicker.
 The horizontal electrical field due to Vds
moves electrons from the source to the
drain through the channel.
 If Vds=0, the channel is formed but not
conduct.

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Devices
Case when Vds=0
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Linear Region
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Linear Region - II
When Vgs>Vt and Vgd>Vt, the inversion
layer increases in thickness and
conduction increases.
 The reason is that there are non-zero
inversion layer at both source and drain
(our previous analysis works for both Vgs
and Vgd).This is called linear region.
 Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e.,
Vds<=Vgs-Vt
 Vds>0
 Ids depends on Vg, Vgs, Vds and Vt.

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Devices
Saturation Region
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Saturation Region - II
When Vgs>Vt and Vgd<Vt, we have nonzero inversion layer at source but zero
inversion layer at drain.
 Inversion layer is said to be pinched off.
This is called the saturation region.
 Vgd<Vt means that Vgs-Vds<Vt, i.e.,
Vds>Vgs-Vt.
 Electrons leaves the channel and moves
to drain terminal through depletion region.

© Digital Integrated Circuits2nd
Devices
Saturation Region - III
In saturation region, the voltage difference
over the channel remains at Vgs-Vt. This
is because if Vds=Vgs-Vt, the inversion
layer is barely pinched off at the drain
(since then Vgd=Vt). If Vds>Vgs-Vt, the
channel is pinched off somewhere
between the drain and source ends. Thus,
the voltage applied across the channel is
Vgs-Vt.
 As a result, Ids depends on Vgs in this
region, so we cannot keep raising Vds to
get better conduction.

© Digital Integrated Circuits2nd
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Summary
Three regions of conduction
 Cut-off: 0<Vgs<Vt
 Linear: 0<Vds<Vgs-Vt
 Saturation: 0<Vgs-Vt<Vds
 Vt depends on gate and insulator
materials, thickness of insulators and so
forth – process dependant factors, and
Vsb and temperature – operational factors.

© Digital Integrated Circuits2nd
Devices
Analysis (for linear region)
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
© Digital Integrated Circuits2nd
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Analysis - II

Denote by V(x) the voltage at a point x
along the channel. The gate-to-point
voltage is Vgs-V(x). Since it needs to be >
Vt for every point along the channel, the
charge per unit cross section area at x is

Cox is the capacitance per unit, which is
where is a constant called the
permittivity of the gate oxide and tox is the
thickness of gate oxide.
© Digital Integrated Circuits2nd
Devices
Analysis - III
I
1
Q
1
W
Gate width W, so the total charge is QW.
 I=QW/t=QWv, v being velocity of carrier.
 Given surface mobility  of electrons,
which depends on process, an empirical
formula for v is
 We have
 Integrate x from 0 to L, we have


For saturation region, replace Vds by VgsVt, we have
. It does
not depend on Vds.
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Effective Channel Length/Width
is due to lateral diffusion of the source and
drain junctions under the gate
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Summary - II

Three regions of conduction
 Cut-off: 0<Vgs<Vt, I=0
 Linear: 0<Vds<Vgs-Vt,

Saturation: 0<Vgs-Vt<Vds
© Digital Integrated Circuits2nd
Devices
PMOS
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PMOS - II
Dual of NMOS
 Three regions of conduction
 Cut-off: 0>Vgs>Vt
 Linear: 0>Vds>Vgs-Vt
 Saturation: 0>Vgs-Vt>Vds
 Current computation is the same as NMOS
except that the polarities of all voltages
and currents are reversed.
 Mobility in PMOS is usually half of the
mobility in NMOS due to process
technology.

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I-V characteristics (different Vt)
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I-V Characteristics II
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Short Channel Effects
The discussion is true for long channel.
 The depletion layer/electron move under
the gate is assumed to be caused entirely
by vertical field, i.e.,
 Near source and drain, there is also
depleted region due to horizontal
electrical field (Vd,Vs). Thus, the region
below gate is already partially depleted.
 Device actually conducts with smaller Vt.
 If the channel is very short, effect is
significant, which make the device hard to
control.
 In practice, L>= Lmin.

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Short Channel Effect - II
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Sub-threshold conduction (Leakage)
Vgs<Vt, cut-off and I=0. Not true.
 In practice, for Vgs<Vt,

I is exponentially dependent on Vgs. Id0
and n are experimentally determined, k is
Boltzmann’s constant and T is
temperature.
 Source of standby power consumption in
portable devices.
 Some extremely low-power circuits use
sub-threshold conduction, e.g., digital
watch.

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Devices
Transistor Equivalent Resistance

In linear region, R=V/I, so

In saturation region, the voltage applied
across the channel is Vgs-Vt. Thus,

Roughly speaking, channel resistance
inversely depends on W since
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Transistor Resistance - II
Larger gate width (larger gate area) ->
smaller resistance -> device runs faster
 This means that power/area increases with
delay decreases. A lot of power-delay
tradeoff like this.

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Devices
Transistor Capacitance
G
CGS
CGD
D
S
CGB
CSB
CDB
B
Gate Capacitance = Channel Capacitance + Overlap
Capacitance
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Overlap Capacitance
Polysilicon gate
Source
Drain
xd
n+
xd
W
n+
Ld
Top view
Gate oxide
tox
n+
L
n+
Cross section
Overlap capacitance=2Cox Xd W
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Channel Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
D
S
Resistive
Saturation
Larger gate width -> Larger capacitance
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Measuring the Gate Cap
3 102 16
10
I
i=CdV/dt, so C=idt/dV
9
Gate Capacitance (F)
V GS
8
7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0 0.5 1
V GS (V)
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1.5 2
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In Standard Cell Library
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A gate type has multiple gate sizes (widths)
Larger gate width means larger gate capacitance and
smaller driving resistance.
Thus, for a gate type, we have a variety of transistors
with different capacitance and resistance tradeoff.
Larger width means larger capacitance and thus
larger power due to charging and uncharging the
capacitance.
Usually, larger width transistor has smaller delay.
© Digital Integrated Circuits2nd
Devices
Technology Scaling


Devices scale to smaller dimensions with advancing technology.
A scaling factor S describes the ratio of dimension between the
old technology and the new technology. In practice, S=1.2-1.5.
© Digital Integrated Circuits2nd
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Technology Scaling - II
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



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In practice, it is not feasible to scale voltage since different ICs in
the system may have different Vdd. This may require extremely
complex additional circuits. We can only allow very few different
levels of Vdd.
In technology scaling, we often have fixed voltage scaling model.
W,L,tox scales down by 1/S
Vdd, Vt unchanged
Area scales down by 1/S2
Cox scales up by S due to tox
Gate capacitance = CoxWL scales down by 1/S
scales up by S
Linear and saturation region current scales up by S
Current density scales up by S3
P=Vdd*I, power density scales up by S3
Power consumption is a major design issue
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Summary

NMOS
 Cut-Off, Linear and Saturation Regions
 How to compute I
 sub-threshold conduction
PMOS is the dual device of NMOS
 I-V characteristics of MOS transistors

 Resistance
 Capacitance
© Digital Integrated Circuits2nd
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