Download Saturation Region - Electrical and Computer Engineering

EE4271
VLSI Design
Dr. Shiyan Hu
Office: EERC 731
[email protected]
Device
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
© Digital Integrated Circuits2nd
Devices
Goal of this chapter
Present intuitive understanding of device
operation
 Introduction of basic device equations

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Devices
MOS Transistor Types and Symbols
D
G
S
NMOS
D
G
S
PMOS
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Devices
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
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Vout2
M3
4
Devices
Circuit on the Chip
A transistor
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Devices
The MOS (Metal-Oxide-Semiconductor)
Transistor
Polysilicon
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Aluminum
Devices
Simple View of A Transistor
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
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D
Devices
Silicon Basics
Transistors are built on a silicon substrate
 Silicon forms crystal lattice with bonds to
four neighbors

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Devices
Doped Silicon



Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
 extra electrons (doped Borons) – n-type
 missing electrons (doped Arsenic/Phosphorus)
more holes) – p-type
n-type
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p-type
Devices
NMOS Transistor
Diffusion
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Devices
NMOS - II
Refer to gate, source, drain and bulk
voltages as Vg,Vs,Vd,Vb, respectively.
 Vab=Va-Vb
 Device is symmetric. Drain and source are
distinguished electrically, i.e., Vd>Vs.
 P regions have acceptor (Boron)
impurities, i.e., many holes.
 N regions have donor
(Arsenic/Phosphorus) impurities, i.e.,
many electrons.
 N+ and P+ are heavily doped N and P
regions, respectively.

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Devices
NMOS - III
Gate oxide are insulators, usually, silicon
dioxide.
 Gate voltage modulates current between
drain and source, how?

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Devices
Enhancement NMOS
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Devices
Enhancement NMOS - II
Does not conduct when Vgs=0, except
that there is leakage current.
 When Vgs is sufficiently large, electrons
are induced in the channel, i.e., the device
conducts. This Vgs is called threshold
voltage.

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Devices
Enhancement NMOS III
Positively Changed
Negatively Changed
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Enhancement NMOS - IV
When Vgs is large enough, the upper part
of the channel changes to N-type due to
enhancement of electrons in it. This is
refereed to as inversion, and the channel
is called n-channel.
 The voltage at which inversion occurs is
called the Threshold Voltage (Vt).
 A p-depletion layer have more holes than
p-substrate since its electrons have been
pushed into the inversion layer.
 Does not conduct when Vgs<Vt (Cut-off).

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Devices
Enhancement NMOS V
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Devices
Enhancement NMOS - VI
When Vgs>Vt, the inversion layer (n
channel) becomes thicker.
 The horizontal electrical field due to Vds
moves electrons from the source to the
drain through the channel.
 If Vds=0, the channel is formed but not
conduct.

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Devices
Case when Vds=0
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Linear Region
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Devices
Linear Region - II
When Vgs>Vt and Vgd>Vt, the inversion
layer increases in thickness and
conduction increases.
 The reason is that there are non-zero
inversion layer at both source and drain
(our previous analysis works for both Vgs
and Vgd).This is called linear region.
 Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e.,
Vds<=Vgs-Vt
 Ids depends on Vg, Vgs and Vds.

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Devices
Saturation Region
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Devices
Saturation Region - II
When Vgs>Vt and Vgd<Vt, we have nonzero inversion layer at source but zero
inversion layer at drain.
 Inversion layer is said to be pinched off.
This is called the saturation region.
 Vgd<Vt means that Vgs-Vds<Vt, i.e.,
Vds>Vgs-Vt.
 Electrons leaves the channel and moves
to drain terminal through depletion region.

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Devices
Saturation Region - III
In saturation region, the voltage difference
over the channel remains at Vgs-Vt. This
is because if Vds=Vgs-Vt, the inversion
layer is barely pinched off at the drain. If
Vds>Vgs-Vt, the channel is pinched off
somewhere between the drain and source
ends. Thus, the voltage applied across the
channel is Vgs-Vt.
 As a result, Ids depends on Vgs alone in
this region, so we cannot keep raising Vds
to get better conduction.

© Digital Integrated Circuits2nd
Devices
Summary
Three regions of conduction
 Cut-off: 0<Vgs<Vt
 Linear: 0<Vds<Vgs-Vt
 Saturation: 0<Vgs-Vt<Vds
 Vt depends on gate and insulator
materials, thickness of insulators and so
forth – process dependant factors, and
Vsb and temperature – operational factors.

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Devices
Analysis (for linear region)
VGS
VDS
S
G
n+
–
V(x)
ID
D
n+
+
L
x
p-substrate
B
MOS transistor and its bias conditions
© Digital Integrated Circuits2nd
Devices
Analysis - II

Denote by V(x) the voltage at a point x
along the channel. The gate-to-channel
voltage is Vgs-V(x). Since it needs to be >
Vt for every point along the channel, the
charge per unit area at x is

Cox is the capacitance per unit, which is
where is a constant called the
permittivity of the gate oxide and tox is the
thickness of gate oxide.
© Digital Integrated Circuits2nd
Devices
Analysis - III
I
1
Q
1
W
Gate width W, so the total charge is QW.
 I=QW/t=QWv, v being velocity of carrier.
 Given surface mobility u of electrons,
which depends on process, an empirical
formula for v is
 We have
 Integrate x from 0 to L, we have


For saturation region, replace Vds by VgsVt, we have
. It does
not depend on Vds.
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Devices
Effective Channel Length/Width
is due to lateral diffusion of the source and
drain junctions under the gate
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Devices
Channel Length Modulation

In saturation region, current is actually
weakly depends on Vds. This is because
that increasing Vds makes the pinch-off
earlier (closer to source). Since electrons
flow through depletion layer to move to
drain in saturation region, this means a
long trip. The current value is actually

is empirically determined. Usually it is
<0.02/Vds.
© Digital Integrated Circuits2nd
Devices
Summary - II

Three regions of conduction
 Cut-off: 0<Vgs<Vt, I=0
 Linear: 0<Vds<Vgs-Vt,

Saturation: 0<Vgs-Vt<Vds
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Devices
PMOS
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Devices
PMOS - II
Dual of NMOS
 Three regions of conduction
 Cut-off: 0>Vgs>Vt
 Linear: 0>Vds>Vgs-Vt
 Saturation: 0>Vgs-Vt>Vds
 Current computation is the same as NMOS
except that the polarities of all voltages
and currents are reversed.
 Mobility of holes u in PMOS is usually half
of the mobility of electronics in NMOS due
to process technology.

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Devices
I-V characteristics (different Vt)
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Devices
I-V Characteristics II
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Devices
Threshold Voltage and Body Effect







Since gate and substrate form the plates of a
capacitor, a strong enough inversion layer needs
sufficient amount of voltage difference, i.e., Vgs=Vt.
The amount of positive charge = the amount of
negative charge on both plates.
If we decrease the bulk/substrate voltage Vb, more
charge is needed on the lower plate to counteract it.
Vgs >Vt in order to form the same inversion layer as
before
Make the circuit run slower.
It is called Body Effect. Try to avoid it.
where is called the body-effect
coefficient and Vt0 is the threshold voltage when
Vsb=0.
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Devices
Threshold Voltage and Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
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-0.5
0
(V)
Devices
Short Channel Effects
is true for long channel.
 The depletion layer/electron move under
the gate is assumed to be caused entirely
by vertical field, i.e.,
 Near source and drain, there is also
depleted region due to horizontal
electrical field (Vd,Vs). So the region
below gate is already partially depleted.
 Device actually conducts with smaller Vt.
 OK for far-apart drain and source. If the
channel is very short, effect is significant,
which make the device hard to control.
 In practice, L>= Lmin.

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Devices
Short Channel Effect - II
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Sub-threshold conduction (Leakage)
-2
10
Linear
Saturation
Region
-4
10
-6
Quadratic (in Vds)
ID (A)
10
Linear/Triode/R
esistive region
-8
10
-10
10
-12
10
Exponential
Sub-threshold
region
VT
0
0.5
1
1.5
2
2.5
VGS (V)
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Devices
Sub-threshold conduction (Leakage) - II
Vgs<Vt, cut-off and I=0. Not true.
 In practice, for Vgs<Vt,

I is exponentially dependent on Vgs. Id0
and n are experimentally determined, k is
Boltzmann’s constant and T is
temperature.
 Source of standby power consumption in
portable devices.
 Some extremely low-power circuits use
sub-threshold conduction, e.g., digital
watch.

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Devices
Transistor Equivalent Resistance

In linear region, R=V/I, so

In saturation region, the voltage applied
across the channel is Vgs-Vt. Thus,

Roughly speaking, channel resistance
inversely depends on W since
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Devices
Transistor Resistance - II
Larger gate width (larger gate area) ->
smaller resistance -> device runs faster
 This means that power/area increases with
delay decreases. A lot of power-delay
tradeoff like this.

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Devices
Transistor Resistance - III
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Devices
Transistor Capacitance
G
CGS
CGD
D
S
CGB
CSB
CDB
B
Gate Capacitance = Channel Capacitance + Overlap
Capacitance
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Devices
Overlap Capacitance
Polysilicon gate
Source
Drain
xd
n+
xd
W
n+
Ld
Top view
Gate oxide
tox
n+
L
n+
Cross section
Overlap capacitance=2Cox Xd W
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Devices
Channel Capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
D
S
Resistive
Saturation
Larger gate width -> Larger capacitance
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Devices
Gate Capacitance
CG C
WLC ox
WLC ox
CGC B
C G CS = CG CD
2
VG S
Capacitance as a function of VGS
(with VDS = 0)
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WLC ox
CG C
2WLC ox
CG CS
WLC ox
2
3
CGCD
0
VDS /(VG S-VT)
1
Capacitance as a function of the
degree of saturation
Devices
Measuring the Gate Cap
3 102 16
10
I
I=CdV/dt, so C=idt/dV
9
Gate Capacitance (F)
V GS
8
7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0 0.5 1
V GS (V)
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1.5 2
Devices
In Standard Cell Library





A gate type has multiple gate sizes (widths)
Larger gate width means larger gate capacitance and
smaller driving resistance.
Thus, for a gate type, we have a variety of transistors
with different capacitance and resistance tradeoff.
Larger width means larger capacitance and thus
larger power due to charging and uncharging the
capacitance.
Usually, larger width transistor has smaller delay.
© Digital Integrated Circuits2nd
Devices
Technology Scaling


Devices scale to smaller dimensions with advancing technology.
A scaling factor S describes the ratio of dimension between the
old technology and the new technology. In practice, S=1.2-1.5.
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Devices
Technology Scaling - II












In practice, it is not feasible to scale voltage since different ICs in
the system may have different Vdd. This may require extremely
complex additional circuits. We can only allow very few different
levels of Vdd.
In technology scaling, we often have fixed voltage scaling model.
W,L,tox scales down by 1/S
Vdd, Vt unchanged
Area scales down by 1/S2
Cox scales up by S due to tox
Gate capacitance = CoxWL scales down by 1/S
scales up by S
Linear and saturation region current scales up by S
Current density scales up by S3
P=Vdd*I, power density scales up by S3
Power consumption is a major design issue
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Summary

NMOS
 Cut-Off, Linear and Saturation Regions
 How to compute I
 Channel length modulation, short channel effect, subthreshold conduction
PMOS is the dual device of NMOS
 I-V characteristics of MOS transistors

 Resistance
 Capacitance
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Devices