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EE2174
Digital Logic and Lab
Dr. Shiyan Hu
Office: EERC 518
[email protected]
Introduction to
CMOS
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
© Digital Integrated Circuits2nd
Devices
Goal of this chapter
Present intuitive understanding on CMOS
 Device
 Interconnect
 Inverter
 Combinational Gate

© Digital Integrated Circuits2nd
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Device
© Digital Integrated Circuits2nd
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MOS Transistor Types and Symbols
D
G
S
NMOS
D
G
S
PMOS
© Digital Integrated Circuits2nd
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Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
© Digital Integrated Circuits2nd
Vout2
M3
5
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Circuit on the Chip
A transistor
© Digital Integrated Circuits2nd
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The MOS (Metal-Oxide-Semiconductor)
Transistor
Polysilicon
© Digital Integrated Circuits2nd
Aluminum
Devices
Simple View of A Transistor
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
© Digital Integrated Circuits2nd
D
Devices
Silicon Basics
Transistors are built on a silicon substrate
 Silicon forms crystal lattice with bonds to
four neighbors

© Digital Integrated Circuits2nd
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Doped Silicon



Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
 extra electrons (doped Borons) – n-type
 missing electrons (doped Arsenic/Phosphorus)
more holes) – p-type
n-type
© Digital Integrated Circuits2nd
p-type
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NMOS Transistor
Diffusion
© Digital Integrated Circuits2nd
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NMOS - II
Refer to gate, source, drain and bulk
voltages as Vg,Vs,Vd,Vb, respectively.
 Vab=Va-Vb
 Device is symmetric. Drain and source are
distinguished electrically, i.e., Vd>Vs.
 P regions have acceptor (Boron)
impurities, i.e., many holes.
 N regions have donor
(Arsenic/Phosphorus) impurities, i.e.,
many electrons.
 N+ and P+ are heavily doped N and P
regions, respectively.

© Digital Integrated Circuits2nd
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NMOS - III
Gate oxide are insulators, usually, silicon
dioxide.
 Gate voltage modulates current between
drain and source, how?

© Digital Integrated Circuits2nd
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Enhancement NMOS
© Digital Integrated Circuits2nd
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Enhancement NMOS - II
Does not conduct when Vgs=0, except
that there is leakage current.
 When Vgs is sufficiently large, electrons
are induced in the channel, i.e., the device
conducts. This Vgs is called threshold
voltage.

© Digital Integrated Circuits2nd
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Enhancement NMOS III
Positively Charged
Negatively Charged
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Enhancement NMOS - IV
When Vgs is large enough, the upper part
of the channel changes to N-type due to
enhancement of electrons in it. This is
referred to as inversion, and the channel
is called n-channel.
 The voltage at which inversion occurs is
called the Threshold Voltage (Vt).
 A p-depletion layer have more holes than
p-substrate since its electrons have been
pushed into the inversion layer.
 Does not conduct when Vgs<Vt (Cut-off).

© Digital Integrated Circuits2nd
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Enhancement NMOS V
© Digital Integrated Circuits2nd
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Enhancement NMOS - VI
When Vgs>Vt, the inversion layer (n
channel) becomes thicker.
 The horizontal electrical field due to Vds
moves electrons from the source to the
drain through the channel.
 If Vds=0, the channel is formed but not
conduct.

© Digital Integrated Circuits2nd
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Case when Vds=0
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Linear Region
© Digital Integrated Circuits2nd
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Linear Region - II
When Vgs>Vt and Vgd>Vt, the inversion
layer increases in thickness and
conduction increases.
 The reason is that there are non-zero
inversion layer at both source and drain
(our previous analysis works for both Vgs
and Vgd).This is called linear region.
 Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e.,
Vds<=Vgs-Vt
 Vds>0
 Ids depends on Vg, Vgs, Vds and Vt.

© Digital Integrated Circuits2nd
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Saturation Region
© Digital Integrated Circuits2nd
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Saturation Region - II
When Vgs>Vt and Vgd<Vt, we have nonzero inversion layer at source but zero
inversion layer at drain.
 Inversion layer is said to be pinched off.
This is called the saturation region.
 Vgd<Vt means that Vgs-Vds<Vt, i.e.,
Vds>Vgs-Vt.
 Electrons leaves the channel and moves
to drain terminal through depletion region.

© Digital Integrated Circuits2nd
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Summary
Three regions of conduction
 Cut-off: 0<Vgs<Vt
 Linear: 0<Vds<Vgs-Vt
 Saturation: 0<Vgs-Vt<Vds
 Vt depends on gate and insulator
materials, thickness of insulators and so
forth – process dependant factors, and
Vsb and temperature – operational factors.

© Digital Integrated Circuits2nd
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PMOS
© Digital Integrated Circuits2nd
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PMOS - II
Dual of NMOS
 Three regions of conduction
 Cut-off: 0>Vgs>Vt
 Linear: 0>Vds>Vgs-Vt
 Saturation: 0>Vgs-Vt>Vds
 Current computation is the same as NMOS
except that the polarities of all voltages
and currents are reversed.
 Mobility in PMOS is usually half of the
mobility in NMOS due to process
technology.

© Digital Integrated Circuits2nd
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I-V characteristics (different Vt)
© Digital Integrated Circuits2nd
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I-V Characteristics II
© Digital Integrated Circuits2nd
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Wire
© Digital Integrated Circuits2nd
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Modern Interconnect
transmitters
© Digital Integrated Circuits2nd
receivers
31
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Modern Interconnect - II
© Digital Integrated Circuits2nd
32
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Interconnect Delay Dominates
Delay (psec)
300
250
Interconnect delay
200
150
100
Transistor/Gate delay
50
0
0.8
0.5
0.35 0.25
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.
© Digital Integrated Circuits2nd
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Devices
Capacitor
A
capacitor is a device that can store an
electric charge by applying a voltage
 The capacitance is measured by the
ratio of the charge stored to the applied
voltage
 Capacitance is measured in Farads
© Digital Integrated Circuits2nd
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3D Parasitic Capacitance

Given a set of conductors, compute the
capacitance between all pairs of conductors.
-
+
+
+
-
© Digital Integrated Circuits2nd
1V
+
+
-
- -
C=Q/V
-
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Simplified Model
Area capacitance
(Parallel plate): area
overlap between
adjacent layers/substrate
 Fringing/coupling
capacitance:

 between side-walls on the
same layer
 between side-wall and
adjacent layers/substrate
© Digital Integrated Circuits2nd
m3
m2
m2
m2
m1
Devices
The Parallel Plate Model (Area Capacitance)
c
 di
t di
Current flow
WL
L
Electrical-field lines
W
H
tdi
Dielectric
Substrate
Capacitance is proportional to the overlap between the
conductors and inversely proportional to their separation
37
Devices
© Digital Integrated Circuits2nd
Wire Capacitance
 More
difficult due to multiple layers,
different dielectric
=8.0
multiple
dielectric
m3
=4.0
m2 =3.9 m2 m2
=4.1
m1
© Digital Integrated Circuits2nd
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Simple Estimation Methods
C
= Ca*(overlap area)
+Cc*(length of parallel run)
+Cf*(perimeter)
 Coefficients Ca, Cc and Cf are given by
the fab
 Cadence Dracula
 Fast but inaccurate
© Digital Integrated Circuits2nd
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Accurate Methods In Industry
 Finite
difference/finite element method
 Most accurate, slowest
 Raphael
 Boundary
element method
 FastCap, Hicap
© Digital Integrated Circuits2nd
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Wire Resistance

Basic formula R=(/h)(l/w)
l
h
w
  : resistivity
 h: thickness, fixed for a given technology and layer
number
 l: conductor length
 w: conductor width
© Digital Integrated Circuits2nd
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Analysis of Simple RC Circuit
i(t)
R
R  i (t )  v(t )  vT (t )
vT(t) ±
C
v(t)
d (Cv(t ))
dv(t )
i (t ) 
C
dt
dt
dv(t )
 RC
 v(t )  vT (t )
dt
state
variable
Input
waveform
© Digital Integrated Circuits2nd
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Analysis of Simple RC Circuit
Step-input response:
v0
v0u(t)
v0(1-e-t/RC)u(t)
dv(t )
 v(t )  v0u (t )
dt
t
v(t )  Ke RC  v0u(t )
RC
match initial state:
v(0)  0
 K  v0u (t )  0  K  v0  0
output response for step-input:
v(t )  v0 (1  e
© Digital Integrated Circuits2nd
t
RC
)u(t )
Devices
0.69RC

v(t) = v0(1 - e-t/RC) -- waveform
under step input v0u(t)

v(t)=0.5v0  t = 0.69RC
 i.e., delay = 0.69RC
(50% delay)
v(t)=0.1v0  t = 0.1RC
v(t)=0.9v0  t = 2.3RC
 i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)

Elmore Delay
TD = 0.69 RC
© Digital Integrated Circuits2nd
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Elmore Delay
Delay
© Digital Integrated Circuits2nd
1. 50%-50%
point delay
2. Delay=0.69RC
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Delay
© Digital Integrated Circuits2nd
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Elmore Delay - III
What is the
delay of a wire?
© Digital Integrated Circuits2nd
47
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Elmore Delay – IV
Assume: Wire modeled by N equal-length segments
For large values of N:
Precisely,
should be
0.69RC/2
© Digital Integrated Circuits2nd
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Elmore Delay - V
n2
n1
n1
n2
C/2
R
C/2
R=unit wire resistance*length
C=unit wire capacitance*length
© Digital Integrated Circuits2nd
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Devices
RC Tree Delay
4
4
2
2
7
7
2
24+4*2=32
1
1
Unit wire cap=1, unit wire res=1
3.5
2*(1+3.5+3.5+2+2)=24
RC Tree Delay=max{32,48.5}=48.5
© Digital Integrated Circuits2nd
3.5
Precisely,
0.69*48.5
50
2
24+7*3.5=48.5
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Inverter
© Digital Integrated Circuits2nd
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Circuit Symbols
© Digital Integrated Circuits2nd
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The CMOS Inverter
V DD
S
Vin=Vdd,Vout=0
Vin=0,Vout=Vdd
D
V in
V out
D
CL
S
© Digital Integrated Circuits2nd
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Its Layout View
© Digital Integrated Circuits2nd
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Pass-Transistors




Need a circuit element which acts as a switch
When the control signal CLK is high, Vout=Vin
When the control signal CLK is low, Vout is open circuited
We can use NMOS or PMOS to implement it. For PMOS device, the
polarity of CLK is reversed.
NMOS based
PMOS based
© Digital Integrated Circuits2nd
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NMOS Pass Transistors



Initially Vout=0. input=drain, output=source
When CLK=0, then Vgs=0. NMOS cut-off
When CLK=Vdd,
 If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd,
NMOS is in saturation region as a transient response and CL is
charged.
 When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off.
 However, if Vout drops below Vdd-Vt, NMOS will be turned on
again since Vgs>Vt.
 Thus, NMOS transmits Vdd value but drops it by Vt.
© Digital Integrated Circuits2nd
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NMOS Pass Transistors - II

If Vin=0 (and CLK=Vdd), source=input, drain=output
 If Vout=Vdd-Vt (note that it is the maximum
value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=VddVt=Vgs-Vt
 The NMOS is on the boundary of linear region and saturation
region
 CL is discharged
 As Vout approaches 0, the NMOS is linear region. Thus, Vout is
completely discharged.
 When Vout=0, Vds=0 and Ids=0, thus, the discharge is done.
 NMOS pass transistor transmits a 0 voltage without any
degradation
© Digital Integrated Circuits2nd
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PMOS Pass Transistors




Similar to NMOS pass transistor
Assume that initially Vout=0
When CLK=Vdd, PMOS cut-off
When CLK=0,
 If Vin=Vdd, PMOS transmits a Vdd value without degradation
 If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt|
© Digital Integrated Circuits2nd
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Transmission Gate





An NMOS transmits a 0 value without degradation while transmits a
Vdd value with degradation
A PMOS transmits a Vdd value without degradation while transmits a 0
value with degradation
Use both in parallel, then can transmit both 0 and Vdd well.
CLK=0, both transistors cut-off
CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when
Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS
cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0.
© Digital Integrated Circuits2nd
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Power Dissipation
© Digital Integrated Circuits2nd
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Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
© Digital Integrated Circuits2nd
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Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Power = CL * Vdd2 * f
Not a function of transistor sizes
Need to reduce CL, Vdd, and f to reduce power.
© Digital Integrated Circuits2nd
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Dynamic Power
Dynamic power is due to charging/discharging
load capacitor CL
In charging, CL is loaded with a charge CL Vdd
which requires the energy of QVdd= CL Vdd2,
and all the energy will be dissipated when
discharging is done. Total power = CL Vdd2
If this is performed with frequency f, clearly,
total power = CL Vdd2 f
© Digital Integrated Circuits2nd
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Dynamic Power- II





If the waveform is not periodic, denote by P the probability of switching
for the signal
The dynamic power is the most important power source
It is quadratically dependant on Vdd
It is proportional to the number of switching. We can slow down the
clock not on the timing critical path to save power.
It is not dependent of the transistor itself but the load of the transistor.
© Digital Integrated Circuits2nd
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Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
Sub-Threshold
in low-energy
circuitCurrent
design.Dominant Factor
© Digital Integrated Circuits2nd
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Subthreshold Leakage Component
© Digital Integrated Circuits2nd
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Principles for Power Reduction
 Prime
choice: Reduce voltage
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.5V)
 Reduce
switching activity
 Reduce physical capacitance
© Digital Integrated Circuits2nd
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Combinational Gate
© Digital Integrated Circuits2nd
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CMOS Combinational Circuits



Implementation of logic gates and other structures using
CMOS technology.
Basic element: transistor
2 types of transistors:
 n-channel (nMOS) and p-channel (pMOS)
 Type depends on the semiconductor materials used to implement
the transistor.
 We want to model transistor behavior at the logic level in order to
study the behavior of CMOS circuits  view pMOS and nMOS
transistors as swithes.
© Digital Integrated Circuits2nd
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Networks of Switches
Use switches to create networks that
represent CMOS logic circuits.
 To implement a function F, create a network
s.t. there is a path through the network
whenever F=1 and no path when F=0.
 Two basic structures

 Transistors in Series
 Transistors in Parallel
© Digital Integrated Circuits2nd
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Transistors in Series/Parallel
nMOS in Series
a
a
X
X:X
Y
Y:Y
b
X:X’
Y:Y’
Y
b
Path between
points a and b
exists if both
X and Y are 1
 X•Y
a
X
Y
b
© Digital Integrated Circuits2nd
a
X:X
b
b
pMOS in Series
a
a
X
nMOS in Parallel
Y:Y
Path between
points a and b
exists if either
X or Y are 1
 X+Y
b
pMOS in Parallel
Path between
points a and b
exists if both
X and Y are 0
 X’•Y’
a
X
Y
a
X:X
b
Y:Y
Path between
points a and b
exists if either
X or Y are 0
 X’+Y’
b
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Networks of Switches (cont.)
In general:

1.
2.
3.
4.
nMOS in series is used to implement AND logic
pMOS in series is used to implement NOR logic
nMOS in parallel is used to implement OR logic
pMOS in parallel is used to implement NAND logic
Observe that:



1 is the complement of 4, and vice-versa
2 is the complement of 3, and vice-versa
© Digital Integrated Circuits2nd
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Fully Complementary CMOS Networks
Basic Gates
© Digital Integrated Circuits2nd
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Fully Complementary CMOS
Complex Gates
Given a function F:
1.
First take the complement of F to form F’
2.
Implement F’ as an nMOS net and connect it to GRD
(pull-down net) and F.
3.
Find dual of F’, implement it as a pMOS net and
connect it to +V (pull-up net) and F.
4.
Connect switch inputs.
© Digital Integrated Circuits2nd
Devices
Fully Complementary CMOS Networks
Complex Gates - Example
F = (A+B)(A+C’)
F’ = A’B’+A’C=A’(B’+C)
© Digital Integrated Circuits2nd
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