Download Synthesis of Combinational Logic

EMT 351
Digital IC Design
Lecturers:
En. Rizalafande Che Ismail
(Subject Coordinator)
Pn. Siti Zarina Md. Naziri
Blok B, Tingkat 2, Kompleks Pusat Pengajian
Ex. 8452 / 012-3225646
Will be covering remaining chapters:
• All about VERILOG SYNTHESIS
– Combinational
– Sequential
– Language constructs
• SWITCH-LEVEL MODELS
– MOS, CMOS in Verilog
• DESIGN EXAMPLES
– FIFO, temperature monitor, bit-slice uC
• RAPID PROTOTYPING WITH FPGA
CHAPTER 8
Synthesis of Combinational Logic
Prepared by SITI ZARINA MD NAZIRI
Sources: SLIDES FROM RIZALAFANDE, CILETTI
DEFINITION - SYNTHESIS
“Process of creating sequence of
transformation between views of a
circuit, from a higher level abstraction to
a lower one, with each step leading to a
more detailed description of the physical
reality.”
HDL-BASED SYNTHESIS
• HDL–based synthesis provides:
–
–
–
–
Alternative to gate-level design
Higher level of design abstraction
Description of overall architecture
Description of functionality
• Synthesis tools provide:
– Automated gate-level representation
– Optimal representation
– Architectural exploration
HDL-BASED SYNTHESIS
Functional simulation
Design entry
HDL behavioral model
Design
verification
Timing simulation
Physical
optimization
and
implementation
PLD
FPGA, Arrays
Standard cells
HDL-based design flow
HDL-BASED SYNTHESIS
• Levels of synthesis
– Logic synthesis
• Boolean description  optimal circuit
– RTL synthesis
• RTL description  Boolean description
– Behavioral (high-level) synthesis
• Algorithmic model of functionality  RTL
description
HDL-BASED SYNTHESIS – LOGIC SYNTHESIS
• Tools which operate on Boolean
equations & produce optimal combinational
logic according to constraints (e.g. speed,
area, power & testability) based on library
used
HDL-BASED SYNTHESIS – LOGIC SYNTHESIS
Technology
libraries
Behavioral
description
TRANSLATION
ENGINE
Two-level
logic functions
OPTIMIZATION
ENGINE
Optimized multi-level
logic functions
MAPPING
ENGINE
Technology
implementation
Synthesis tool organization
HDL-BASED SYNTHESIS – RTL SYNTHESIS
• Transforms a behavior described in
terms of operations on registers, signals and
constraints into an optimal combinational
logic and thus map the result into the target
technology
• RTL description represents either a FSM or a
more general machine (data-flow graphs)
• In Verilog, the synthesis is represented by
language operators & synchronous
concurrent assignment to register variables
(i.e. non-blocking assignments)
HDL-BASED SYNTHESIS – BEHAVIORAL
SYNTHESIS
• Tools that synthesize data path elements,
control units and memory
• A relatively young technology, but successful
tools have been developed supporting
behavioral synthesis for DSP applications
• Poses the great challenge to EDA tools
because there are many algorithms still
cannot be synthesized easily
HDL-BASED SYNTHESIS – BEHAVIORAL
SYNTHESIS
Data flow graph
representation of behavior
TECHNOLOGY-INDEPENDENT DESIGN
• Describes only the functionality that needs
to be synthesized, not time delays
• Signals are correct & match the clock
boundaries in both behavioral & gate-level
realizations
– External clock & reset controls all storage element
– Inputs to combinational logic are primary inputs
or are from storage elements
– The combinational logic is assumed to settle in
one clock cycle
– Outputs may(not) be registered
TECHNOLOGY-INDEPENDENT DESIGN
2
3
4
1
1. External clock & reset controls all storage element
2. Inputs to combinational logic are primary inputs or are from
storage elements
3. The combinational logic is assumed to settle in one clock cycle
4. Outputs may(not) be registered
BENEFITS OF SYNTHESIS
• Fast generation of the gate-level
description from the HDL
• Reduced effort to debug the gate-level
design
• Efficient gate-level implementation
• Consistency between RTL and gate-level
descriptions
• Faster mechanism for re-targeting designs
(e.g. FPGAs to cells)
• Higher focus of the design effort
(Functionality vs. gates and transistors)
• Top-down organization with language-based
description and documentation
SYNTHESIS METHODOLOGY
1.
2.
3.
4.
5.
6.
7.
Focus on the overall functionality
Create architectural partition (top-down)
Develop unit functional descriptions
Validate the design units (bottom-up)
Follow a technology-independent design style
Synthesize a gate-level realization subject to
constraints
Conduct post-synthesis performance verification to
ensure timing and functionality
PRODUCT
Technology-specific optimized gate-level
realization of the design
SYNTHESIS METHODOLOGY
• Synthesis tools must be used
EFFECTIVELY:
– Follow design methodology
– Intelligent partitioning of functionality
– Smart HDL descriptive style (to achieve
expected results)
– Awareness of vendor-specific HDL
vocabulary (not all are synthesizable)
– Post-synthesis verification of gate-level
realization
VENDOR SUPPORT
•
•
•
•
•
•
•
•
Accept source code using the entire Verilog HDL
Ignore unsupported usage
Time declarations are ignored
Delay control (#) is ignored
All signals are assumed to be at maximum strength
Boolean operations on 'x' and 'z' are forbidden
Use only synthesizable constructs
Do not instantiate storage elements
VENDOR SUPPORT
FULLY supported Verilog constructs
• Module instantiation
• Name and positional port
mapping
• input, output, inout port
modes
• macromodule, module
• parameter
• integer and reg types
• All numeric bases
• Identifiers
• Continuous assignment
• Procedural assignment
• Non-blocking assignment
• Procedural-continuous
assignment
•
•
•
•
•
•
•
•
•
•
case, casex, casez, endcase
default
disable
function, endfunction
if, if ... else, if ... else ... if
Subranges in referenced
identifiers
Shift, conditional and
concatenation operators
Procedural blocks (begin …
end)
wire, wand, wor, tri supply0,
supply1
task, endtask (No timing or
event controls)
VENDOR SUPPORT
PARTIALLY supported Verilog constructs
• *, /, %
– Both operands must be constants or the second
operand must be a power of 2.
• for
– The loop range must be bound by static variables
• fork ... join
– No event control or delay control greater than a clock
period <= Cannot mix blocking and non-blocking
assignment in same behavior
• and, nand, &&, …
– May not use explicit ‘x’ or ‘z’ constructs with primitives
or operators.
VENDOR SUPPORT
IGNORED Verilog constructs
•
•
•
•
•
•
•
•
Intra-assignment (delay and event control operators)
scalared, vectored
small, medium, large
specify ... endspecify
$time
weak1, weak0, high0, high1, pull0, pull1
$keyword
wait
VENDOR SUPPORT
UNSUPPORTED constructs (Vendor-dependent)
• Assignments with bit or part
select on LHS
• Global variables
• ===, !==
• cmos, rcmos, rnmos,
nmos, pmos, rpmos
• tran, tranif0, tranif1,
rtran, rtranif0, rtranif1
• deassign (Not for
combinational)
• defparam
• event
• force
• fork, join
• forever, while
• initial
• pulldown, pullup
• release
• repeat
SYNTHESIS OF COMBINATIONAL LOGIC - RULES
Logic_inputs(t)
COMBINATIONAL
LOGIC
Logic_outputs(t)
Logic_Output(t) = f(Logic_Inputs(t))
• Avoid technology dependent modeling; i.e.
implement functionality, not timing
• The combinational logic must not have feedback
• Specify the output of a combinational behavior for
all possible cases of its inputs
• Logic that is not combinational will be synthesized
as sequential
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Logic_inputs(t)
COMBINATIONAL
LOGIC
Logic_outputs(t)
Logic_Output(t) = f(Logic_Inputs(t))
•
•
•
•
•
•
Netlist of primitives
User-defined primitives (UDPs)
Continuous assignments
Cyclic behavior
Function or task
Interconnected modules
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 1: Netlist of Primitives
• Combinational logic can be synthesized from a
netlist of gate-level Verilog primitives
• Synthesization by synthesis tool will correct &
remove redundant logic  provides safety to design
module or_nand_1 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
wire w1, w2, w3;
or (w1, x1, x2);
or (w2, x3, x4);
or (w3, x3, x4);
nand (y, w1, w2, w3, enable);
endmodule
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 2: UDPs
• Synthesis tool can operate on a UDP to first
obtain an equivalent representation in terms of
Boolean expressions, and then optimize the
logic (only covered by some tools)
module ….
table
// inputs output
// a b c
y
0 1 ?
:
1;
0 0 ?
:
0;
1 ? 1
:
1;
1 ? 0
:
0;
endtable
C
A
Y
B
Post-Synthesis
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 3: Continuous Assignments
• Synthesis tool translates continuous
assignment statement into a set of equivalent
Boolean equations which can be optimized
simultaneously
module or_nand_2 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
assign y = !(enable & (x1 | x2) & (x3 | x4));
endmodule
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 4: Cyclic (or Combinational) Behavior
• The event control expression must not be edgedependent, and all inputs to the behavior must be
included in the event control expression, otherwise a
latch will be inferred
module or_nand_3 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;
always @ (enable or x1 or x2 or x3 or x4)
if (enable)
y = !((x1 | x2) & (x3 | x4));
else
y = 1; // operand is a constant.
endmodule
NOTE:
An event control
expression does not
imply synthesis of a
clock or a reg
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 5: Function or Task
• Functions
- Represent combinational logic because the value
produced by a function depends only upon the
values of its arguments
- As a general rule, incomplete case statements and
incomplete conditionals should be avoid in order
to implement combinational logic
• Task
- Restrictions is similar to functions, but is more
general
- However, it must restricted for not using timing
control constructs in any procedural code it
contains
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
module or_nand_4 (enable, x1, x2, x3,
x4, y);
input enable, x1, x2, x3, x4;
output y;
assign y = or_nand (enable, x1, x2,
x3, x4);
function or_nand;
input enable, x1, x2, x3, x4;
begin
or_nand = ~(enable & (x1 | x2)
& (x3 | x4));
end
endfunction
endmodule
module or_nand_5 (enable, x1, x2, x3,
x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;
always @ (enable or x1 or x2 or x3 or
x4)
or_nand (enable, x1, x2, x3c, x4);
task or_nand;
input enable, x1, x2, x3, x4;
output y;
begin
y = !(enable & (x1 | x2) & (x3 | x4));
end
endtask
endmodule
 Simulation result for both module
SYNTHESIS OF COMBINATIONAL LOGIC - STYLES
Style 6: Interconnect Modules
• Combinational logic can be created by
interconnecting & synthesizing modules that
implement combinational logic using any styles
mentioned before
SIMULATION & SYNTHESIS EFFICIENCY
• The use of procedural-continuous
assignment (PCA) (assign.. deassign)
reduces the size of the event sensitivity list
and improves the simulation efficiency by
dynamically changing the sensitivity list
• However, some tools do not support PCA for
synthesis - two models might be used and
switched between simulation and synthesis
SIMULATION & SYNTHESIS EFFICIENCY
Simulation friendly
(prefered for simulation)
Synthesis & simulation friendly
(prefered for synthesis)
module or_nand_6
(enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;
module or_nand_3
(enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;
always @ (enable)
if (enable)
assign y = ~((x1 | x2) & (x3 | x4));
else
assign y = 1;
endmodule
always @ (enable or x1 or x2 or x3 or x4)
if (enable)
y = !((x1 | x2) & (x3 | x4));
else
y = 1; // operand is a constant.
endmodule
Example: or_nand
TECHNOLOGY MAPPING AND SHARED
RESOURCES
• Synthesis tools include a technology mapping
engine that covers the generic, optimized
multi-level Boolean description
• Depends on the tool, it may covered basic
library cells or more complex ones
• If the data flows within the behavior do not
conflict, the resource can be shared between
one or more paths
• This feature is vendor dependent, if the tool
does not automatically implement resource
sharing, the user must write a Verilog code
to force the sharing
THREE-STATE BUFFERS
• Verilog language has built-in constructs for
modeling and synthesizing the functionality
of three-state devices
• Three-state devices are controlled by a signal
whose value determines whether an input
signal is connected to the output
• This functionality is important in physical
circuits having multiple drivers
THREE-STATE BUFFERS
BUSES
• Play an important role in many systems
• Characterized by a ‘z’ logic to the bus driver signal
when the bus control signal is de-asserted.
Otherwise the bus is driven
• Easily described using Verilog continuous
assignment
module …..
assign data = (bus_enable) ? Output_bus : 32’bz;
endmodule
control signal
THREE-STATE BUFFERS
Bi-directional Bus Drivers
• Must be capable of sending and receiving data
• If a module having bi-directional port (inout), the
testbench cannot drive the port directly
• In order to do so, the designers need to assign value
to the register before loaded to the bus
module …
inout [31:0] data_to_from_bus;
….
assign in_data = (rcv_data) ?
data_to_from_bus : 32’bz;
assign data_to_from_bus = (send_data) ?
reg_to_bus : data_to_from_bus;
endmodule
THREE-STATE BUFFERS
Bus Loading
• The speed of a bus to operate is limited by the
capacitive loading placed on it by driving and
receiving circuits
• It is important that Verilog code of a bus circuit be
synthesized efficiently
• The recommended practice is to multiplex the
drivers of a bus so that it can reduce the capacitive
loading
module ….
assign data_to_from_bus = (enab_a) ? Reg_a_to_bus:
(enab_b) ? Reg_b_to_bus:32’bz;
endmodule
THREE-STATE OUTPUTS AND DON’T CARES
When the output of a module is assigned by a
conditional assignment, a variety of results are
possible with some leading to three-state outputs
module alu_with_z1….
assign alu_out = (enable == 1) ? Alu_reg:4’bz;
Result of
always @ (opcode or data_a or data_b)
alu_with_z2
case (opcode)
synthesis has
3’b001: alu_reg = data_a | data_b;
simpler
3’b010: alu_reg = data_a ^ data_b;
realization
3’b110: alu_reg = ~data_b;
default: alu_reg = 4’b0;
// alu_with_z2 has default: alu_reg = 4’bx;
endcase
endmodule
SUMMARY
• Combinational logic will form its output
based on its input
• UDPs, continuous assignments, instantiated
gates and behaviors that no need memory
will be synthesized into combinational logic
• Combinational logic easily to synthesize but
need to aware about unwanted latches that
result from incompletely-specified case
statements and conditionals