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Note: Certain parts of this presentation have been intentionally left blank or missing for you to complete during or after the class Custom Single Purpose Processors: Hardware Outline Chapter 2: Custom singlepurpose processors Introduction Combinational logic Sequential logic Custom single-purpose processor design RT-level custom single-purpose processor design Digital Foundations The basic model of a computer system: CPU MEM I/O Central Processing Unit (CPU) CPU MEM I/O Memory CPU MEM I/O Input/Output (I/O) CPU MEM I/O Hierarchical View of EP and Digital Systems CPU MEM Computer Architecture I/O Operating System HLLs State Machines Interface Method MSI Functions Design Techniques Gates Boolean Algebra Introduction Processor Digital circuit that performs a computation tasks Controller and datapath General-purpose: variety of computation tasks Single-purpose: one particular computation task Custom single-purpose: non-standard task A custom single-purpose processor may be Fast, small, low power But, high NRE, longer time-to-market, less flexible Digital camera chip CCD A2D CCD preprocessor Pixel coprocessor D2A lens JPEG codec Microcontroller Multiplier/Accum DMA controller Memory controller Display ctrl ISA bus interface UART LCD ctrl CMOS transistor on silicon Transistor The basic electrical component in digital systems Acts as an on/off switch Voltage at “gate” controls whether current flows from source to drain Don’t confuse this “gate” with a logic gate source gate 1 IC package IC source gate oxide channel drain Silicon substrate Conducts if gate=1 drain CMOS transistor implementations Complementary Metal Oxide Semiconductor We refer to logic levels Typically 0 is 0V, 1 is 5V Two basic CMOS types nMOS conducts if gate=1 pMOS conducts if gate=0 Hence “complementary” Basic gates Inverter, NAND, NOR source source gate Conducts if gate=1 drain nMOS gate Conducts if gate=0 drain pMOS Basic logic gates x F x 0 1 F 0 1 F=x Driver x F = x’ Inverter x F y F=xy AND F x 0 1 F 1 0 x y F = (x y)’ NAND F x 0 0 1 1 y 0 1 0 1 F 0 0 0 1 x y x 0 0 1 1 y 0 1 0 1 F 1 1 1 0 x y F F=x+y OR F = (x+y)’ NOR F x 0 0 1 1 y 0 1 0 1 F 0 1 1 1 x x 0 0 1 1 y 0 1 0 1 F 1 0 0 0 x F y F=xy XOR F y F=x y XNOR x 0 0 1 1 y 0 1 0 1 F 0 1 1 0 x 0 0 1 1 y 0 1 0 1 F 1 0 0 1 Combinational logic design Summary B) Truth table A) Problem description y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1. D) Minimized output equations y bc 00 01 11 10 a 0 1 y= z bc a 00 0 01 11 a 0 0 0 0 1 1 1 1 Inputs b c 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 C) Output equations Outputs z y y= z= E) Logic Gates a b c y 10 z 1 z= RT Level Combinational components Multiplexer I(m-1) I1 I0 n … S0 … n-bit, m x 1 Multiplexer S(log m) n O O= I0 if S=0..00 I1 if S=0..01 … I(m-1) if S=1..11 Decoder I(log n -1) I0 … Adder A Comparator B n A n log n x n Decoder … n-bit Adder O(n-1) O1 O0 carry sum sum = A+B (first n bits) carry = (n+1)’th bit of A+B With enable input e all O’s are 0 if e=0 With carry-in input Ci sum = A + B + Ci A B n n-bit Comparator n O0 =1 if I=0..00 O1 =1 if I=0..01 … O(n-1) =1 if I=1..11 ALU less equal greater less = 1 if A<B equal =1 if A=B greater=1 if A>B n B n n bit, m function S0 ALU … S(log m) n O O = A op B op determined by S. May have status outputs carry, zero, etc. Sequential Circuits Include feedback Presence of a clock Behavior is no longer simply a function of the inputs--must be evaluated synchronously with clock Flip-flops D-type J-K type S-R type etc. D-F/F P D Q CK P C Dn Qn+1 0 1 0 1 1 0 Illegal 0 1 0 0 1 X X X 0 1 1 1 1 Q* Excitation Function: Dn = Qn+1 C State Machines Mealy: Outputs depend on states and on inputs. Moore: Outputs depend only on states. One-Hot: A type of Moore machine in which there is one F/F per state. State Machine Models State Memory Moore Outputs (& One-Hot) Clk Inputs Combinatorial Network Mealy Outputs Sequential Circuit Design Problem statement State diagram Transition table Simplified excitation functions Implementation Verification Example Design a sequence detector that will identify 1011. 1011 SM Z State Diagram Input/Output Input Name Name Output Input/Output Input Moore Mealy One-Hot SMs Moore machines are glitchless since outputs change only synchronously with clock. For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-ofgates” FPGA. A 12-state SM: Don’t bother to reduce/encode. A 16-bit counter: Definitely encode states. SM for 1011 Sequence Detector 0 Reset 1 1 Found Found1 None 0 1 0 Found4 Found2 0 Z 1 1 Found3 0 Note: Dashed lines show non-resetting algorithm. Transition Table Output Present State Z 0 F0 F1 F2 F3 F4 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 Input Next State X 0 1 0 1 0 1 0 1 0 1 F0’ F1’ F2’ F3’ F4’ 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 Excitation Functions The Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant. For example: DF0 = F0•X* + F2•X*, instead of DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X* Similarly, DF1 = F0•X + F1•X + F4•X DF2 = F1•X* + F3•X* + F4•X* DF3 = ….. DF4 = ……. Simplification If there are any redundant terms, we can simplify; however, for One-Hot approach, there are no simplifications possible since we must account for every separate state path using a separate FF. Implementation Assign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown: F0 X* F2 X* & D PQ + F0 & Clk The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4. Verification Check that the SM performs as required. More complex input vectors are required since the internal state memory expands total possible states. Use simulation tools. The Power of One-Hot Design Can skip transition table--“read” the implementation directly off the state diagram: 1 Found None 1 Found1 F0 X F1 X & + D Q & C Clk F1 Sequential Circuit Functions Counters Binary, BCD Ripple, Synchronous Registers and Latches PIPO, PISO, SIPO, SISO Sequential components I n load clear n-bit Register shift n-bit Shift register I n Q clear n-bit Counter n Q Q Q= 0 if clear=1, I if load=1 and clock=1, Q(previous) otherwise. count Q = lsb - Content shifted - I stored in msb Q= 0 if clear=1, Q(prev)+1 if count=1 and clock=1. Sequential logic design Summary A) Problem Description You want to construct a clock divider. Slow down your preexisting clock so that you output a 1 for every four clock cycles Sequential logic design (cont.) F) Combinational Logic E) Minimized Output Equations a x I1 I0 Q1 Q0