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Chapter 6 Differential and
Multistage Amplifiers
Introduction
6.1 The BJT differntial pair
6.2 Small-signal operation of the BJT differential amplifier
6.3 Other nonideal characteristics of the
differential amplifier
6.4 MOS diffenrential amplifiers
6.5 Biasing in intergrated circuits
6.6 The BJT differential amplifier with active load
6.9 Multistage amplifiers
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Introduction


The differential amplifier
(pair) configuration is the
most widely used
building block in analog
IC design.
BJT differential amplifier
is the basis of a veryhigh-speed logic circuit
family, called emittercoupled logic (ECL).
Why?
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Reasons:
Direct coupling between signal source and amplifier
will easily cause temperature Drift (zero drift).
What shall we do?
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Advantages

There are 2 reasons for using differential
in preference to single-ended amplifiers.
(1) Differential circuits are much less sensitive to noise
and interference than single-ended circuits.
(2) It enables us to bias the amplifier and to couple
amplifier stage without the need of bypass and
coupling capacitors which are impossible to
fabricate economically by IC technology.
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6.1 The BJT Differential Pair
Basic Operation-1:Common-mode input
The differential pair with a commonmode input signal vCM.
Two transistors are matched.
Current source with infinite output
resistance.
Current I divide equally between two
transistors.
The difference in voltage between the
two collector is zero.
The differential pair rejects the
common-mode input signal as long as
two transistors remain in active region.
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Basic Operation-2
The differential pair with a
“large” differential input signal.
Q1 is on and Q2 is off.
Current I entirely flows in Q1.
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Basic Operation-3
The differential pair with a
large differential input signal of
polarity opposite to that in (b).
Q2 is on and Q1 is off.
Current I entirely flows in Q2.
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Basic Operation-4:Difference-mode or
Difference signals
The differential pair with a
small differential input signal vi.
Small signal operation or
linear amplifier.
Assuming the bias current
source I to be ideal and thus I
remains constant with the
change in vCM.
Increment in Q1 and
decrement in Q2.
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Large-Signal Operation
iE1 
IS
v B1  v E 
VT
e

I S v v V
iE 2  e

1
iE1

v  v
iE1  iE 2
1 e
1
iE 2

v  v
iE1  iE 2
1 e
iE1  iE 2  I
I
iE1 
v  v 
V
1 e
I
iE 2 
v  v 
V
1 e
B2
E
T
B2
B2
B1

B1
B2

VT
VT
B1
T
B1
B2
T
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Large-Signal Operation



Nonlinear curves.
Linear segments.
Maximum value of input differential voltages
vid  12 VT
vid  4VT  100mv

as a small-signal amplifier
can be used as a fast current
switch
Enlarge the linear segment by including equal
resistance Re in series with the emitters.
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Large-Signal Operation
The transfer characteristics of the BJT differential pair (a) can be linearized
by including resistances in the emitters.
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6.2 Small-signal operation of the BJT
differential amplifier
The currents and voltages in the differential amplifier when a small
differential input signal vid is applied.
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Small-Signal Operation
VT VT

IE I
2
v
re  d
2re
re 
ic  ie 
 vd
2re
 gm
vd
2
A simple technique for determining the signal currents in a differential amplifier
excited by a differential voltage signal vid; dc quantities are not shown.
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Small-Signal Operation
A differential
amplifier with emitter
resistances.
Only signal
quantities are shown
(in color).
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Input Differential Resistance
•
Input differential resistance is finite.
vd
vd
Rid 

 (1   )2re  2r
v
ib
d
2re
 1
The resistance seen between the two bases is equal to
the total resistance in the emitter circuit multiplied by
(1+β).
• Input differential resistance of differential pair with
emitter resistors.
vid
Rid 
 (1  （
) 2re＋2 Re )
ib
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Differential Voltage Gain
•
Differential voltage gain

Output voltage taken single-ended
vo1
Ad 1 
  12 g m RC
vid

vo 2 1
Ad 2 
 2 g m RC
vid
Output voltage taken differentially
vo 2  vo1
Ad 
 g m RC
vid
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Differential Voltage Gain
•
Differential voltage gain of the differential pair with
resistances in the emitter loads
 Output voltage taken single-ended
vo1
1 RC
Ad 1   
vid
2 re  Re

vo 2 1 RC
Ad 2 

vid 2 re  Re
Output voltage taken differentially
vo 2  vo1
RC
Ad 

vid
re  Re
The voltage gain is equal to the ratio of the total
resistance in the collector circuit to the total
resistance in the emitter circuit.
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Differential Half-Circuit Analysis
Differential input signals.
Single voltage at joint
emitters is zero.
The circuit is symmetric.
Equivalent commonemitter amplifiers in (b).
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Differential Half-Circuit Analysis
This equivalence applies only for
differential input signals.
Either of the two commonemitter amplifiers can be used to
find the differential gain,
differential input resistance,
frequency response, and so on
Half circuit is biased at I/2.
The voltage gain(with the output
taken differentially) is equal to the
voltage of half circuit.
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Differential Half-Circuit Analysis
The differential amplifier
fed in a single-ended manner.
Signal voltage at the emitter
is not zero.
Almost identical to the
symmetric one.
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Common-Mode Gain
The differential amplifier fed by a common-mode voltage signal vicm.
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Common-Mode Gain
RC
RC
vc1  vCM
 vCM
2 REE  re
2 REE
vc1  vc 2
Equivalent “half-circuits” for
common-mode calculations.
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Common-Mode Gain
•
Common-mode voltage gain

Output voltage taken single-ended
vo1
RC
Acm1 

vicm
2 REE

Acm 2
vo 2
RC


vicm
2 REE
Output voltage taken differentially
Acm 
vo 2  vo1
0
vid
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Common-Mode Rejection Ratio
•
Common-mode rejection ratio

Output voltage taken single-ended
Ad
CMRR 
ACM

1
g m RC
 2
 g m REE
RC

2R
Output voltage taken differentially
CMRR  
•
This is true only when the circuit is symmetric.
Mismatch on CMRR
RC RC
Acm 
2 REE RC
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 v1  v2 
vo  Ad v1  v2   ACM 

 2 
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Input Common-Mode Resistance
Definition of the input common-mode resistance Ricm.
The equivalent common-mode half-circuit.
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Input Common-Mode Resistance
•
Input common-mode resistance
2 Ricm  (1   )(2 REE // ro )
Ricm
•
ro
 (1   )( REE // )
2
Input common-mode resistance is very large.
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Example 6.1
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Example6.1 (cont’d)
•
•
•
•
•
Evaluate the following:
The input differential resistance.
The overall differential voltage gain(neglect the
effect of ro).
The worst-case common-mode gain if the two
collector resistance are accurate within ±1%.
The CMRR, in dB.
The input common-mode resistance(suppose the
Early voltage is 100V).
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6.3 Other Nonideal characteristic of the
Differential Amplifier
Input offset voltage Vos
Ideal differential pair is perfectly matched, but practical circuits exhibits
Mismatches that result in a dc Vo is not zero. Vo is the output dc offset
Voltage. Input offset voltage Vos:
VOS 
VO
Ad
Input bias and offset currents Ios
I B1  I B 2 
I
2
 1
perfectly matched
I OS  I B1 I B 2
Input Common-Mode Range
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6.4 MOS Differential Amplifiers
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Operation with a Common –Mode
Input Voltage
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Operation with a Common –Mode
Input Voltage
•
•
•
•
•
Symmetry circuit.
Common-mode voltage.
Current I divides equally between two
transistors.
The difference between two drains is zero.
The differential pair rejects the commonmode input signals.
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Operation with a Differential Input
Voltage
The MOS differential
pair with a differential
input signal vid applied.
With vid positive: vGS1 >
vGS2, iD1 > iD2, and vD1 <
vD2; thus (vD2  vD1) will be
positive.
With vid negative: vGS1 <
vGS2, iD1 < iD2, and vD1 >
vD2; thus (vD2  vD1) will be
negative.
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Operation with a Differential Input
Voltage
•
•
•
Differential input voltage.
Response to the differential input signal.
The current I can be steered from one MOS to
the other by varying the differential input voltage
in the range:
 2VOV  vid  2VOV
•
When differential input voltage is very small, the
differential output voltage is proportional to it, and
the gain is high.
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Large-Signal Operation
Transfer characteristic
curves
Normalized plots of the
currents in a MOSFET
differential pair.
Note that VOV is the
overdrive voltage at
which Q1 and Q2 operate
when conducting drain
currents equal to I/2.
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Large-Signal Operation
•
•
•
•
•
•
Nonlinear curves.
Maximum value of input differential voltage.
When vid = 0, two drain currents are equal to I/2.
Linear segment.
Linearity can be increased by increasing
overdrive voltage(see next slide).
Price paid is a reduction in gain(current I is kept
constant).
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Large-Signal Operation
The linear range of operation of the MOS differential pair can be
extended by operating the transistor at a higher value of VOV.
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Small-Signal Operation of MOS
Differential Pair
•
•
•
•
•
Linear amplifier
Differential gain
Common-mode gain
Common-mode rejection ratio(CMRR)
Mismatch on CMRR
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Differential Gain
a common-mode
voltage applied to
set the dc bias
voltage at the gates.
vid applied in a
complementary (or
balanced) manner.
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Differential Gain
I
2 I D 2( 2)
I
gm 


VOV
VOV
VOV
Signal voltage at the joint source connection must be zero.
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Differential Gain
An alternative way of
looking at the smallsignal operation of
the circuit
.
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Differential Gain
•
Differential gain

Output taken single-ended
vo1
Ad 1 
  12 g m RD
vid

vo 2 1
Ad 2 
 2 g m RD
vid
Output taken differentially
vo
Ad 
 g m RD
vid

Advantages of output signal taken differentially
• Reject common-mode signal
• Increase in gain by a factor of 2(6dB)
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Differential Gain
MOS differential amplifier with ro and RSS taken into account.
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Differential Gain
Equivalent circuit for determining the differential gain.
Each of the two halves of the differential amplifier circuit is a commonsource amplifier, known as its differential “half-circuit.”
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Differential Gain
•
Differential gain
 Output taken single-ended
vo1
Ad 1 
  12 g m ( RD // ro )
vid
vo 2 1
Ad 2 
 2 g m ( RD // ro )
vid

Output taken differentially
vo
Ad 
 g m ( RD // ro )
vid
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Common-Mode Gain
The MOS differential
amplifier with a commonmode input signal vicm.
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Common-Mode Gain
Equivalent circuit for determining the common-mode gain (with ro ignored).
Each half of the circuit is known as the “common-mode half-circuit.”
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Common-Mode Gain
•
Common-mode gain

Output taken single-ended
Acm1  Acm 2

vo1 vo 2
RD
RD




1
vicm vicm
2 Rss
 2 Rss
gm
Output taken differentially
vo 2  vo1
Acm 
0
vicm
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Common-Mode Rejection Ratio
•
Common-mode rejection ratio(CMRR)

Output taken single-ended
Ad 1
Ad 2
CMRR 

 g m Rss
Acm1
Acm 2

Output taken differentially
CMRR  
This is true only when the circuit is perfectly matched.
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Mismatch on CMRR
•
Effect of RD mismatch on CMRR
vo  vo 2  vo1  
RD
vicm
2 Rss
CMRR  (2 g m Rss ) (
•
RD
)
RD
Effect of gm mismatch on CMRR
CMRR  (2 g m Rss ) (
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g m
)
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Mismatch on CMRR
Determine the commonmode gain resulting from a
mismatch in the gm values of
Q1 and Q2.
Common-mode half
circuit is not available due
to mismatch in circuit.
The nominal value gm.
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Mismatch on CMRR
•
Effect of gm mismatch on CMRR
id 1
g m1

id 2
gm2
vs  vicm
id 1  id 2
g m vicm

2 g m Rss
g m
CMRR  (2 g m Rss ) (
)
gm
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Homework



March 30, 2009
6.1; 6.18; 6.21; 6.27;
6.87
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6.5 Biasing in Integrated Circuits
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Design Philosophy of Integrated
Circuits

Strive to realize as many of the functions
required as possible using MOS transistors only.

Large even moderate value resistors are to be
avoided

Constant-current sources are readily available.

Coupling and bypass capacitors are not available
to be used, except for external use.
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Design Philosophy of Integrated
Circuits

Low-voltage operation can help to reduce power
dissipation but poses a host of challenges to the
circuit design.

Bipolar integrated circuits still offer many exciting
opportunities to the analog design engineer.
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Biasing mechanism for ICs
BJT Circuits
•
•

The basic BJT current source

Current-steering
MOSFET Circuits

The basic MOSFET current source

MOS current-steering circuits
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Biasing mechanism for ICs(cont’d)
•
Current-mirror circuits with improved
performance

A bipolar mirror with base-current compensation

The wilson current mirror

The current steering circuits

The widlar current source
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The Basic BJT Current Mirror
Io 
I REF
Io
I REF
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

IE
 1
 2

IE
 1

 2

1
1
2

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A Simple BJT Current Source.
I o  I REF
I REF 
VCC  VBE ( on)
R
VA
Ro  r02 
I CQ
Disadvantages:
1) Increasing Io ……
2) Decreasing Io……
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Current Steering
VCC  VEE  VEB1  VBE 2
I REF 
R
I1  I REF
I 2  I REF
I 3  2 I REF
I 4  3I REF
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Current-Mirror Circuits with
Improved Performance
Two performance parameters need to be
improved:
a.
The accuracy of the current transfer ratio
of the mirror.
b.
The output resistance of the current
source.
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Current Mirror with Base-Current
Compensation
Io
I REF
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1

1 2
2
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The Wilson Bipolar Current Mirror
I REF
Io 
Io
I REF
 
2 


I
2 E
   1   1 

 1
IE
1

1 2
2

ro
Ro 
2
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The Widlar Current Source
I 
VBE1  VT ln  REF 
 IS 
I
VBE 2  VT ln  o
 IS



I 
VBE1  VBE 2  VT ln  REF 
 Io 
VBE1  VBE 2  I o RE
VT
I REF
Io 
ln(
)
RE
Io
Ro  1  g m ( RE // r )ro
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The advantages of Widlar Current
Source
Example6.2 p518
1.
Widlar circuit allows the generation of a
small constant current using relatively
small resistors( saving in chip area ).
2.
Another important characteristic of the
widlar current source is that its output
resistance is high.
Ro  R  (1  g m R )ro  (1  g m R )ro
'
E
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'
E
'
E
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The Basic MOSFET Current Source
1 ' W 
2
K n   VGS  Vtn 
2
 L 1
V V
I D1  I REF  DD GS
R
1
W 
2
I o  I D 2  K ' n   VGS  Vtn 
2
 L 2
I D1 
Io
I REF
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（W L ) 2

（W L )1
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MOS Current-Steering Circuits
I 2  I REF
(W L) 2
(W L)1
I 3  I REF
(W L)3
(W L)1
I5  I 4
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(W L)5
(W L) 4
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The Wilson MOS Current Mirror
Ro  g m3ro3ro 2
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6.6 The Differential Amplifier with
Active Load


Replace resistance RD with a constant
current source results in a much high
voltage gain as well as saving in chip area.
Convert the output from differential to
single-ended.
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The Bipolar Differential Pair with
Active Load
vd
gm 
2
vd
gm 
2

vd
gm
2
Quiescent analysis:
if the circuit Is perfectly
matched, no output
Current flows through
the output Terminal.
Active-loaded bipolar differential pair.
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Determine the Transconductance
Ro  ro 2 // ro 4
Ro  ro / 2 for the case ro 2  ro 4
vo  g m vd (ro / 2)
vo g m ro
Ad  
vd
2
I
Gm  g m  2
VT
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Differential Gain
•
The differential gain is determined as GmRo
Ad  Gm Ro  g m (ro 2 // ro 4）
•
When
ro 2  ro 4  ro
A0
Ad  g m ro 
2
1
2
•
Input differential resistance
Rid  2r
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Common-Mode Gain and CMRR
Common-mode gain:
Acm  
ro 4 2
r
  o4
2 REE  3
 3 REE
CMRR
CMRR  ( g m r02 // ro 4 )(
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 3 REE
ro 4
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)
Differential-to-Single-Ended
Conversion
Drawback:
Lose a factor of
2(or 6 dB)
A simple but inefficient approach for differential to
single-ended conversion.
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The Active-Loaded MOS Differential Pair
The active-loaded MOS differential pair.
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The Active-Loaded MOS Differential Pair
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The Active-Loaded MOS Differential Pair
The circuit with a differential input signal applied, neglecting
the ro of all transistors.
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Differential Gain of the ActiveLoaded MOS Pair
•
•
•
•
The output resistance ro plays a significant
role in the operation of active-loaded
amplifier.
Asymmetric circuit.
Half-circuit is not available.
The gain will be determined as GmRo
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Short-Circuit Transconductance
Determining the short-circuit transconductance Gm = io/vid
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Short-Circuit Transconductance
Gm  g m
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Output Resistance
Circuit for determining Ro. The circled numbers
indicate the order of the analysis steps.
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Output Resistance
Circuit for
determining Ro.
The circled numbers
indicate the order of
the analysis steps.
Ro  ro 2 // ro 4
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Differential Gain
•
The differential gain is determined as GmRo
Ad  Gm Ro  g m (ro 2 // ro 4）
•
When r  r  r
o2
o4
o
A0
Ad  g m ro 
2
1
2
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Common-Mode Gain and CMRR
Analysis of the activeloaded MOS differential
amplifier to determine its
common-mode gain.
Power supplies
eliminated.
Rss is the output resistance
of the current source.
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Common-Mode Gain and CMRR
Asymmetric circuit.
Each of the two transistors
as a CS configuration with a
large source degeneration
resistance 2Rss.
Common-mode gain:
ro 4
1
1
Acm  

2 Rss 1  g m3r03
2 g m3 Rss
CMRR
CMRR  ( g m ro )( g m Rss )
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Comparison with MOS circuits
1.
2.
3.
4.
The MOS mirror does not suffer from the finiteβeffect.
In the BJT mirror and current source, the output
voltage can be within VCEsat; the corresponding
value in MOS circuit is VGS-Vt>VCEsat, where powersupply voltages are being steadily reduced.
The current transfer ratio in the BJT mirror is
determined by the relative areas of the transistors,
whereas in a MOS mirror it is determined by the
relative (W/L) ratio.
Both of mirror circuit have an output resistance of
ro=VA/I, however, VA is usually lower for MOS
devices.
Note: The fifth edition P550-552
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Homework
April 8th, 2009
6.45; D6.60;
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6.7 Multistage Amplifiers
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Multistage Amplifier
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Multistage Amplifier
•
•
•
•
•
The first stage(input stage) is differential-in,
differential-out and consists of Q1 and Q2.
The second stage is differential-in, single-endedout amplifier which consists of Q3 and Q4.
The third stage is CE amplifier which consists of
pnp transistor Q7 to shifting the dc level.
The last stage is the emitter follower.
Biasing stage.
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Multistage Amplifier
Equivalent circuit for calculating
the gain of the input stage of the
example.
Input differential resistance
Rid  2r 1  20.2k
Gain of first stage
v01 Ri 2 //( R1  R2 )
A1 

 22.4
vid
re1  re 2
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Multistage Amplifier
Equivalent circuit for
calculating the gain of the
second stage of the
example.
Gain of second stage
v02
Ri 3 // R3
A2 

 59.2
v01
re 4  re5
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Multistage Amplifier
Equivalent circuit for
calculating the gain of the third
stage of the example.
Gain of third stage
v03
Ri 4 // R5
A3 

 6.42
v02
re 7  R4
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Multistage Amplifier
Equivalent circuit for calculating
the gain of the output stage of the
example.
Gain of output stage
v0
R6
A4 

 0.998
v03
re8  R6
Output resistance
Ro  R6 // re8  R5 (1   )  152
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Two-Stage CMOS Op-Amp
Configuration
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Homework:
April 8th, 2008
6.87
6.121
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