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Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003 © Digital Integrated Circuits2nd Inverter Propagation Delay © Digital Integrated Circuits2nd Inverter CMOS Inverter Propagation Delay VDD tpHL = f(Ron.CL) = 0.69 RonCL Vout ln(0.5) Vout CL Ron 1 VDD 0.5 0.36 Vin = V DD RonCL © Digital Integrated Circuits2nd t Inverter MOS transistor model for simulation G CGS CGD D S CGB CSB CDB B © Digital Integrated Circuits2nd Inverter Computing the Capacitances Consider each capacitor individually is almost impossible for manual analysis VDD VDD M2 Vin Cg4 Cdb2 Cgd12 M4 Vout Cdb1 Cw M1 Vout2 Cg3 M3 Interconnect Fanout Simplified Model © Digital Integrated Circuits2nd Vin Vout CL Inverter Computing the Capacitances NMOS and PMOS transistor are either in cutoff or saturation mode during at least the first half (50%) of the output transient. So, the only contributions to Cgd are the overlap capacitance, since channel capacitance occurs between either Gate-Body for transistors in cutoff region or GateSource for transistors in saturation region. © Digital Integrated Circuits2nd Inverter The Miller Effect Cgd1 V Vout Vout V Vin M1 V 2Cgd1 M1 V Vin “A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.” © Digital Integrated Circuits2nd Inverter The Miller Effect Consider the situation that an impedance is connected between input and output of an amplifier The same current flows from (out) the top input terminal if an impedance Z in,Miller is connected across the input terminals The same current flows to (in) the top output terminal if an impedance Z out, Miller is connected across the output terminal This is know as Miller Effect Two important notes to apply Miller Effect: There should be a common terminal for input and output The gain in the Miller Effect is the gain after connecting feedback impedance Z f Inverter © Digital Integrated Circuits2nd Graphs from Prentice Hall Computing the Capacitances © Digital Integrated Circuits2nd Inverter CMOS Inverters VDD ADp=45 λ 2 PDp=19 λ PMOS 9λ/2λ In Out Metal1 Polysilicon ADn=19 λ 2 PDn=15 λ 3λ/2λ NMOS © Digital Integrated Circuits2nd GND Inverter Junction Capacitance © Digital Integrated Circuits2nd Inverter Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest © Digital Integrated Circuits2nd Inverter Capacitance parameters in 0.25mm CMOS process Cdb will be slightly different in L-to-H and Hto-L, why? (the pn junction reverse bias voltage range) © Digital Integrated Circuits2nd Cgd1 Cgd2 Cdb1 Cdb2 Cg3 Cg4 HL(fF) 0.23 0.61 0.66 1.50 0.76 2.28 LH(fF) 0.23 0.61 0.90 1.15 0.76 2.28 Inverter Transient Response Cgd directly couples the steep input change before the circuit can even start to react to the changes at input (potential forward bias the pn junction) 3 2.5 ? Vout(V) 2 tp = 0.69 CL (Reqn+Reqp)/2 1.5 1 tpLH tpHL 0.5 0 -0.5 0 0.5 1 1.5 t (sec) © Digital Integrated Circuits2nd 2 2.5 -10 x 10 Inverter Low-to-High and High-to-Low delay It is desired to have identical propagation delays for both rising and falling inputs. Equal delay requires equal equivalent onresistance, thus equal current IDAST (neglecting the channel length modulation) This demands almost the same requirements for a Vm at VDD/2. Why? © Digital Integrated Circuits2nd Inverter Requirements for equal delay 2 VDSAT (VDD VT )VDSAT I DSAT 2 V ' W I Dn k n ( ) n VDSATn (VDD VTn ) DSATn L 2 VDSATp ' W I Dp k p ( ) p VDSATp (VDD VTp ) L 2 W k' L Assume VDD VTp VDSATp / 2 ' then k p VDSATp (W / L) p ' k n VDSATn (W / L) n k pVDSATp k nVDSATn 1 This is exactly the formerly defined parameter r (last lecture) © Digital Integrated Circuits2nd Inverter Design for delay performance Keep capacitances small • careful layout, e.g. to keep drain diffusion as small as possible Increase transistor sizes • watch out for self-loading! When intrinsic capacitance starts to dominate the extrinsic ones Increase VDD (????) © Digital Integrated Circuits2nd Inverter Delay as a function of VDD 5.5 For fixed (W/L) 5 tp(normalized) 4.5 Recall a range of low voltage is able to give even better voltage transfer characteristic 4 3.5 3 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 V 1.8 2 2.2 2.4 (V) DD © Digital Integrated Circuits2nd Inverter Device Sizing -11 3.8 x 10 (for fixed load and VDD) 3.6 3.4 tp(sec) 3.2 3 2.8 Self-loading effect: Intrinsic capacitances dominate 2.6 2.4 2.2 2 2 4 6 © Digital Integrated Circuits2nd 8 S W/L 10 12 14 Inverter NMOS/PMOS ratio -11 5 x 10 tpHL tpLH 4.5 tp(sec) (Average) tp b= Wp/Wn 4 Lp=Ln 3.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 b Widening PMOS improves the L-H delay by increasing the charge current, but it also degrades the H-L by giving a larger parasitic capacitance. Considering average is more meaningful!! © Digital Integrated Circuits2nd Inverter Delay Definitions © Digital Integrated Circuits2nd Inverter Impact of Rise Time on Delay 0.35 tpHL(nsec) 0.3 0.25 0.2 0.15 0 © Digital Integrated Circuits2nd 0.2 0.4 0.6 trise (nsec) 0.8 1 Inverter Custom design process: An inverter design example © Digital Integrated Circuits2nd Inverter 1. Schematic design © Digital Integrated Circuits2nd Inverter 2. Layout design © Digital Integrated Circuits2nd Inverter Step 1: define Nwell (for Pmos) © Digital Integrated Circuits2nd Inverter Step 2: define pselect (for Pmos) © Digital Integrated Circuits2nd Inverter Step 3: define active region (for Pmos) © Digital Integrated Circuits2nd Inverter Step 4: define poly (gate for Pmos) © Digital Integrated Circuits2nd Inverter Step 5: define contacts (for Pmos) © Digital Integrated Circuits2nd Inverter Step 6: define Vdd and connect source (of Pmos) to it © Digital Integrated Circuits2nd Inverter Step 7: make at least one Nwell contact © Digital Integrated Circuits2nd Inverter Step 8: create Nmos (repeat similar steps before except you do not need make Nwell) © Digital Integrated Circuits2nd Inverter step9: make input and output connections © Digital Integrated Circuits2nd Inverter 2. DRC (Design Rule Check) © Digital Integrated Circuits2nd Inverter Correct error if there is any © Digital Integrated Circuits2nd Inverter After correction © Digital Integrated Circuits2nd Inverter 3. LVS (Layout versus Schematic) © Digital Integrated Circuits2nd Inverter 4. Extract Layout parasitics and post-layout simulation © Digital Integrated Circuits2nd Inverter CMOS Inverter N Well VDD VDD PMOS 2l Contacts PMOS In Out In Out Metal 1 Polysilicon NMOS NMOS GND © Digital Integrated Circuits2nd Inverter Two Inverters Layout preference: Share power and ground Abut cells VDD Connect in Metal © Digital Integrated Circuits2nd Inverter Impact of Process Variations (DFM) 2.5 2 Good PMOS Bad NMOS 1.5 out (V) Nominal V Good NMOS Bad PMOS 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) © Digital Integrated Circuits2nd in Inverter Inverter Sizing for delay © Digital Integrated Circuits2nd Inverter Inverter with Load W means the size is increased by a factor of W with respect to the minimum size Delay 3W W Cint CL Load Delay = kRW(Cint + CL) = kRWCint + kRWCL = Delay (Internal) + Delay (Load) = kRW Cint(1+ CL /Cint) © Digital Integrated Circuits2nd Inverter Delay as function of size Delay = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) RW = Runit / W ; Cint = W Cunit t p t p 0 (1 C L /(WCunit )) tp0 = 0.69RunitCunit • Intrinsic delay is fixed and independent of sizeW • Making W large yields better performance gain, eliminating the impact of external load and reducing the delay to intrinsic only. But smaller gain at penalty of silicon area if W is too large! © Digital Integrated Circuits2nd Inverter Delay Formula Delay ~ RW Cint C L t p kRW Cint 1 C L / Cint t p 0 1 f / Cint = Cgin with 1 for modern technology (see page199 Cgin : input gate capacitance CL = f Cgin - effective fanout This formula maps the intrinsic capacitor and load capacitor as functions of a common capacitor, which is the gate capacitance of the minimum-size inverter © Digital Integrated Circuits2nd Inverter Single inverter versus inverter chain Gate sizing for an isolated gate is not really meaningful. Realistic chips always have a long chain of gates. So, a more relevant and realistic problem is to determine the optimal sizing for a chain of gates. © Digital Integrated Circuits2nd Inverter Inverter Chain In Out CL If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters? © Digital Integrated Circuits2nd Inverter Apply to Inverter Chain (fixed N stages) Unit size (minimum size) inverter Size ? In 1 2 Size ? N Out CL tp = tp1 + tp2 + …+ tpN C gin, j 1 t pj ~ RunitCunit 1 C gin , j N N C gin, j 1 t p t p, j t p0 1 C j 1 i 1 gin, j © Digital Integrated Circuits2nd , C gin, N 1 C L Inverter Optimal Tapering for Given N Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N Minimize the delay, find N - 1 partial derivatives equated to 0 Result: Cgin,j+1/Cgin,j = Cgin,j /Cgin,j-1 Size of each stage is the geometric mean of two neighbors C gin, j C gin, j 1C gin, j 1 - each stage has the same effective fanout - each stage has the same delay © Digital Integrated Circuits2nd Inverter Optimum Delay for fixed N stages When each stage is sized by f and has same effective fanout f: f N F CL / Cgin,1 Effective fanout of each stage: effective fanout of the overall circuit f NF Minimum path delay N t p t p, j j 1 © Digital Integrated Circuits2nd C gin, j 1 t p 0 1 C i 1 gin, j N Nt p 0 (1 N F / ) Inverter Example In C1 Out 1 f f2 CL= 8 C1 CL/C1 has to be evenly distributed across N = 3 stages: f 38 2 © Digital Integrated Circuits2nd Inverter Optimum Number of Stages For a given load CL and given input capacitance Cin Find optimal sizing f CL F Cin f Cin N t p Nt p 0 F 1/ N ln F with N ln f t p 0 ln F f / 1 ln f ln f t p t p 0 ln F ln f 1 f 0 2 f ln f For = 0, f = e, N = lnF © Digital Integrated Circuits2nd f exp 1 f Inverter Optimum Effective Fanout f Optimum f for given process defined by f exp 1 f © Digital Integrated Circuits2nd fopt = 3.6 for =1 Inverter Normalized delay function of F t p Nt p 0 1 N F / © Digital Integrated Circuits2nd fopt = 4 Inverter Buffer Design 1 f tp 1 64 65 2 8 18 64 3 4 15 64 4 2.8 15.3 64 1 8 1 4 16 2.8 8 1 N 64 © Digital Integrated Circuits2nd 22.6 Inverter