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Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance 4: CMOS Transistor Theory CMOS VLSI Design Slide 2 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance – I = C (DV/Dt) -> Dt = (C/I) DV – Capacitance and current determine speed Also explore what a “degraded level” really means 4: CMOS Transistor Theory CMOS VLSI Design Slide 3 MOS Capacitor Gate and body form MOS capacitor Operating modes – Accumulation – Depletion – Inversion Vg < 0 + - polysilicon gate silicon dioxide insulator p-type body (a) 0 < V g < Vt + - depletion region (b) V g > Vt + - inversion region depletion region (c) 4: CMOS Transistor Theory CMOS VLSI Design Slide 4 Terminal Voltages Vg Mode of operation depends on Vg, Vd, Vs + + – Vgs = Vg – Vs Vgs Vgd – Vgd = Vg – Vd Vs Vd – Vds = Vd – Vs = Vgs - Vgd + Vds Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation – Cutoff – Linear – Saturation 4: CMOS Transistor Theory CMOS VLSI Design Slide 5 nMOS Cutoff No channel Ids = 0 Vgs = 0 + - g + - s d n+ n+ Vgd p-type body b 4: CMOS Transistor Theory CMOS VLSI Design Slide 6 nMOS Linear Channel forms Current flows from d to s V – e from s to d Ids increases with Vds Similar to linear resistor gs > Vt + - g + - s d n+ n+ Vgd = Vgs Vds = 0 p-type body b Vgs > Vt + - g s + d n+ n+ Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt p-type body b 4: CMOS Transistor Theory CMOS VLSI Design Slide 7 nMOS Saturation Channel pinches off Ids independent of Vds We say current saturates Similar to current source Vgs > Vt + - g + - Vgd < Vt d Ids s n+ n+ Vds > Vgs-Vt p-type body b 4: CMOS Transistor Theory CMOS VLSI Design Slide 8 I-V Characteristics In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 4: CMOS Transistor Theory CMOS VLSI Design Slide 9 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Qchannel = gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 4: CMOS Transistor Theory CMOS VLSI Design Slide 10 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Qchannel = CV C= gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 4: CMOS Transistor Theory CMOS VLSI Design Slide 11 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Qchannel = CV Cox = ox / tox C = Cg = oxWL/tox = CoxWL V= gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 4: CMOS Transistor Theory CMOS VLSI Design Slide 12 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Qchannel = CV Cox = ox / tox C = Cg = oxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 4: CMOS Transistor Theory CMOS VLSI Design Slide 13 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E-field between source and drain v= 4: CMOS Transistor Theory CMOS VLSI Design Slide 14 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E= 4: CMOS Transistor Theory CMOS VLSI Design Slide 15 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: – t= 4: CMOS Transistor Theory CMOS VLSI Design Slide 16 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: – t=L/v 4: CMOS Transistor Theory CMOS VLSI Design Slide 17 nMOS Linear I-V Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross I ds 4: CMOS Transistor Theory CMOS VLSI Design Slide 18 nMOS Linear I-V Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds t 4: CMOS Transistor Theory CMOS VLSI Design Slide 19 nMOS Linear I-V Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds t W mCox L V V Vds gs t 2 V Vgs Vt ds Vds 2 4: CMOS Transistor Theory V ds CMOS VLSI Design W = mCox L Slide 20 nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current I ds 4: CMOS Transistor Theory CMOS VLSI Design Slide 21 nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current Vdsat I ds Vgs Vt Vdsat 2 4: CMOS Transistor Theory CMOS VLSI Design Slide 22 nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current Vdsat I ds Vgs Vt 2 V 2 gs Vt 4: CMOS Transistor Theory V dsat 2 CMOS VLSI Design Slide 23 nMOS I-V Summary Shockley 1st order transistor models 0 Vds I ds Vgs Vt 2 2 Vgs Vt 2 4: CMOS Transistor Theory Vgs Vt V V V ds ds dsat Vds Vdsat CMOS VLSI Design cutoff linear saturation Slide 24 Example We will be using a 0.6 mm process for your project – From AMI Semiconductor – tox = 100 Å 2.5 V =5 2 – m = 350 cm /V*s 2 – Vt = 0.7 V 1.5 V =4 Plot Ids vs. Vds 1 V =3 – Vgs = 0, 1, 2, 3, 4, 5 0.5 V =2 – Use W/L = 4/2 l V =1 0 Ids (mA) gs gs gs gs gs 0 3.9 8.85 1014 W W W mCox 350 120 m A /V 2 8 L L 100 10 L 4: CMOS Transistor Theory CMOS VLSI Design 1 2 3 4 5 Vds Slide 25 pMOS I-V All dopings and voltages are inverted for pMOS – Source is the more positive terminal Mobility mp is determined by holes – Typically 2-3x lower than that of electrons mn – 120 cm2/V•s in AMI 0.6 mm process Thus pMOS must be wider to provide same current – In this class, assume mn / mp = 2 0 Vgs = -1 Vgs = -2 -0.2 Ids (mA) Vgs = -3 -0.4 Vgs = -4 -0.6 -0.8 -5 Vgs = -5 -4 -3 -2 -1 0 Vds 4: CMOS Transistor Theory CMOS VLSI Design Slide 26 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important – Creates channel charge necessary for operation Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 4: CMOS Transistor Theory CMOS VLSI Design Slide 27 Gate Capacitance Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, ox = 3.90) p-type body 4: CMOS Transistor Theory CMOS VLSI Design Slide 28 Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter – Use small diffusion nodes – Comparable to Cg for contacted diff – ½ Cg for uncontacted – Varies with process 4: CMOS Transistor Theory CMOS VLSI Design Slide 29