Download I DDQ

Digital Testing:
Current Testing
5/23/2017
Based on text by S. Mourad
"Priciples of Electronic Systems"
Problem 1
a) Use Boolean difference to find all tests for E s-a-1 and Esa-0 fault.
b) Find all tests that distinguish between E s-a-0 and D s-a1 faults.
Problem 2
For the circuit shown compute the combinational controllability
and observability in all the signal lines. Use the following
notation (CC0,CC1)CO to indicate your results. For instance, if
the signal x1 has CC0=1, CC1=1 and CO=5, write (1,1)5 next to
the signal name on the figure. Make sure that you consider all
signals (including the branch signals a,b,c,d,e, and f).
Problem 3
Use the critical signal approach to detect C s-a-1 fault. What other
faults can you detect using this run of the critical signal setting? Hint:
start with the output signal Y = 1.
ABCDEFGH26158910Y
Problem 4
Use D-algorithm to find test vector for s-a-0 fault on
the fanout branch h in the circuit shown.
sa0
Outline
Why current testing
Effect on propagation delays
Measurement of current
Test pattern generation
Subthreshold current
Effect of deep submicron
From http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_other/576_applications/30_2219.jpg
Fab. 2, 2001
Copyrights(c) 2001, Samiha Mourad
6
Motivation
Early 1990’s – Fabrication Line had 50 to 1000
defects per million chips
Conventional way to reduce defects:



Increasing test fault coverage
Increasing burn-in coverage
Increase Electro-Static Damage awareness
New way to reduce defects:

IDDQ Testing – also useful for Failure Effect Analysis
What is Current Testing?
Also called IDDQ Testing
Measurement of the supply, VDD,
quiescent current
the sum of all off-state transistors
Useful only for CMOS circuits
Limitation due to shrinking technology
Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus
Current Testing Basics
CMOS circuits operate with normally
negligible static current (power)
But, a defect that causes an appreciable
static current can be detected by
measuring the supply current, IDDQ
Technique used since inception of CMOS
technology
Limitation due to shrinking technology
IDDQ Testing
IDD --- Current flow through VDD
Q --- Quiescent state
IDDQ Testing --- Detecting faults by monitoring IDDQ
VDD
IDD
Inputs
CMOS
circuit
Normal IDDQ: ~10-9Amp.
Abnormal IDDQ: >10-5Amp.
Outputs
Advantages of IDDQ Testing
Fault effect is easy to detect
Many realistic faults are detectable
ATPG is relatively simple
Test length is shorter
Built-in current sensing is possible
IDDQ Distribution
Frequency
Good
Mg
Defective
Md
IDDQ
(Md - Mg) should be an easily measurable quantity
How Does it Work?
Apply a test pattern
Wait for the transient to settle down
Measure the current
Needed:
How to generate the patterns
How to measure the current
But, first current characteristics
Dynamic Current
Vout
VOH
Vin
Vout
CL
VOL
t
I
t
Inverter: Good and Faulty IDDQ
A NAND Tree
s
a
z
b
c
d
Measurement requires the current settling down
The effect of the delays shown on the next slide
Current for the NAND Tree
IDDQ Measurement
Measurement may interfere with the measured
current
A successful measurement should be:
easily placed between the CUT and the bypass Capacitor of
the power pin
Capable of measuring small currents
Non intrusive, no drop of VDD
Fast measurement few ns per pattern
Two types: on- and off-chip
External Measurement
V
Vdd
CUT
R
(a)
P ower
Supply
t
(b)
t
Problem: CUT sensitive to power supply drop on R
Current Sensing Structures
R
Power
Supply
CUT
Sense amplifiers designed
to minimize the VDD
voltage drop
(a)
R
R
(b)
Shunting by diode limits
the voltage drop to 0.7V
Another option is to use pass
transistor
Internal Measurement
I
When large IDDQ exists, V>VR and
Fail flag is set.
VDD-GND Shorts
Vdd
Bridging Faults
IC
DUT
Vref
VGND
V.drop
Comparator
Gate oxide
pinholes
Floating gates &
junction leakages
VGND
No defect
(a)
GND
(b)
No
defect
Defect
Vref
BICS Based on Bipolar Transistor
VDD
VDD
CMOS
Pass/Fail
Flag
Module
VR
V
f1
f1
VR
+ -
f2
CMOS
Module
V
Virtual
Ground
Switching
circuit
I
GND
The switching circuit may switch off a
faulty module to prevent large power
consumption
Fault
categories
V
Analysis of a Short
Consider p-MOS with
input B stuck-on (B s/0)
Transistor is always on
Z = AB + C
A
B
Z
A
C
B
(a)
(b)
Vdd
Vdd
Vdd
Vdd
IDDQ
A=B=0
A=0 B=1
A=1 B=0
A=1 B=1
(c)
For the shorted pMOS transistor, find:
a path form VDD to GND through this transistor, then
AB = 11 is needed to detect this short using IDDQ
Detecting Short Faults
C
C
Z
A
B
Z
A
B
(a)
(b)
a) To detect leakage between gate and source B set A=0 and C=1
b) To detect leakage between gate and drain B set A=1 and C=0
Test Pattern Generation (TPG)
Mainly two methods:
based on switch level using graph
representation as for layout
based on leakage fault models
Graph or Switch Based TPG
Vdd
NAND Gate
Z
A
A
Vdd
B
Z
A
Z
B
A
C
A
C
B
A
B
Z
B
C
GND
B
GND
n-graph
(a)
(b)
p-graph
The combined
graph
(c)
Path A,A,B to test shorts on A transistors
Path B,A,B to test shorts on B transistors
Leakage Fault Model
sg
bs
dg
bg
bd
sd
IO bg bd bs ds gd
00 0 0 0 0 0
01 n y n n y
10 y n n n y
11 0 0 0 0 0
gs
0
n
y
0
pMOS model
N
00
22
43
00
Assuming all possible shorts between
the four nodes, bulk, source, gate, and
drain results in 6 tuples of faults (bg
bd bs ds gd gs )
Consider various I/O patterns
Only correct logic signal values are
used for leakage models. Some I/O
combinations are impossible for a
given logic, for instance 00, 11
The 6 tuples are represented by octal
numbers as shown in column N of the
table
For instance for I/O=10 transistor
fault code is N=438=100011
and represents the following faults:
bg, gd, gs
Characterizing a NAND
The leakage fault model notation is used to characterize
a 2-input NAND
Octal fault vector code
for each transistor
A
P1
B
P2
Z
O
A
N1
C
B
N2
(a)
K
0
1
2
3
4
5
6
7
N1
0
22
0
26
0
70
43
0
N2 P1
0 0
0 43
0 0
43 43
0 0
26 0
43 26
0 0
P2
0
43
0
0
0
43
26
0
(b)
I/O octal code, eg.:
6=110=>A=1,B=1,O=0
Characterizing a NOR
IDDQ Vector Selection
Characterize each logic component using switch-level
simulation – relate input/output logic values & internal
states to:
 leakage fault detection
 weak fault sensitization and propagation
Store information in leakage and weak fault tables
Generate complete stuck-at fault tests
Logic simulate stuck-at fault tests – use tables to find
faults detected by each vector to select vectors for
current measurement
Impact of Deep Submicron
10-6
Drain Current (I D), A
Deep submicron
transistors work at
lower Vt
The lower Vt the higher
IDDQ
The discrepancy
between the faulty and
non-faulty IDDQ is
narrowing
10-8
Ioff
10-10
Ioff
10-12
-0.5
0
0.5
Gate-Source voltage (V
1.0
GS
),V
1.5
Controlling leakage IDDQ
Reverse biasing the substrate
Cooling the devices
Using dual threshold voltage
Partitioning the circuit to manageable IDDQ
Change of Current with
Body Bias and Temperature
Normalized IDDQ to IDDQ of 0.18um
Gate at 150C without Body Bias
1.E+01
1.E+00
1.E-01
Inverter with input state of 0
Lg=.18u @150C
Lg=.25u @150C
Lg=.18u @25C
Lg=.25u @25C
Lg=.18u @-50C
Lg=.25u @-50C
150C
25C
1.E-02
1.E-03
-50C
1.E-04
-3.5
-2.5
-1.5
Vbs (V)
-0.5
0.5
Stuck-open Faults
To test a/1 use vectors
A stuck
A
open
transistor
is always off
A B C D Out
D
B
x
C
y
T1 = 1 1 1 1 0
T2 = 0 0 0 1 ?
Out
A
B
D
C
When T2 is applied (and transistor A
is open), charge sharing among x, y
and Out occurs, and logic state is
undetermined.
Yet the following inverter will draw a
significant current and IDDQ detects
this fault.
Other Faults Detectable by IDDQ
• Gate-oxide short
• Most stuck-at faults
• Latch-up
• Delay faults
• Any other fault due to extra conductor, missing
isolating layer, excess well/substrate leakage,
etc.
Circuit Constraints
To ensure IDDQ detectability, two conditions
must be satisfied:
1. Normal IDDQ must be small
2. Faults must result in large IDDQ
A Good Circuit that may be
identified as Faulty
A=011
B=110
x=11?
large
current
Sel=0 if AB=10
z=x0?
1
MUX
0
Output
When the third pattern AB=10 is applied, change sharing
between x, z occurs, and a large current may exist in the
inverter. However the output is still correct.
Problem due to high impedance node
A bridging fault (BF)
that cannot be Detected by IDDQ
a
0


x
y
y


1
x
b


=1: a=0, b=1
=1: Eventually x=y (and will set to full VDD or GND value as one
signal will dominate), no big current
Problem due to feedback loop
Problems with Dynamic Logic
f
o
a
f
O
p
x
Inputs
y
f
b
Problems: 1. Large current in normal circuits due to
charge sharing
2. Very few faults are detected because of the
precharge property (no direct path VDD-GND)
3. Fault masking of BF(a, b) due to BF(o, p)
Transistor Group
Output
G3
G2
Transistor group (TG) --"Channel-connected
component"
A
Connections between two
TGs are unidirectional
B
G1
C
E
D
Control direction or loop
can be defined
A Minimum Set of Design & Test Rule
for IDDQ Testing
A1. Gate and drain (or source) nodes of a transistor are not in
the same TG.
A2. No conducting path exists from VDD to GND during steady
state.
A3. Each output of a TG is connected to VDD or GND during
steady state.
A4. No control loops among TGs exist.
A5. The bulk (or well) of an n-(p-)type transistor is connected
to GND (VDD).
A6. During testing, each PI is controlled by a monitored power
source.
Results of Design & Test Rules
Theorem 1: All irredundant single BFs in a circuit satisfying
A1-A6 can be detected using IDDQ testing.
Theorem 2: For a circuit satisfying A1-A6, a test detecting a
single BF f also detects all multiple BFs that
contain f.
Theorem 3: If any one of A1-A6 is removed, then circuits
exist for which IDDQ testing cannot give correct
test results.
Strategies for dealing with circuits not satisfying each rule
are required to ensure IDDQ detectability.
Fault Simulation in IDDQ
1. Fault models --- Bridging, break, stuck-open,
stuck-at ?
2. Fault list generation --- need inductive fault
analysis
3. Fault coverage ?
4. Easy for bridging and stuck-on faults
5. Difficult for break and stuck-open faults
6. Stuck-at faults may or may not be modeled as
short to VDD or GND
Fault simulation for BFs
If A1-A6 are satisfied, then fault simulation is
quite simple
1. Perform a good circuit simulation for the
given test pattern.
2. Any BF between a node with logic 1 and a
node with logic 0 is detected.
No simulation on faulty circuit is needed.
No fault list enumeration is needed.
Test Generation
1. Conventional test generation for stuck-at faults
can be modified to detect BFs.
2. No fault propagation.
3. Must make sure the faults result in a conducting
path between VDD and GND.
Switch level test generation may be necessary.
4. Break and stuck-open faults are difficult to detect.
Test generator for bridging faults
Again, assume A1-A6 are satisfied
1. For the bridging fault BF (a, b) to be detected,
add an XOR gate with its inputs connected to
a and b.
2. The test generator work is simply to set the
output of the XOR gate to 1.
No Fault propagation.
Current monitoring Techniques
ATE
ATE
Current Supply
Monitor
BICS
DUT
DUT
CUT
External
monitoring
Test
Fixture
Built-In
Current Sensor
External Devices
TEST POWER SUPPLY
RM
S (STROBE)
VDD
VDD pin
N
IDD
CN
Transistor conducts in
normal mode and
is open in test mode
DUT
VSS pin
Problems:
1. Current resolution is limited.
2. Test equipment must be modified.
3. Current cannot be measured at the full speed of the tester.
4. Cannot partition circuit.
Built-in Current Sensors (BICSs)
VDD
VDD
Test
BICS
Pass
/Fail
Inputs
CUT
Outputs
OR
Inputs
CUT
Outputs
Test
BICS
Pass /Fail
Sometimes called ISSQ testing
BICS Based on Logic Threshold
Favalli (JSSC-90)
VDD
Pullup
VDD
VDD
Pullup
inputs
Pullup
...
Pulldown
Pulldown
t
Normal : t = 1
Test
:t=0
For correct operation
No path to VDD from
gates of MTD transistors
tout = 1 if no fault
= 0 if fault exists
Pulldown
...
MT
MT
Gnd
MT
...
MTD
Gnd
tout
MTD
MTD
Gnd
Improvement on Favalli's design
VDD
Pullup
VDD
VDD
Pullup
inputs
Pullup
...
Pulldown
Pulldown
Pulldown
...
t
MT
tout
Merge all MT and MTD
respectively
MTD
Gnd
Improvement on Favalli's Design
VDD
Pullup
VDD
VDD
Pullup
inputs
Pullup
...
Pulldown
Pulldown
Pulldown
...
MT
tout
Using BiCMOS design
MTD
Gnd
BICS Based on Dual Power Supply &
Operational Amplifier
VDD'=5V
RS
-
Virtual
Short
IRS
I-
+
I+
VoutIDD
VSS
Vin=3V
Vout+
VDD=3V
Threshold detector
CUT
Fault indication
Virtual short
VDD~Vin
Infinite input impedance of OP
I-=0 and IRS=IDD
BICS Based on Current Conveyor
Iz
Virtual
Short
V'DD=5V
Current Conveyor
Ix
VDD
Iy
Threshold
Detector
Fail/Pass
CUT
Virtual short
Current Conveying
VDD ~ VDD'
Iy ~ Ix
Advantages of Built-In Current Sensors (BICS)
• Higher test rate compared to external devices
• Easier to partition circuits
• Easier to control current resolution
• Suitable for mixed-mode circuits
• Built-In self test capability achievable
• Lower test equipment cost
• On-Line testing possible
Disadvantages of BICS
• Impact on circuit performance
• Reliability of itself
• Area overhead
• Power consumption
HP and Sandia Lab Data
HP – static CMOS standard cell, 8577 gates, 436 FF
Sandia Laboratories – 5000 static RAM tests
Reject ratio (%) for various tests:
Reject ratio (%)
Company
IDDQ
HP
Sandia
Without IDDQ
With IDDQ
Without IDDQ
With IDDQ
No
Test
16.46
0.80
Only
Funct.
6.36
0.09
Only
Scan
6.04
0.11
Functional Tests
5.562
0
Both
5.80
0.00
Failure Distribution in
Hewlett-Packard Chip
Sematech Study
IBM Graphics controller chip – CMOS ASIC, 166,000
standard cells
0.8μ static CMOS, 0.45μ lines (Leff), 40 to 50 MHz clock, 3
metal layers, 2 clocks
Full boundary scan on chip
Tests:
 Scan flush – 25 ns latch-to-latch delay test
 99.7 % scan-based stuck-at faults (slow 400 ns rate)
 52 % SAF coverage functional tests (manually created)
 90 % transition delay fault coverage tests
 96 % pseudo-stuck-at fault coverage IDDQ tests
Sematech Conclusions
Hard to find point differentiating good and bad devices
for IDDQ & delay tests
High # passed functional test, failed all others
High # passed all tests, failed IDDQ > 5 mA
Large # passed stuck-at and functional tests
 Failed delay & IDDQ tests
Large # failed stuck-at & delay tests
 Passed IDDQ & functional tests
Delay test caught failures in chips at higher
temperature burn-in – chips passed at lower
temperature
Current Limit Setting
Should try to get it < 1 mA
Histogram for 32 bit microprocessor
Delta IDDQ Testing (Thibeault)
Use derivative of IDDQ at test vector i as current
signature
ΔIDDQ (i) = IDDQ (i) – IDDQ (i – 1)
Leads to a narrower histogram
Eliminates variation between chips and between
wafers
Select decision threshold Δdef to minimize
probability of false test decisions
|IDDQ| and |IDDQ|
Setting Threshold
IDDQ
ΔIDDQ
Mean (good chips)
0.696 μA
-2×10-4 μA
Mean (bad chips)
1.096 μA
0.4 μA
Variance
0.039 (μA)2
0.004 (μA)2
Δdef
Error Prob.
Error Prob.
0.3
0.059
7.3×10-4
0.4
0.032
4.4×10-5
0.5
0.017
1.7×10-6
Summary
IDDQ test is used as a reliability screen
Can be a possible replacement for expensive burn-in
test
IDDQ test method has difficulties in testing of sub-micron
devices
 Greater leakage currents of MOSFETs
 Harder to discriminate elevated IDDQ from 100,000
transistor leakage currents
ΔIDDQ test may be a better choice
Built-in current (BIC) sensors can be useful