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Roadmap for Carbon Nanotubes and Graphene ITRS Logic Workshop Tsukuba, Japan George Bourianoff facilitating Sept 23, 2008 Workshop and Business Meeting Objectives (Sept. 22 – 23) Layout roadmap for Carbon Nanotubes and Graphene for “Ultimately Scaled CMOS” and “Beyond CMOS”. Build on results from July ERD meetings. – – Provide information needed to develop new Memory Table entries for STT RAM (new TE for 2009). Determine content for 2009 ERD logic section – – – Review Technology Entries (TEs) from 2007 Review potential TE adds/drops for 2009 Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections – Ultimate CMOS roadmap – potential solution (PIDS Role?) Beyond CMOS roadmap entry – current ERD format? How can we improve the integration? (e.g. joint workshops, key materials properties table, …) Approximate timeline for 2009 ERD Business meeting Agenda • Review objectives, desired outcome and timeline of roadmapping exercise • Present and discuss strawman structure based on ITRS “potential solution format” • Discuss table contents (Technology Entries) • Discuss next steps Objectives • Identify infrastructure requirements and gaps to fabricate industrially relevant, carbon based prototype devices with timeline • Identify key infrastructure requirements neede to develop new functionalities of carbon based electronics with timeline Scope of roadmap discussion Integrate with other known technology roadmaps to achieve commercial viability Identify critical infrastructure requirements to fabricate industrially relevant prototypes Identify existing infrastructure & infrastructure gaps Decide roadmap format – e.g. potential solution format – – Decide major technology entries Determine approximate timelines 5 ERD WG 9/22-23/08 Work in Progress --- Not for Publication Carbon-based Nanoelectronics Workshop Agenda 9:30 Introduction 9:40 “Theory of electronic states and transport in graphene and nanotube” 10:30 “Graphene conduction control by gate voltage 11:20 “Epitaxial graphene on Si substrate mediated by an ultra-thin SiC layer” 12:10 Lunch 13:00 “Evaluation of number of graphene layers grown on SiC” 13:50 “Beyond-CMOS applications of graphene based nanoelectronics” 14:40 Summary 15:00 Spin Torque Transfer RAM Workshop 6 ERD WG 9/22/08 Dr. Y. Awano (Fujitsu) Prof. T. Ando (Tokyo Inst. Tech) Dr. K. Tsukagoshi (AIST) Prof. M. Suemitsu (Tohoku U.) Dr. H. Hibino (NTT) Prof. P. Kim (Columbia U.) Dr. Y. Awano (Fujitsu) Dr. U-In Chung (Samsung) Work in Progress --- Not for Publication Proposed roadmap format • Build on ITRS “potential solution” format • Separate into FET driven requirements and novel device infrastructure requirements • Tie closely and directly to ERM ERM table of applications vs TWIG Table ERM2 MATERIALS ERD MEMORY Applications of Emerging Research Materials ERD LOGIC LITHOGRAPHY FEP INTERCONNECTS Nanotube Macromolecules Nano-mechanical Memory Molecular memory Nanowire Graphene and graphitic structures Molecular devices Self Assembled Materials Nanotubes High-index immersion liquids Resists Imprint polymers Metal nanowires Novel cleans Selective etches Low-κ ILD Selective depositions Sub- lithographic patterns Selective etch Enhanced dimensional control Deterministic doping Selective deposition Electrical applications Thermal applications Mechanical applications Polymer electrical and thermal/ mechanical property control Selective etch High performance Selective deposition capacitors Semiconductor spin transport Spin Materials MRAM by spin injection Ferromagnetic (FM) semiconductors FM metals Tunnel dielectrics Passivation dielectrics Complex Metal Oxides Interfaces and Heterointerfaces 1T Fe FET Fuse-anti-fuse Electrical and spin contacts and interfaces Multiferroics (Spin materials) High performance capacitors Novel phase change Electrical and spin contacts and interfaces Contacts and interfaces Insert new column here?? Low Dimensional Materials ASSEMBLY AND PACKAGE Proposed structure - table 1 First Year available for Production 2009 2010 45nm 2011 2012 2013 32nm 2014 2015 2016 22nm 2017 2018 2019 16nm 2020 2021 Materials & Processes for Carbonbased Nanoelectronics CNTs density (pitch) growth control doping contacting alignment variability Graphene Manufacturable deposition patterning edge effects contacting dielectrics bilayers variability This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Development Underway Qualification / Pre-Production Continuous Improvement 2022 11nm 2023 2024 Proposed structure –table 2 Carbon-based Nanoelectronics Devics Digital CNTFET Analog CNTFET digital GNRFET Analog GNRFET bilayer devices Quantum interference devices This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Development Underway Qualification / Pre-Production Continuous Improvement Discussion on table structure • Recognizes need for improved samples regardless of specific applications • Recognizes that some applications will drive special needs e.g. FETs • Will this structure accomplish our objective? • Is there a better structure Table contents General Requirements CNTs density (pitch) growth control doping contacting alignment variability Graphene Manufacturable deposition patterning edge effects contacting dielectrics bilayers variability Device Specific Requirements Digital CNTFET Analog CNTFET digital GNRFET Analog GNRFET bilayer devices Quantum interference devices Graphene SETs Quantum Hall devices Timeline • • • • • Circulate proposal to entire group Merge all inputs in December Solicit volunteers for specific topics Schedule regular meetings in spring Output in time for spring meeting Content of 2009 ERD Logic section ITRS Logic Workshop Tsukuba, Japan George Bourianoff facilitating Sept 23. 2008 Workshop and Business Meeting Objectives (Sept. 22 – 23) Layout roadmap for Carbon Nanotubes and Graphene for “Ultimately Scaled CMOS” and “Beyond CMOS”. Build on results from July ERD meetings. – – Provide information needed to develop new Memory Table entries for STT RAM (new TE for 2009). Determine content for 2009 ERD logic section – – – Review Technology Entries (TEs) from 2007 Review potential TE adds/drops for 2009 Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections – Ultimate CMOS roadmap – potential solution (PIDS Role?) Beyond CMOS roadmap entry – current ERD format? How can we improve the integration? (e.g. joint workshops, key materials properties table, …) Approximate timeline for 2009 ERD Business meeting 15 ERD WG 9/22-23/08 Work in Progress --- Not for Publication Objectives • • • • • Determine content for 2009 ERD logic section Review Technology Entries (TEs) from 2007 Review potential TE adds/drops for 2009 Solicit writing volunteers for 2009 Discuss linkage to materials and architecture sections • How can we improve the integration? (e.g. joint workshops, key materials properties table, …) • Approximate timeline for 2009 • ERD Business meeting High performance logic table 2007 Device FET [A] Typical example devices Si CMOS FET Extension 1D structures Channel replacement CNT FET III-V compound semiconductor and NW FET Ge channel NW heteroreplacement structures SET Molecular SET Crossbar latch Molecular transistor Molecular QCA Ferromagnetic logic Moving domain wall M: QCA Spin Gain transistor Spin FET Nanoribbon transistors with graphene Cell Size (spatial pitch) [B] Density 2 (device/cm ) Spin transistor Spin Torque Transistor Projected 100 nm 100 nm [D] 300 nm [I] 40 nm [O] 10 nm [U] 140 nm [Y] 100 nm [C] Demonstrated 590 nm ~1.5 m [E] 1700 nm [J] ~200 nm [K, L] ~2 m [V] 250 nm [Z, AA] 100 m [AB] Projected Demonstrated Projected Demonstrated Projected Demonstrated 1E10 2.8E8 12 THz 1.5 THz 61 GHz 5.6 GHz 4.5E9 4E7 6.3 THz [F] 200 MHz [G] 61 GHz [C] 220 Hz [H] 6.1E9 3.5E7 >1 THz >300 GHz 61 GHz [C] Data not available 1E12 2E7 1 THz [W] 100 Hz [V] 1 GHz [U] 100 Hz [V] 5E9 1.6E9 1 GHz [Y] 30 Hz [Z, AA] 10 MHz [Y] 30 Hz [Z] 4.5E9 1E4 40 GHz [AC] Not known Not known Not known Projected 3E-18 3E-18 3.00E-18 5E-17 [X] ~1E-17 [Z] 3E-18 Demonstrated 1E-16 1E-11 [H] 1E-16 [J] 6E10 ~2E9 10 THz [Q] 2 THz [R] 1 GHz [O] 1 MHz [P] 1×10–18 [O] [>1.5×10–17 ] [S] –17 8×10 [T] 3E-7 [V] 6E-18 [AA] Not known Projected 238 238 61 10 1000 5E-2 Not known Demonstrated 1.6 1E-8 Data not available 2E-4 2E-9 5E-8 Not known Operational Temperature RT RT RT [M, N] RT RT RT Materials System Si RT CNT, Si, Ge, III-V, In2O3, ZnO, TiO2, SiC, 379 InGaAs, InAs, InSb III-V, Si, Ge, Organic molecules Ferromagnetic alloys Si, III-V, complex metals oxides 62 91 244 32 122 Switch Speed Circuit Speed Switching Energy, J Binary Throughput, 2 GBit/ns/cm Research Activity [AD] [>1.3×10 –14 ] [S] 2007 Technology Entries – High Performance • Extensions to CMOS - Low dimensional structures previously included Carbon Nanotube FETs, nanowire FETs, and Nanowire heterostructures. This edition will also include nanoribbon devices using graphene.. • 2. Extensions to CMOS - High mobility channel replacement FETs including III-V and Ge channel replacement • 3. Single electron devices discussion had similar scope to previous editions • 4. Molecular devices had similar scope to previous editions with primary focus on molecule on CMOS architecture (CMOL) concept • 5. Ferromagnetic logic devices are based on collective magnetic effects associated with the magnetic polarity of a nanodomain. • 6. Spin devices are based on spin dynamics of one or a few electrons, defects, or nuclei 2007 Alternative Device Table Resonant Tunneling Diodes Multi-ferroic Tunnel Junctions Single Electron Transistors Molecular Devices Ferro-Magnetic Devices Frequency Coherent Spin Devices State Variable Charge Dielectric and magnetic domain polarization Charge Molecular conformation Ferromagnetic polarization Precession frequency Response Function Negative differential resistance Four resistive states Staircase I/V from Coulomb blockade Hysteretic Nonlinear Nonlinear Class— Example Mobile Multi-ferroic tunnel junction Voltage tunable transfer function CMOL, cross bar latch Amplifiers, buses, switches Spin torque oscillator Architecture Heterogeneous Morphic Heterogeneous, morphic MQCA, morphic Morphic Application Elements in hybrid magneto electric circuits Analog pattern matching Associative processing , NP complete, Elements in hybrid magneto-electric circuits Microwave power, tunable rectifiers Comments Additional functionality Density, functionality Density, cost functionality Radiation hard, environmental rugged RF functionality Status Demo Demo Demo Demo Simulation Material Issues Stray charge RT DMS 2007 Technology Entries Alternative Information Processing • • • • • • 1. 2. 3. 4. 5. 6. Resonant Tunneling Diodes Multi-ferroic Tunnel Junctions Single Electron Transistors Molecular Devices Ferro-Magnetic Devices Frequency Coherent Spin Devices Suggestions received • Include a discussion of hybrid devices – Not sure that makes sense at the device level – Proposal – make the point in the intro that some applications may benefit from a hybrid approach • Include steep subthreshold devices – They are in the transition table – Should we keep them there? • Include MQCA as a category – It already is in the alternative device table – no action needed • Nanocrystal flash devices for logic – It already is in the alternative device table – no action needed 2007 Transition table IN/OUT Rapid Single Flux Quanta (RSFQ) CMOS extension-III-V channel replacements Impact Ionization MOS Nano Electro Mechanical Systems (NEMS) OUT Reason for IN/OUT RSFQ devices, systems and circuits have been developed, prototyped, and fabricated. They could become an important technology if the correct market driver emerges Comment Design and fabrication lines for RSFQ systems exist. Cryogenic operation, cost and material integration issues limit application space IN Low bandgap, compound III-V semiconductors can potentially improve transistor performance Research on compound III-V semiconductors on SI substrates has increased significantly over the last 2 years Possible Future Simulation results showing very low sub threshold slopes indicate potential for low power operation Reliability remains an issue may be included in future editions Possible Future Potential for ultra low leakage device based on nano relay operation Issues associated with stiction, speed, active power and reliability are being studied –may be included in future editions Lateral interband tunneling transistor Possible Future Floating gate MOS devices Possible Future Potential to utilize gate modulated interband tunneling to reduce subthreshold slope Devices with nanocrystals embedded in gate allow circuits with tuneable thresholds. Potential for low power circuits May be included in future editions May be included in future editions New topics for discussion – Should we broaden the “high performance” table to include Low Power” and “Low Standby Power”? (Call it “High Volume” applications?) – Pros • Would align better with ITRS System Drivers • Would reflect motivation of much research • Several recent theoretical and simulation papers support this – Con • Would be orthogonal to the historical “tracking” function of the Table Technology Entries(1) • FET extensions – Low dimension Channel replacement category • Recommend keeping category perhaps emphasizing carbon based components • Discuss CNTFETs with PIDs – High mobility channel replacements • Send III-V and Ge to PIDs • Graphene keep or talk to PIDs SETs • Recommend keeping but emphasize low power application – Pros • A lot of recent work supports that. (Very recent paper by Vishwa Ray at UT Arlington* shows RT operation self aligned process on Si) – Cons • Past efforts have not been fruitful • Stray charge will always be problem Nature of Nanotechnology advance online Molecular • Recommend moving to transition table and keeping in the alternate technology table • Pros – Recent progress has been weak • Cons – Many people believe passionately that it still has great potential Ferromagnetic and spin transistor • Recommend keeping categories but merging them together • Pros – Line between the two entries is becoming blurred as we heard yesterday – Large amount of activity in area (driven currently by memory including embedded) • Cons – ?? New Technology Entries to consider • ??? 2007 Technology Entries Alternative Information Processing • • • • • • 1. 2. 3. 4. 5. 6. Resonant Tunneling Diodes Multi-ferroic Tunnel Junctions Single Electron Transistors Molecular Devices Ferro-Magnetic Devices Frequency Coherent Spin Devices Resonant Tunnel Diodes • Recommend moving to transition table • Pros – Not much progress • Cons – It is an interesting device with NDR – Many people feel passionately about it Multiferroic tunnel junctions • Recommendation – change the category to multiferroic switching elements • Pros – Recent demonstration of RT mutiferroic properties in BFO – Several applications in low power spin wave circuits – Main application would be 4 state logic which is not attractive for other reasons • Cons – ??? Single Electron Transistors • Recommendation- Keep category as it is • Pros – Potential Non Boolean logic applications such as image recognition still receiving attention – Still an active area • Cons – ??? Molecular devices • Recommendation – Keep the category • Pros – Area of intense activity – Driven by nano bio – New applications being constantly proposed • Cons – ???? Ferromagnetic devices • Recommendation – Keep the category – Pros • Area of intense activity • Potential applications and devices outside of Boolean Logic gates • Include Graphene devices – Cons • ???? Coherent spin devices • Recommendation – Keep the category – Pros • Significant activity taking place • Pseuduospintronic devices on bilayer graphene would go here • Spin hall effect devices would go here (also on graphene most likely) – Cons • Single spins at room temperature will never be robust (?) and therfore should drop