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Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits Revised from Digital Integrated Circuits, © Jan M. Rabaey el © Digital Integrated Circuits2nd Sequential Circuits Sequential Logic Inputs Outputs COMBINATIONAL LOGIC Current State Registers Q Next state D CLK 2 storage mechanisms • positive feedback • charge-based © Digital Integrated Circuits2nd Sequential Circuits Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edgetriggered elements flip-flops This leads to confusion however © Digital Integrated Circuits2nd Sequential Circuits Memory elements At high level , memory is classified as background memory and foreground memory. Memory that is embedded into logic is foreground memory. Large amounts of centralized memory core is background memory, which achieves higher area density through efficient use of array structures. Here, we focus on foreground memory elements. © Digital Integrated Circuits2nd Sequential Circuits Latch versus Register Latch stores data when clock is high D Q D Q Clk Clk Clk Clk D D Q Q © Digital Integrated Circuits2nd Register stores data when clock rises or falls Sequential Circuits Latches © Digital Integrated Circuits2nd Sequential Circuits Latch-Based Design • P latch is transparent when f = 1 • N latch is transparent when f = 0 f N Latch Logic P Latch Logic © Digital Integrated Circuits2nd Sequential Circuits Timing Definitions CLK t tsu D D thold DATA STABLE Q CLK t tc 2 Q Register q DATA STABLE t Tsetup: setup time is the time that data input D must be valid before clock transition Thold: hold time is the time that data input D must remain valid after the clock edge Tc2q: propagation delay of copying D to Q output (with respect to clk) © Digital Integrated Circuits2nd Sequential Circuits Characterizing Timing tD 2 D Q Clk tC 2 Q Clk Q Register © Digital Integrated Circuits2nd D Q tC 2 Q Latch Sequential Circuits Maximum Clock Frequency FF’s f tc2q + tp,comb + tsetup <= T Clock period T must accommodate the longest possible delay LOGIC tp,comb Also another constraint: tcdreg + tcdlogic > =thold tcd: contamination delay = minimum delay This constraint ensures the input data of the sequential circuits is held long enough after the clock edge and not modified too soon by the new coming-in data © Digital Integrated Circuits2nd Sequential Circuits Positive Feedback: Bi-Stability Vi2 V o1 V i1 V o2 A V i 2 = V o1 C B V i 1 = V o2 When the gain of inverter in transient region is larger than 1, A & B are the only stable operating points, C is metastable. © Digital Integrated Circuits2nd Sequential Circuits Meta-Stability Gain should be larger than 1 in the transition region Hence, cross coupling of two inverters results in a bistable circuit, that is a circuit with two stable states. The circuit serves as a memory, storing either a 1 or 0 (A or B) © Digital Integrated Circuits2nd Sequential Circuits Bistable circuit In absence of triggering, a bistable circuit remains in a single state (static memory as long as power is on). Another common name for a bistable circuit is flip-flop A FF is only useful when there is a mean to bring it from one state to the other one. Two approaches can achieve that: cutting the feedback loop, once the feedback loop is open, a new value can be written. This is called multiplexer based. Overpowering the feedback loop, by applying a trigger signal at the input of the FF, a new value is forced into the circuit by overpowering the previous stored value. © Digital Integrated Circuits2nd Sequential Circuits Mux-Based Latches Negative latch (transparent when CLK= 0) 1 D CLK Q Clk Q Clk In Q 0 Q 0 © Digital Integrated Circuits2nd Positive latch (transparent when CLK= 1) D 1 CLK Q Clk Q Clk In Sequential Circuits Mux-based Static Latch The most robust and common technique to build a latch is to use transmission-gate multiplexers. Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states CLK Q Clock load is 4, clock activity factor is 1, so more power CLK D © Digital Integrated Circuits2nd CLK Sequential Circuits Mux-Based Latch Clock load reduced to 2 at the cost of static power consumption CLK QM CLK QM CLK CLK NMOS only © Digital Integrated Circuits2nd Non-overlapping clocks Sequential Circuits Static Latch: an alternative CLK I1 D D T1 I2 CLK Eliminating the feedback, we can obtain another implementation of a latch by cross-coupling the inverters. In this case, the transmission gate and source driver D must overpower the feedback to switch the state. So now sizing is important. If minimum-sized devices are used in transmission gates, it is essential that transistors of inverter I2 be made even weaker. © Digital Integrated Circuits2nd Sequential Circuits Master-Slave (Edge-Triggered) Register The most common approach for constructing an edge-triggered Register is to use a master-slave configuration, which consists of cascading a (negative/positive) latch with a (positive/negative) one. © Digital Integrated Circuits2nd Sequential Circuits Master-Slave Register design I2 D T2 I3 I5 T4 I4 T3 I6 Q QM I1 T1 CLK • At low phase of the clock, master stage is transparent and D is passed to QM. (During this time, slave stage is in hold mode, keeping its value using feedback). • On the rising edge, master stage stops sampling and slave starts sampling. • At high phase of the clock, slave samples output QM, while master is in hold mode. Since QM is constant now, Q makes one transition per clock cycle. The value of Q is the value of D right before the rising edge. © Digital Integrated Circuits2nd Sequential Circuits Clk-Q Delay 2.5 Volts CLK 1.5 D Tsetup 0.5 2 0.5 0 © Digital Integrated Circuits2nd tc 2 q(lh) tc 2 q(hl) Q 0.5 1 1.5 time, nsec 2 2.5 Sequential Circuits Setup Time © Digital Integrated Circuits2nd Voltage at input of T2 Sequential Circuits Timing properties of Master-Slave Register (first order estimation) I2 D T2 I3 I5 T4 I4 T3 I6 Q QM I1 T1 CLK Assume inverters have the same delay Tinv and transmission gates have the same delay Ttp Setup time: 2Tinv + Ttp Propagation time: Ttp + 2Tinv Hold time: 0 © Digital Integrated Circuits2nd Sequential Circuits Reduced Clock Load Master-Slave Register CLK D T1 CLK CLK I1 I2 T2 CLK I3 Q I4 Reverse conduction When I4 is a weak device, it is not a major problem Does this problem appear in the previous register? © Digital Integrated Circuits2nd Sequential Circuits Avoiding Clock Overlap Direct path from D to Q CLK CLK Q X A D B Driving the same node CLK CLK (a) Schematic diagram CLK CLK (b) Overlapping clock pairs © Digital Integrated Circuits2nd Problem at 0-0 overlap? Sequential Circuits Avoiding Clock Overlap When clock goes high, master stage should stop sampling the input and go into hold mode. Since CLK and CLK are both high for a short period of time, there is a direct path from D to Q. As a result, Q might change during the overlap period, which is undesired for edge-trigger registers. This is known as a race condition in which Q is a function of whether D arrives at node X before or after the falling edge of the CLK. Also, if there is clock overlap between CLK and CLK, node A can be driven by both D and B, which may result in an undefined state. These problems can be avoided by using two nonoverlapping clocks. © Digital Integrated Circuits2nd Sequential Circuits 2 phase non-overlapping clocks f f D In f f Note: During non-overlap time, both latches are in highimpedance state (feedback loop is open, gain is 0). So, this duration should not be long. f f tf12 © Digital Integrated Circuits2nd Sequential Circuits Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset S R S R Q Q 0 0 Q Q 1 0 1 0 0 1 1 1 0 0 1 0 Q S Q R Q Q Forbidden State Cross-coupled NANDs S Q What if they need to be clocked? © Digital Integrated Circuits2nd R Q Sequential Circuits Ratioed CMOS SR latch VDD M2 M4 Q Q Added clock CLK M6 S M5 M1 M3 M8 CLK M7 R This is not used in datapaths any more, but is a basic building memory cell © Digital Integrated Circuits2nd Sequential Circuits Sizing Issues 2.0 3 Q S W = 0.5 m m 2 W = 0.6 m m W = 0.7 m m Volts Q (Volts) 1.5 1.0 1 W = 0.8 m m 0.5 0.0 2.0 2.5 3.0 W/L 5 and 6 3.5 4.0 (a) 0 W = 1m m W = 0.9 m m 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (b) Output voltage dependence on transistor width Transient response Boundary condition: current equal © Digital Integrated Circuits2nd Sequential Circuits Storage Mechanisms Static latch Dynamic (charge-based) latch CLK CLK Q CLK D Q D CLK CLK A stored value remains valid as long as power supply is applied. Drawback: complexity © Digital Integrated Circuits2nd Temporary storage of charge on parasitic capacitors, similar to dynamic logic. Periodic refresh may be necessary. Sequential Circuits Dynamic transmission gate register CLK CLK B A D CLK Q=D CLK This implementation is very efficient since it requires only 8 transistors (6 if NMOS only switches). The reduced transistor count is attractive for high-performance data path. Setup time: Ttp Propagation time: Ttp + 2Tinv Hold time: 0 © Digital Integrated Circuits2nd Sequential Circuits Correct operation of dynamic register CLK CLK D Q CLK CLK Positive-edge triggered register Since registers are periodically clocked, the storage nodes are constantly updated. Clock overlap might be an important concern. During 0-0 overlap period, a direct path for data flow from D to Q exists (a race condition occurs). The same is true for 1-1 overlap period. 0-0 overlap can be addressed if there is enough delay between D input and Q. 1-1 overlap can be taken care of by enforcing that the hold time larger than the overlap duration. © Digital Integrated Circuits2nd Sequential Circuits Correct operation of dynamic register CLK CLK D Q CLK CLK Positive-edge triggered register CLK CLK © Digital Integrated Circuits2nd Ensure enough delay Hold time constraint Sequential Circuits 2-phase dynamic register f f In D Input Sampled f f Output Enable © Digital Integrated Circuits2nd Sequential Circuits Making a Dynamic Latch Pseudo-Static CLK D D CLK Dynamic register is very appealing from perspectives of complexity, performance and power consumption. But robustness limit its use. The storage node is prone to coupling, noise and leakage. Fortunately, most of the problems can be adequately addressed by adding a weak feedback inverter and making it pseudostatic (at slight cost of delay). © Digital Integrated Circuits2nd Sequential Circuits More Precise Setup Time © Digital Integrated Circuits2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 D Inv2 SM D1 QM Clk-Q Delay Inv1 CP TClk-Q TSetup-1 Data Time Clock TSetup-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 D Inv2 SM D1 QM Clk-Q Delay Inv1 CP TClk-Q TSetup-1 Data Time Clock TSetup-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 D Inv2 SM D1 QM Clk-Q Delay Inv1 CP TClk-Q TSetup-1 Data Time Clock TSetup-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 D Inv2 SM D1 Clk-Q Delay QM Inv1 TClk-Q CP TSetup-1 Data Time Clock TSetup-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 D Inv2 SM D1 Clk-Q Delay TClk-Q QM Inv1 CP TSetup-1 Data Time Clock TSetup-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Setup/Hold Time Illustrations Hold-1 case CN TG1 SM D1 D Inv2 Clk-Q Delay QM Inv1 CP 0 TClk-Q THold-1 Clock Data THold-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Time Setup/Hold Time Illustrations Hold-1 case CN TG1 SM D1 D Inv2 Clk-Q Delay QM Inv1 CP 0 TClk-Q THold-1 Clock Data THold-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Time Setup/Hold Time Illustrations Hold-1 case CN TG1 SM D1 D Inv2 Clk-Q Delay QM Inv1 CP 0 TClk-Q THold-1 Clock Data THold-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Time Setup/Hold Time Illustrations Hold-1 case CN TG1 SM D1 D Inv1 Inv2 Clk-Q Delay QM TClk-Q CP 0 THold-1 Clock Data THold-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Time Setup/Hold Time Illustrations Hold-1 case CN TG1 SM D1 D Inv2 Clk-Q Delay QM TClk-Q Inv1 CP 0 THold-1 Clock Data THold-1 t=0 © Digital Integrated Circuits2nd Time Sequential Circuits Time Other Latches/Registers: 2 C MOS Clock overlap insensitive register: embed clock signal in VDD VDD the inverter M2 CLK M6 M4 CLK M8 X D CLK M3 M1 Master Stage Q CL1 CLK M7 CL2 M5 Slave Stage “Keepers” can be added to make circuit pseudo-static © Digital Integrated Circuits2nd Sequential Circuits Insensitive to Clock-Overlap 0 VDD VDD VDD VDD M2 M6 M2 M6 M4 0 M8 X D Q X D 1 M1 M5 (a) Equivalent circuit in (0-0) overlap X can make only 0->1 transition, but can not make it to Q © Digital Integrated Circuits2nd M3 M1 Q 1 M7 M5 (b) Equivalent circuit (1-1) overlap No direct path from D to Q CLK CLK Overlapping clock pairs Sequential Circuits C2MOS The circuit is insensitive to clock overlaps since overlaps activate either the pull-up or the pull-down network in master/slave stage (never both) One potential problem is slow rise and fall of the clocks, where both NMOS and PMOS are on. This could create a path between input and output that can destroy the state. CLK CLK Timing (delay) characteristics may be improved compared to transmission-gate-based static register. © Digital Integrated Circuits2nd Sequential Circuits